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features ? incorporates the arm926ej-s ? arm ? thumb ? processor ? dsp instruction extensions, arm jazelle ? technology for java ? acceleration ? 8 kbyte data cache, 16 kbyte instruction cache, write buffer ? 200 mips at 180 mhz ? memory management unit ? embeddedice ? , debug communication channel support ? additional embe dded memories ? one 32 kbyte internal ro m, single-cycle access at maximum matrix speed ? one 32 kbyte (for at91sam9xe256 and at91sam9xe512) or 16 kbyte (for at91sam9xe128) internal sram, single-cycle access at maximum matrix speed ? 128, 256 or 512 kbytes of internal high-speed flash fo r at91sam9xe128, at91sam9xe256 or at91sam9xe512 respectively. organized in 256, 512 or 1024 pages of 512 bytes respectively. ? 128-bit wide access ? fast read time: 45 ns ? page programming time: 4 ms, including page auto-erase, full erase time: 10 ms ? 10,000 write cycles, 10 years data rete ntion, page lock capabilities, flash security bit ? enhanced embedded flash controller (eefc) ? interface of the flash block wi th the 32-bit internal bus ? increases performance in arm and thum b mode with 128-bit wide memory interface ? external bus interface (ebi) ? supports sdram, static memory, ecc- enabled nand flash and compactflash ? ? usb 2.0 full speed (12 mbit s per second) device port ? on-chip transceiver, 2,688-byte configurable integrated dpram ? usb 2.0 full speed (12 mbits per second) host single port in the 208-pin pqfp device and double port in 217-ball lfbga device ? single or dual on -chip transceivers ? integrated fifos and dedicated dma channels ? ethernet mac 10/100 base-t ? media independent interface or re duced media independent interface ? 128-byte fifos and dedicated dma channels for receive and transmit ? image sensor interface ? itu-r bt. 601/656 external interface, programmable frame capture rate ? 12-bit data interface for support of high sensibility sensors ? sav and eav synchronization, prev iew path with scaler, ycbcr format ? bus matrix ? six 32-bit-layer matrix ? remap command ? fully-featured system controller, including ? reset controller, shutdown controller ? four 32-bit battery backup regi sters for a total of 16 bytes ? clock generator and power management controller ? advanced interrupt controller and debug unit ? periodic interval timer, watchdog timer and real-time timer at91 arm thumb microcontrollers at91sam9xe128 at91sam9xe256 at91sam9xe512 preliminary 6254b?atarm?29-apr-09
2 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? reset controller (rstc) ? based on a power-on reset cell, reset sour ce identification and reset output control ? clock generator (ckgr) ? selectable 32,768 hz low-power oscillat or or internal low power rc oscillator on battery backup power supply, providing a permanent slow clock ? 3 to 20 mhz on-chip oscillator, one up to 240 mhz pll and one up to 100 mhz pll ? power management controller (pmc) ? very slow clock operating mode, software programmable power optimization capabilities ? two programmable external clock signals ? advanced interrupt controller (aic) ? individually maskable, eight-level pr iority, vectored interrupt sources ? three external interrupt sources and one fast interrupt source, spurious interrupt protected ? debug unit (dbgu) ? 2-wire uart and support for debug communicatio n channel, programmable ice access prevention ? mode for general purpose two-wi re uart serial communication ? periodic interval timer (pit) ? 20-bit interval timer plus 12-bit interval counter ? watchdog timer (wdt) ? key-protected, programmable only once, window ed 16-bit counter running at slow clock ? real-time timer (rtt) ? 32-bit free-running backup counter runn ing at slow clock with 16-bit prescaler ? one 4-channel 10-bit analog to digital converter ? three 32-bit parallel input/output controllers (pioa, piob, pioc,) ? 96 programmable i/o lines multiplexed with up to two peripheral i/os ? input change interrupt ca pability on each i/o line ? individually programmable open-drain, pull-up resistor and synchronous output ? peripheral dma controller channels (pdc) ? two-slot multimedia card interface (mci) ? sdcard/sdio and multimediacard ? compliant ? automatic protocol control and fast automatic data transfers with pdc ? one synchronous serial controllers (ssc) ? independent clock and frame sync sign als for each receiver and transmitter ? i2s analog interface support, time division multiplex support ? high-speed continuous data stream ca pabilities with 32-bit data transfer ? four universal synchron ous/asynchronous receive r transmitters (usart) ? individual baud rate generator, irda ? infrared modulation/demodulatio n, manchester encoding/decoding ? support for iso7816 t0/t1 smart card, hardware handshaking, rs485 support ? full modem signal control on usart0 ? one 2-wire uart ? two master/slave serial peripheral interface (spi) ? 8- to 16-bit programmable da ta length, four external peripheral chip selects ? synchronous communications ? two three-channel 16-bit timer/counters (tc) ? three external clock inputs, two multi-purpose i/o pins per channel ? double pwm generation, capture/waveform mode, up/down capability ? high-drive capability on outputs tioa0, tioa1, tioa2 ? two two-wire interfaces (twi) ? master, multi-master and slave mode operation ? general call supported in slave mode ? connection to pdc channel to optimize data transfers in master mode only
3 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? ieee ? 1149.1 jtag boundary sc an on all digital pins ? required power supplies: ? 1.65v to 1.95v for vddbu, vddcore and vddpll ? 1.65v to 3.6v for v ddiop1 (peripheral i/os) ? 3.0v to 3.6v for vddiop0 and vdda na (analog-to-digital converter) ? programmable 1.65v to 1.95v or 3.0v to 3.6v for vddiom (memory i/os) ? available in a 208-pin pqfp green and a 217-ball lfbga green package 1. at91sam9xe128/256/512 description the at91sam9xe128/256/512 is based on the integration of an arm926ej-s processor with fast rom and ram, 128, 256 or 512 kbytes of flash and a wide range of peripherals. the embedded flash memory can be programmed in-system via the jtag-ice interface or via a parallel interface on a production programmer prior to mounting. built-in lock bits a security bit and mmu protect the firmware from accidental overwrite and preserve its confidentiality. the at91sam9xe128/256/512 embeds an ethernet mac, one usb device port, and a usb host controller. it also integr ates several standard peripheral s, like six uarts, spi, twi, timer counters, synchronous serial controller, adc and a multimedia /sd card interface. the at91sam9xe128/256/512 system controller includes a reset controller capable of manag- ing the power-on sequence of the microcontroller and the complete system. correct device operation can be monitored by a built-in brownout detector and a watchdog running off an inte- grated rc oscillator. the at91sam9xe128/256/512 is architectured on a 6-layer matrix, allowing a maximum inter- nal bandwidth of six 32-bit buses. it also feat ures an external bus interface capable of interfacing with a wide range of memory devices. the pinout and ball-out are fully compatible with the at91sam9260 with the exception that the pin bms is replaced by the pin erase.
4 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 2. at91sam9xe128/256/512 block diagram the block diagram shows all the features fo r the 217-lfbga package. some functions are not accessible in the 208-pqfp package and t he unavailable pins are highlighted in ?multiplexing on pio controller a? on page 37 , ?multiplexing on pio controller b? on page 38 , ?multiplexing on pio controller c? on page 39 . the usb host port b is also not available. table 2-1 on page 4 defines all the multiplexed and not multiplexed pins not available in the 208-pqfp package. table 2-1. unavailable signals in 208-pin pqfp device pio peripheral a peripheral b - hdpb - - hdmb - pa30 sck2 rxd4 pa 3 1 s c k 0 t x d 4 pb12 twd1 isi_d10 pb13 twck1 isi_d11 pc2 ad2 pck1 pc3 ad3 spi1_npcs3 pc12 irq0 ncs7
5 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 2-1. at91sam9xe128/256/512 block diagram arm926ej-s processor jtag selection and boundary scan in-circuit emulator aic rom 32 kbytes d0-d15 a0/nbs0 a2-a15, a18-a20 a16/ba0 a17/ba1 ncs0 ncs1/sdcs nrd nwr0/nwe nwr1/nbs1 nwr3/nbs3 sdck, sdcke ras, cas sdwe, sda10 fiq irq0-irq2 pllrca drxd dtxd mmu apb flash 128, 256 or 512 kbytes peripheral bridge 24-channel peripheral dma plla bus interface a1/nbs2/nwr2 tst pck0-pck1 system controller xin tdi tdo tms tck jtagsel id nandoe, nandwe pmc pllb osc xout pit wdt dbgu slave master pdc a23-a24 ncs5/cfcs1 a25/cfrnw ncs4/cfcs0 nwait cfce1-cfce2 ebi static memory controller compactflash nand flash sdram controller ncs2, ncs6, ncs7 ncs3/nandcs rtck ecc controller etxck-erxck etxen-etxer ecrs-ecol erxer-erxdv erx0-erx3 etx0-etx3 mdc mdio f100 10/100 ethernet mac fifo dma fifo ssc pdc usb device ddm ddp tk tf td rd rf rk tc0 tc1 tc2 tclk0-tclk2 tioa0-tioa2 tiob0-tiob2 spi0 spi1 pdc usart0 usart1 usart2 usart3 usart4 rts0-rts3 sck0-sck3 txd0-txd5 rxd0-rxd5 cts0-cts3 pdc twi0 twi1 twck twd mci pdc transceiver dpram icache 16 kbytes dcache 8 kbytes 6-layer matrix npcs2 npcs1 spck mosi miso npcs0 npcs3 spi0_, spi1_ mcck mcda0-mcda3 mccda nrst xin32 xout32 vddcore pioa piob pioc dsr0 dcd0 dtr0 ri0 usb ohci dma transc. transc. hdpa hdma hdpb hdmb image sensor interface dma isi_pck isi_do-isi_d7 isi_hsync isi_vsync isi_mck 4-channel 10-bit adc ad0-ad3 adtrig advref vddana gndana pdc d16-d31 rtt osc rstc por 4gpreg shdn wkup shdc por rc oscsel vddbu mcdb0-mcdb3 mccdb tc3 tc4 tc5 tclk3-tclk5 tioa3-tioa5 tiob3-tiob5 fast sram 16 or 32 kbytes filter a21/nandale a22/nandcle ntrst erase pdc bod
6 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 3. signal description table 3-1 gives details on the signal name classified by peripheral. table 3-1. signal description list signal name function type active level reference voltage comments power supplies vddiom ebi i/o lines power supply power 1.65v to 1.95v or 3.0v to 3.6v vddiop0 peripherals i/o lines power supply power 3.0v to 3.6v vddiop1 peripherals i/o lines power supply power 1.65v to 3.6v vddbu backup i/o lines power supply power 1.65v to 1.95v vddana analog power supply power 3.0v to 3.6v vddpll pll power supply power 1.65v to 1.95v vddcore core chip and embedded memories power supply power 1.65v to 1.95v gnd ground ground gndpll pll ground ground gndana analog ground ground gndbu backup ground ground clocks, oscillators and plls xin main oscillator input input xout main oscillator output output xin32 slow clock oscillator input input xout32 slow clock oscillator output output oscsel slow clock oscillator selection input vddbu accepts between 0v and vddbu. pllrca pll a filter input pck0 - pck1 programmable clock output output vddiop0 shutdown, wakeup logic shdn shutdown control output low vddbu driven at 0v only. wkup wake-up input input vddbu accepts between 0v and vddbu. ice and jtag ntrst test reset signal input low vddiop0 pull-up resistor (100 k ) tck test clock input vddiop0 no pull-up resistor, schmitt trigger tdi test data in input vddiop0 no pull-up resistor, schmitt trigger tdo test data out output vddiop0 tms test mode select input vddiop0 no pull-up resistor, schmitt trigger jtagsel jtag selection input vddbu pull-down resistor (15 k ).
7 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary rtck return test clock output vddiop0 flash memory erase flash and nvm configuration bits erase command input high vddiop0 pull-down resistor (15 k ) reset/test nrst microcontroller reset i/o low vddiop0 open-drain output, pull-up resistor (100 k ). inserted in the boundary scan. tst test mode select input vddbu pull-down resistor (15 k ) debug unit - dbgu drxd debug receive data input vddiop0 dtxd debug transmit data output vddiop0 advanced interrupt controller - aic irq0 - irq2 external interrupt inputs input vddiop0 fiq fast interrupt input input vddiop0 pio controller - pioa - piob - pioc pa0 - pa31 parallel io controller a i/o vddiop0 pulled-up input at reset (100k ) (1) pb0 - pb30 parallel io controller b i/o vddiop0 pulled-up input at reset (100k ) (1) pc0 - pc31 parallel io controller c i/o vddiop0 pulled-up input at reset (100k ) (1) external bus interface - ebi d0 - d31 data bus i/o vddiom pulled-up input at reset a0 - a25 address bus output vddiom 0 at reset nwait external wait signal input low vddiom static memory controller - smc ncs0 - ncs7 chip select lines output low vddiom nwr0 - nwr3 write signal output low vddiom nrd read signal output low vddiom nwe write enable output low vddiom nbs0 - nbs3 byte mask signal output low vddiom table 3-1. signal description list (continued) signal name function type active level reference voltage comments
8 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary compactflash support cfce1 - cfce2 compactflash chip enable output low vddiom cfoe compactflash output enable output low vddiom cfwe compactflash write enable output low vddiom cfior compactflash io read output low vddiom cfiow compactflash io write output low vddiom cfrnw compactflash read not write output vddiom cfcs0 - cfcs1 compactflash chip select lines output low vddiom nand flash support nandcs nand flash chip select output low vddiom nandoe nand flash output enable output low vddiom nandwe nand flash write enable output low vddiom sdram controller sdck sdram clock output vddiom sdcke sdram clock enable output high vddiom sdcs sdram controller chip select output low vddiom ba0 - ba1 bank select output vddiom sdwe sdram write enable output low vddiom ras - cas row and column signal output low vddiom sda10 sdram address 10 line output vddiom multimedia card interface mci mcck multimedia card clock output vddiop0 mccda multimedia card slot a command i/o vddiop0 mcda0 - mcda3 multimedia card slot a data i/o vddiop0 mccdb multimedia card slot b command i/o vddiop0 mcdb0 - mcdb3 multimedia card slot b data i/o vddiop0 universal synchronous asynchronous receiver transmitter usartx sckx usartx serial clock i/o vddiop0 txdx usartx transmit data i/o vddiop0 rxdx usartx receive data input vddiop0 rtsx usartx request to send output vddiop0 ctsx usartx clear to send input vddiop0 dtr0 usart0 data terminal ready output vddiop0 dsr0 usart0 data set ready input vddiop0 table 3-1. signal description list (continued) signal name function type active level reference voltage comments
9 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary dcd0 usart0 data carrier detect input vddiop0 ri0 usart0 ring indicator input vddiop0 synchronous serial controller - ssc td ssc transmit data output vddiop0 rd ssc receive data input vddiop0 tk ssc transmit clock i/o vddiop0 rk ssc receive clock i/o vddiop0 tf ssc transmit frame sync i/o vddiop0 rf ssc receive frame sync i/o vddiop0 timer/counter - tcx tclkx tc channel x external clock input input vddiop0 tioax tc channel x i/o line a i/o vddiop0 tiobx tc channel x i/o line b i/o vddiop0 serial peripheral interface - spix_ spix_miso master in slave out i/o vddiop0 spix_mosi master out slave in i/o vddiop0 spix_spck spi serial clock i/o vddiop0 spix_npcs0 spi peripheral chip select 0 i/o low vddiop0 spix_npcs1- spix_npcs3 spi peripheral chip select output low vddiop0 two-wire interface twdx two-wire serial data i/o vddiop0 twckx two-wire serial clock i/o vddiop0 usb host port hdpa usb host port a data + analog vddiop0 hdma usb host port a data - analog vddiop0 hdpb usb host port b data + analog vddiop0 hdmb usb host port b data + analog vddiop0 usb device port ddm usb device port data - analog vddiop0 ddp usb device port data + analog vddiop0 table 3-1. signal description list (continued) signal name function type active level reference voltage comments
10 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary note: 1. programming of this pull-up resistor is performed independently for each i/o line through the pio controllers. after res et, all the i/o lines default as inputs with pull-up re sistors enabled, except those which are multiplexed with the external bus inter- face signals that require to be enabled as peripheral at reset. th is is explicitly indicated in the column ?reset state? of the peripheral multiplexing tables. ethernet 10/100 etxck transmit clock or reference clock input vddiop0 mii only, refck in rmii erxck receive clock input vddiop0 mii only etxen transmit enable output vddiop0 etx0-etx3 transmit data output vddiop0 etx0-etx1 only in rmii etxer transmit coding error output vddiop0 mii only erxdv receive data valid input vddiop0 rxdv in mii, crsdv in rmii erx0-erx3 receive data input vddiop0 erx0-erx1 only in rmii erxer receive error input vddiop0 ecrs carrier sense and data valid input vddiop0 mii only ecol collision detect input vddiop0 mii only emdc management data clock output vddiop0 emdio management data input/output i/o vddiop0 ef100 force 100mbit/sec. output high vddiop0 image sensor interface isi_d0- isi_d11 image sensor data input vddiop1 isi_mck image sensor reference clock output vddiop1 isi_hsync image sensor horizontal synchro input vddiop1 isi_vsync image sensor vertical synchro input vddiop1 isi_pck image sensor data clock input vddiop1 analog to digi tal converter ad0-ad3 analog inputs analog vddana digital pulled-up inputs at reset advref analog positive reference analog vddana adtrg adc trigger input vddana fast flash programming interface pgmen[2:0] programming enabling input vddiop0 pgmncmd programming co mmand input low vddiop0 pgmrdy programming ready output high vddiop0 pgmnoe programming read input low vddiop0 pgmnvalid data direction output low vddiop0 pgmm[3:0] programming mode input vddiop0 pgmd[15:0] programming data i/o vddiop0 table 3-1. signal description list (continued) signal name function type active level reference voltage comments
11 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 4. package and pinout the at91sam9xe128/256/512 is available in a 208-pin pqfp green package (0.5mm pitch) or in a 217-ball lfbga green package (0.8 mm ball pitch). 4.1 208-pin pqfp package outline figure 4-1 shows the orientation of the 208-pin pqfp package. a detailed mechanical description is given in the section ?at91sam9xe mechanical character- istics? of the product datasheet. figure 4-1. 208-pin pqfp package outline (top view) 152 53 104 105 156 157 208
12 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 4.2 208-pin pqfp package pinout table 4-1. pinout for 208-pin pqfp package pin signal name pin signal name pin signal name pin signal name 1 pa24 53 gnd 105 ras 157 advref 2 pa25 54 ddm 106 d0 158 pc0 3 pa26 55 ddp 107 d1 159 pc1 4 pa27 56 pc13 108 d2 160 vddana 5 vddiop0 57 pc11 109 d3 161 pb10 6 gnd 58 pc10 110 d4 162 pb11 7 pa28 59 pc14 111 d5 163 pb20 8 pa29 60 pc9 112 d6 164 pb21 9 pb0 61 pc8 113 gnd 165 pb22 10 pb1 62 pc4 114 vddiom 166 pb23 11 pb2 63 pc6 115 sdck 167 pb24 12 pb3 64 pc7 116 sdwe 168 pb25 13 vddiop0 65 vddiom 117 sdcke 169 vddiop1 14 gnd 66 gnd 118 d7 170 gnd 15 pb4 67 pc5 119 d8 171 pb26 16 pb5 68 ncs0 120 d9 172 pb27 17 pb6 69 cfoe/nrd 121 d10 173 gnd 18 pb7 70 cfwe/nwe/nwr0 122 d11 174 vddcore 19 pb8 71 nandoe 123 d12 175 pb28 20 pb9 72 nandwe 124 d13 176 pb29 21 pb14 73 a22 125 d14 177 pb30 22 pb15 74 a21 126 d15 178 pb31 23 pb16 75 a20 127 pc15 179 pa0 24 vddiop0 76 a19 128 pc16 180 pa1 25 gnd 77 vddcore 129 pc17 181 pa2 26 pb17 78 gnd 130 pc18 182 pa3 27 pb18 79 a18 131 pc19 183 pa4 28 pb19 80 ba1/a17 132 vddiom 184 pa5 29 tdo 81 ba0/a16 133 gnd 185 pa6 30 tdi 82 a15 134 pc20 186 pa7 31 tms 83 a14 135 pc21 187 vddiop0 32 vddiop0 84 a13 136 pc22 188 gnd 33 gnd 85 a12 137 pc23 189 pa8 34 tck 86 a11 138 pc24 190 pa9 35 ntrst 87 a10 139 pc25 191 pa10 36 nrst 88 a9 140 pc26 192 pa11 37 rtck 89 a8 141 pc27 193 pa12 38 vddcore 90 vddiom 142 pc28 194 pa13 39 gnd 91 gnd 143 pc29 195 pa14 40 erase 92 a7 144 pc30 196 pa15 41 oscsel 93 a6 145 pc31 197 pa16 42 tst 94 a5 146 gnd 198 pa17 43 jtagsel 95 a4 147 vddcore 199 vddiop0 44 gndbu 96 a3 148 vddpll 200 gnd 45 xout32 97 a2 149 xin 201 pa18 46 xin32 98 nwr2/nbs2/a1 150 xout 202 pa19 47 vddbu 99 nbs0/a0 151 gndpll 203 vddcore 48 wkup 100 sda10 152 nc 204 gnd 49 shdn 101 cfiow/nbs3/nwr3 153 gndpll 205 pa20 50 hdma 102 cfior/nbs1/nwr1 154 pllrca 206 pa21 51 hdpa 103 sdcs/ncs1 155 vddpll 207 pa22 52 vddiop0 104 cas 156 gndana 208 pa23
13 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 4.3 217-ball lfbga package outline figure 4-2 shows the orientation of the 217-ball lfbga package. a detailed mechanical description is given in the section ?at91sam9xe mechanical character- istics? of the product datasheet. figure 4-2. 217-ball lfbga package outline (top view) 12 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 abcdefghj klmnprtu ball a1
14 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 4.4 217-ball lfbga package pinout table 4-2. pinout for 217-ball lfbga package pin signal name pin signal name pin signal name pin signal name a1 cfiow/nbs3/nwr3 d5 a5 j14 tdo p17 pb5 a2 nbs0/a0 d6 gnd j15 pb19 r1 nc a3 nwr2/nbs2/a1 d7 a10 j16 tdi r2 gndana a4 a6 d8 gnd j17 pb16 r3 pc29 a5 a8 d9 vddcore k1 pc24 r4 vddana a6 a11 d10 gnd k2 pc20 r5 pb12 a7 a13 d11 vddiom k3 d15 r6 pb23 a8 ba0/a16 d12 gnd k4 pc21 r7 gnd a9 a18 d13 ddm k8 gnd r8 pb26 a10 a21 d14 hdpb k9 gnd r9 pb28 a11 a22 d15 nc k10 gnd r10 pa0 a12 cfwe/nwe/nwr0 d16 vddbu k14 pb4 r11 pa4 a13 cfoe/nrd d17 xin32 k15 pb17 r12 pa5 a14 ncs0 e1 d10 k16 gnd r13 pa10 a15 pc5 e2 d5 k17 pb15 r14 pa21 a16 pc6 e3 d3 l1 gnd r15 pa23 a17 pc4 e4 d4 l2 pc26 r16 pa24 b1 sdck e14 hdpa l3 pc25 r17 pa29 b2 cfior/nbs1/nwr1 e15 hdma l4 vddiop0 t1 pllrca b3 sdcs/ncs1 e16 gndbu l14 pa28 t2 gndpll b4 sda10 e17 xout32 l15 pb9 t3 pc0 b5 a3 f1 d13 l16 pb8 t4 pc1 b6 a7 f2 sdwe l17 pb14 t5 pb10 b7 a12 f3 d6 m1 vddcore t6 pb22 b8 a15 f4 gnd m2 pc31 t7 gnd b9 a20 f14 oscsel m3 gnd t8 pb29 b10 nandwe f15 erase m4 pc22 t9 pa2 b11 pc7 f16 jtagsel m14 pb1 t10 pa6 b12 pc10 f17 tst m15 pb2 t11 pa8 b13 pc13 g1 pc15 m16 pb3 t12 pa11 b14 pc11 g2 d7 m17 pb7 t13 vddcore b15 pc14 g3 sdcke n1 xin t14 pa20 b16 pc8 g4 vddiom n2 vddpll t15 gnd b17 wkup g14 gnd n3 pc23 t16 pa22 c1 d8 g15 nrst n4 pc27 t17 pa27 c2 d1 g16 rtck n14 pa31 u1 gndpll c3 cas g17 tms n15 pa30 u2 advref c4 a2 h1 pc18 n16 pb0 u3 pc2 c5 a4 h2 d14 n17 pb6 u4 pc3 c6 a9 h3 d12 p1 xout u5 pb20 c7 a14 h4 d11 p2 vddpll u6 pb21 c8 ba1/a17 h8 gnd p3 pc30 u7 pb25 c9 a19 h9 gnd p4 pc28 u8 pb27 c10 nandoe h10 gnd p5 pb11 u9 pa12 c11 pc9 h14 vddcore p6 pb13 u10 pa13 c12 pc12 h15 tck p7 pb24 u11 pa14 c13 ddp h16 ntrst p8 vddiop1 u12 pa15 c14 hdmb h17 pb18 p9 pb30 u13 pa19 c15 nc j1 pc19 p10 pb31 u14 pa17 c16 vddiop0 j2 pc17 p11 pa1 u15 pa16 c17 shdn j3 vddiom p12 pa3 u16 pa18 d1 d9 j4 pc16 p13 pa7 u17 vddiop0 d2 d2 j8 gnd p14 pa9 d3 ras j9 gnd p15 pa26 d4 d0 j10 gnd p16 pa25
15 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 5. power considerations 5.1 power supplies the at91sam9xe128/256/512 has several types of power supply pins: ? vddcore pins: power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 1.65v and 1.95v, 1.8v nominal. ? vddiom pins: power the external bus interface i/o lines; voltage ranges between 1.65v and 1.95v (1.8v typical) or between 3.0v and 3.6v (3.3v nominal). the expected voltage range is selectable by software. ? vddiop0 pins: power the peripheral i/o lines and the usb transceivers; voltage ranges from 3.0v and 3.6v, 3v or 3.3v nominal. ? vddiop1 pin: powers the peripherals i/o lines involving the image sensor interface; voltage ranges from 1.65v and 3.6v, 1.8v, 2.5v, 3v or 3.3v nominal. ? vddbu pin: powers the slow clock oscillator and a part of the system controller; voltage ranges from 1.65v to 1.95v, 1.8v nominal. ? vddpll pins: power the pll cells and the main oscillator; voltage r anges from 1.65v and 1.95v, 1.8v nominal. ? vddana pin: powers the analog to digital converter; voltage ranges from 3.0v and 3.6v, 3.3v nominal. the power supplies vddiom, vddiop0 and vdd iop1 are identified in the pinout table and their associated i/o lines in the multiplexing tables. these supplies enable the user to power the device differently for interfacing with memories and for interfacing with peripherals. ground pins gnd are common to vddcore, vddiom, vddiop0 and vddiop1 pins power supplies. separated ground pins are provid ed for vddbu, vddpll and vddana. these ground pins are respectively gndbu, gndpll and gndana.
16 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 6. i/o line considerations 6.1 erase pin the pin erase is used to re-initialize the flash content and the nvm bits. it integrates a perma- nent pull-down resistor of about 15 k , so that it can be left unconnected for normal operations. this pin is debounced on the rc oscillator or 32,768 hz to improve the glitch tolerance. mini- mum debouncing time is 200 ms. 6.2 i/o line drive levels the pio lines pa0 to pa31 and pb0 to pb31 and pc0 to pc3 are high-drive current capable. each of these i/o lines can drive up to 16 ma perma nently with a total of 350 ma on all i/o lines. refer to the ?dc characteristics? section of the product datasheet. 6.3 shutdown logic pins the shdn pin is a tri-state output only pin, which is driven by the shutdown controller. there is no internal pull-up. an external pull-up to vddbu is needed and its value must be higher than 1 m . the resisitor value is calculated according to the regulator enable implementation and the shdn level. the pin wkup is an input-only. it can accept voltages only between 0v and vddbu. 7. processor and architecture 7.1 arm926ej-s processor ? risc processor based on arm v5tej archit ecture with jazelle technology for java acceleration ? two instruction sets ? arm high-performance 32-bit instruction set ? thumb high code density 16-bit instruction set ? dsp instruction extensions ? 5-stage pipeline architecture: ? instruction fetch (f) ? instruction decode (d) ? execute (e) ? data memory (m) ? register write (w) ? 8 kb data cache, 16 kb instruction cache ? virtually-addressed 4-way associative cache ? eight words per line ? write-through and write-back operation ? pseudo-random or round-robin replacement ? write buffer ? main write buffer with 16-word data buffer and 4-address buffer
17 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? dcache write-back buffer with 8-word entries and a single address entry ? software control drain ? standard arm v4 and v5 memory management unit (mmu) ? access permission for sections ? access permission for large pages and small pages can be specified separately for each quarter of the page ? 16 embedded domains ? bus interface unit (biu) ? arbitrates and schedules ahb requests ? separate masters for both instruction and data access providin g complete matrix system flexibility ? separate address and data buses for both the 32-bit instruction interface and the 32-bit data interface ? on address and data buses, data can be 8-bit (bytes), 16-bit (half-words) or 32-bit (words) 7.2 bus matrix ? 6-layer matrix, handling requests from 6 masters ? programmable arbitration strategy ? fixed-priority arbitration ? round-robin arbitration, either with no default master, last accessed default master or fixed default master ? burst management ? breaking with slot cycle limit support ? undefined burst length support ? one address decoder provided per master ? three different slaves may be assigned to each decoded memory area: one for internal rom boot, one for internal flash boot, one after remap ? boot mode select ? non-volatile boot memory can be internal rom or internal flash ? selection is made by general purpose nvm bit sampled at reset ? remap command ? allows remapping of an internal sram in place of the boot non-volatile memory (rom or flash) ? allows handling of dynamic exception vectors 7.2.1 matrix masters the bus matrix of the at91sam9xe128/256/512 manages six masters, thus each master can perform an access concurrently with others, depending on whether the slave it accesses is available.
18 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary each master has its own decoder, which can be defined specifically for each master. in order to simplify the addressing, all the masters have the same decodings. 7.2.2 matrix slaves each slave has its own arbiter, thus allowing a di fferent arbitration per slave to be programmed. 7.2.3 masters to slaves access all the masters can normally access all the slaves. however, some paths do not make sense, such as allowing access from the ethernet mac to the internal peripherals. thus, these paths are forbidden or simply not wired, and shown as ??? in the following table. 7.3 peripheral dma controller ? acting as one matrix master ? allows data transfers from/to peripheral to/from any memory space without any intervention of the processor. ? next pointer support, forbids strong real-time constraints on buffer management. table 7-1. list of bus matrix masters master 0 arm926 ? instruction master 1 arm926 data master 2 peripheral dma controller master 3 usb host controller master 4 image sensor controller master 5 ethernet mac table 7-2. list of bus matrix slaves slave 0 internal flash slave 1 internal sram slave 2 internal rom usb host user interface slave 3 external bus interface slave 4 reserved slave 5 internal peripherals table 7-3. at91sam9xe128/256 /512 masters to slaves access master 0 and 1 2 3 4 5 slave arm926 instruction and data periphera dma controller isi controller ethernet mac usb host controller 0 internal flash x ? ? x 1 internal sram x x x x x 2 internal rom x x ? ? ? uhp user interface x ? ? ? ? 3 external bus interface x x x x x 4 reserved ? ???? internal peripherals x x ? ? ?
19 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? twenty-four channels ? two for each usart ? two for the debug unit ? two for each serial synchronous controller ? two for each serial peripheral interface ? two for the two wire interface ? one for multimedia card interface ? one for analog to digital converter the peripheral dma controller handles transfer requests from the channel according to the fol- lowing priorities (low to high priorities): ? twi0 transmit channel ? twi1 transmit channel ? dbgu transmit channel ? usart4 transmit channel ? usart3 transmit channel ? usart2 transmit channel ? usart1 transmit channel ? usart0 transmit channel ? spi1 transmit channel ? spi0 transmit channel ? ssc transmit channel ? twi0 receive channel ? twi1 receive channel ? dbgu receive channel ? usart4 receive channel ? usart3 receive channel ? usart2 receive channel ? usart1 receive channel ? usart0 receive channel ? adc receive channel ? spi1 receive channel ? spi0 receive channel ? ssc receive channel ? mci transmit/receive channel 7.4 debug and test features ? arm926 real-time in-circuit emulator ? two real-time watchpoint units ? two independent registers: debug control register and debug status register ? test access port accessible through jtag protocol ? debug communications channel
20 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? debug unit ?two-pin uart ? debug communication channel interrupt handling ? chip id register ? ieee1149.1 jtag boundary-scan on all digital pins
21 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 8. memories figure 8-1. at91sam9xe128/256/512 memory mapping 16k bytes 16k bytes 0xfffc 0000 16k bytes 0xfffc 4000 spi1 0xfffc c000 spi0 16k bytes 0xfffc 8000 16k bytes 16k bytes 16k bytes 0xfffa 4000 tco, tc1, tc2 0xfffa 8000 mci 0xfffb 0000 0xfffb 4000 usart0 0xfffb c000 usart1 0xfffa 0000 0xfffa c000 usart2 16k bytes twi0 16k bytes 16k bytes 0xfffb 8000 16k bytes 16k bytes udp ssc 256m bytes 0x1000 0000 0x0000 0000 0x0fff ffff 0xffff ffff 0xf000 0000 0xefff ffff address memory space internal peripherals internal memories ebi chip select 0 ebi chip select 1/ sdramc ebi chip select 2 ebi chip select 3/ nandflash ebi chip select 4/ compact flash slot 0 ebi chip select 5/ compact flash slot 1 ebi chip select 6 ebi chip select 7 undefined (abort) 256m bytes 256m bytes 256m bytes 256m bytes 256m bytes 256m bytes 256m bytes 1,518m bytes 0x2000 0000 0x1fff ffff 0x3000 0000 0x2fff ffff 0x4000 0000 0x3fff ffff 0x6fff ffff 0x6000 0000 0x5fff ffff 0x5000 0000 0x4fff ffff 0x7000 0000 0x7fff ffff 0x8000 0000 0x8fff ffff 0x9000 0000 256m bytes 0xffff fd00 0xffff fc00 0xffff fa00 0xffff f800 0xffff f600 0xffff f400 0xffff f200 16 bytes 256 bytes 512 bytes 512 bytes 512 bytes 512 bytes pmc pioc piob pioa dbgu rstc 0xffff f000 512 bytes aic 0xffff ee00 512 bytes matrix 0xffff ec00 512 bytes smc 0xffff fd10 16 bytes shdc 0xffff ea00 512 bytes sdramc 0xffff fd20 16 bytes rttc 0xffff fd30 16 bytes pitc 0xffff fd40 16 bytes wdtc 0xffff fd50 16 bytes gpbr 0xffff fd60 eefc reserved 256m bytes peripheral mapping internal memory mapping (1) can be rom or flash depending on gpnvm[3] notes : isi emac 0xffff c000 sysc reserved 0xffff ffff system controller mapping 16k bytes 0xffff ffff reserved 0xffff c000 adc usart3 usart4 twi1 tc3, tc4, tc5 16k bytes 16k bytes 16k bytes 16k bytes 16k bytes 0xfffd 4000 0xfffd 8000 0xfffd 0000 0xfffe 0000 0xfffd c000 0xfffe 4000 0xffff e800 ecc 512 bytes ccfg 0xffff ef10 32k bytes 128, 256 or 512k bytes 0x10 8000 rom 0x20 0000 flash 0x30 0000 0x30 8000 sram 0x50 4000 0x10 0000 0x28 0000 uhp 32k bytes 16k bytes 0x50 0000 reserved reserved reserved reserved 0x0fff ffff boot memory (1) 0x0000 0000 reserved 0xf000 0000 512 bytes
22 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary a first level of address decoding is performed by the bus matrix, i.e., the implementation of the advanced high performance bus (ahb) for its master and slave interfaces with additional features. decoding breaks up the 4 gbytes of address spac e into 16 banks of 256 mbytes. the banks 1 to 7 are directed to the ebi that associates thes e banks to the external chip selects ebi_ncs0 to ebi_ncs7. bank 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1 mbyte of internal memory area. the bank 15 is reserved for the peripher- als and provides access to the advanced peripheral bus (apb). other areas are unused and performing an access within them provides an abort to the master requesting such an access. each master has its own bus and its own decoder, thus allowing a different memory mapping per master. however, in order to simplify the mappings, all the masters have a similar address decoding. regarding master 0 and master 1 (arm926 instruction and data), three different slaves are assigned to the memory space decoded at address 0x0: one for internal boot, one for external boot, one after remap, refer to table 8-3, ?internal memory mapping,? on page 26 for details. a complete memory map is presented in figure 8-1 on page 21 . 8.1 embedded memories 8.1.1 at91sam9xe128 ? 32 kb rom ? single cycle access at full matrix speed ? 16 kb fast sram ? single cycle access at full matrix speed ? 128 kb embedded flash 8.1.2 at91sam9xe256 ? 32 kb rom ? single cycle access at full matrix speed ? 32 kb fast sram ? single cycle access at full matrix speed ? 256 kb embedded flash 8.1.3 at91sam9xe512 ? 32 kb rom ? single cycle access at full matrix speed ? 32 kb fast sram ? single cycle access at full matrix speed ? 512 kb embedded flash 8.1.4 rom topology the embedded rom contains the fast flash programming and the sam-ba boot programs. each of these two programs is stored at 16 kb boundary and the program executed at address
23 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary zero depends on the combination of the tst pin and pa0 to pa2 pins. figure 8-2 shows the con- tents of the rom and the program available at address zero. figure 8-2. rom boot memory map 8.1.4.1 fast flash programming interface the fast flash programming interface programs th e device through a serial jtag interface or a multiplexed fully-handshaked parallel port. it allows gang-programming with market-standard industrial programmers. the ffpi supports read, page program, page erase, full erase, lock, unlock and protect commands. the fast flash programming interface is enabled and the fast programming mode is entered when the tst pin and the pa0 and pa1 pins are all tied high and pa2 is tied low. 8.1.4.2 sam-ba ? boot assistant the sam-ba boot assistant is a default boot program that provides an easy way to program in situ the on-chip flash memory. the sam-ba boot assistant supports serial communication through the dbgu or through the usb device port. 0x0000 0000 0x0000 3fff ffpi program tst=1 pa0=1 pa1=1 pa2=0 0x0000 0000 0x0000 3fff sam-ba program tst=0 0x0000 0000 0x0000 7fff sam-ba program ffpi program rom table 8-1. signal description signal name pio type a ctive level comments pgmen0 pa0 input high must be connected to vddio pgmen1 pa1 input high must be connected to vddio pgmen2 pa2 input low must be connected to gnd pgmncmd pa4 input low pulled-up input at reset pgmrdy pa5 output high pulled-up input at reset pgmnoe pa6 input low pulled-up input at reset pgmnvalid pa7 output low pulled-up input at reset pgmm[3:0] pa8..pa10 input pulled-up input at reset pgmd[15:0] pa12..pa27 input/out put pulled-up input at reset
24 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? communication through the dbgu supports a wi de range of crystals from 3 to 20 mhz via software auto-detection. ? communication through the usb device port is depends on crystal selected: ? limited to an 18,432 hz crystal if the internal rc oscillator is selected ? supports a wide range of crystals from 3 to 20 mhz if the 32,768 hz crystal is selected the sam-ba boot provides an interface with sam-ba graphic user interface (gui). 8.1.5 embedded flash the flash of the at91sam9xe128/256/512 is organized in 256/512/1024 pages of 512 bytes directly connected to the 32-bit internal bus. each page contains 128 words. the flash contains a 512-byte write buffer allo wing the programming of a page. this buffer is write-only as 128 32-bit words, and accessible all along the 1 mb address space, so that each word can be written at its final address. the flash benefits from the integration of a power reset cell and from a brownout detector to prevent code corruption during power su pply changes, even in the worst conditions. 8.1.5.1 enhanced embedded flash controller the enhanced embedded flash controlle r (eefc) is continuously clocked. the enhanced embedded flash controller (eefc) is a slave for the bus matrix and is configu- rable through its user interface on the apb bus. it ensu res the interface of the flash block with the 32-bit internal bus. its 128-bit wide memory interface increases performance, four 32-bit data are read during each access, this multiply the throughput by 4 in case of consecutive data. it also manages the programming, erasing, locking and unlocking sequences of the flash using a full set of commands. one of the commands returns the embedded flash descriptor definition that informs the system about the flash organiz ation, thus making the software generic pro- gramming of the access parameters of the flash (number of wait states, timings, etc.) 8.1.5.2 lock regions the memory plane of 128, 256 or 512 kbytes is organized in 8, 16 or 32 locked regions of 32 pages each. each lock region can be locked independently, so that the software protects the first memory plane against erroneous programming: if a locked-regions erase or program command occurs, the command is aborted and the eefc could trigger an interrupt. the lock bits are software programmable through the eefc user interface. the command ?set lock bit? enables the protection. the command ?clear lock bit? unlocks the lock region. asserting the erase pin clears the lock bits, thus unlocking the entire flash.
25 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 8-3. flash first memory plane mapping 8.1.5.3 gpnvm bits the at91sam9xe128/256/512 features four gpnvm bits that can be cleared or set respec- tively through the commands ?clear gpnvm bi t? and ?set gpnvm bit? of the eefc user interface. 8.1.5.4 security bit the at91sam9xe128/256/512 features a security bit, based on a specific gpnvm bit, gpn- vmbit[0]. when the security is enabled, access to the flash, ei ther through the ice interface or through the fast flash programming interface, is forbidden. this ensures the confidentiality of the code programmed in the flash. disabling the security bit can only be achieved by asserti ng the erase pin at 1, and after a full flash erase is performed. when the security bit is deactivated, all accesses to the flash are permitted. as the erase pin integrates a permanent pull-down, it can be left unconnected during normal operation. 0x0020 0000 0x0021 ffff or 0x0023 ffff or 0x0027 ffff page 0 locked region 0 512 bytes 16 kbytes locked region 7, 15 or 31 page 31 locked regions area 128, 256 or 512 kbytes 256, 512 or 1024 pages 32 bits wide table 8-2. general-purpose non volatile memory bits gpnvmbit[#] function 0 security bit 1 brownout detector enable 2 brownout detector reset enable 3 boot mode select (bms)
26 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 8.1.5.5 non-volatile brownout detector control two gpnvm bits are used for controlling the brownout detector (bod), so that even after a power loss, the brownout detector operations remain in their state. ? gpnvmbit[1] is used as a brownout detector enable bit. setting gpnvmbit[1] enables the bod, clearing it disables the bod. assertin g erase clears gpnvmbit[1 ] and thus disables the brownout detector by default. ? gpnvmbit[2] is used as a brownout reset enable signal for the reset controller. setting gpnvmbit[2] enables the brownout reset when a brownout is detected, clearing gpnvmbit[2] disables the brownout reset. a sserting erase disables th e brownout reset by default. 8.1.6 boot strategies table 8-3 summarizes the internal memory mapping for each master, depending on the remap status and the gpnvmbit[3] state at reset. the system always boots at address 0x0. to ensure a maximu m number of possibilities for boot, the memory layout can be configured with two parameters. remap allows the user to lay out the first internal sram bank to 0x0 to ease development. this is done by software once the system has booted. refer to the section ?at91sam9xe bus matrix? in the product datasheet for more details. when remap = 0, a non volatile bit stored in flash memory (gpnvmbit[3]) allows the user to lay out to 0x0, at his convenience, the rom or the flash. refer to the section ?enhanced embedded flash controller (eefc)? in the product datasheet for more details. note: memory blocks not affected by these paramete rs can always be seen at their specified base addresses. see the complete memory map presented in figure 8-1 on page 21 . the at91sam9xe matrix manages a boot memory that depends on the value of gpnvmbit[3] at reset. the internal memory area mapped between address 0x0 and 0x0fff ffff is reserved for this purpose. if gpnvmbit[3] is set, the boot memory is the internal flash memory if gpnvmbit[3] is clear (flash reset state), the boot memory is the embedded rom. after a flash erase, the boot memory is the internal rom. 8.1.6.1 gpnvmbit[3] = 0, boot on embedded rom the system boots using the boot program. ? boot on slow clock (on-chip rc or 32,768 hz) ? auto baudrate detection ? sam-ba boot in case no valid program is detected in external nvm, supporting ? serial communication on a dbgu ? usb device port table 8-3. internal memory mapping address remap = 0 remap = 1 gpnvmbit[3] clear gpnvmbit[3] set 0x0000 0000 rom flash sram
27 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 8.1.6.2 gpnvmbit[3] = 1, boot on internal flash ? boot on slow clock (on-chip rc or 32,768 hz) the customer-programmed software must perform a complete configuration. to speed up the boot sequence when booting at 32 khz, the user must take the following steps: 1. program the pmc (main oscillator enable or bypass mode) 2. program and start the pll 3. switch the main clock to the new value. 8.2 external memories the external memories are accessed through the external bus interface. each chip select line has a 256 mb memory area assigned. refer to the memory map in figure 8-1 on page 21 . 8.2.1 external bus interface ? integrates three external memory controllers: ? static memory controller ? sdram controller ? ecc controller ? additional logic for nandflash ? full 32-bit external data bus ? up to 26-bit address bus (up to 64 mb linear) ? up to 8 chip selects, configurable assignment: ? static memory controller on ncs0 ? sdram controller or static memory controller on ncs1 ? static memory controller on ncs2 ? static memory controller on ncs3, optional nand flash support ? static memory controller on ncs4 - ncs5, optional compactflash support ? static memory controller on ncs6-ncs7 8.2.2 static memory controller ? 8-, 16- or 32-bit data bus ? multiple access modes supported ? byte write or byte select lines ? asynchronous read in page mode supported (4- up to 32-byte page size) ? multiple device adaptability ? compliant with lcd module ? control signals programmable setup, pulse and hold time for each memory bank ? multiple wait state management ? programmable wait state generation ? external wait request ? programmable data float time ? slow clock mode supported
28 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 8.2.3 sdram controller ? supported devices: ? standard and low power sdram (mobile sdram) ? numerous configurations supported ? 2k, 4k, 8k row address memory parts ? sdram with two or four internal banks ? sdram with 16- or 32-bit data path ? programming facilities ? word, half-word, byte access ? automatic page break when memory boundary has been reached ? multibank ping-pong access ? timing parameters specified by software ? automatic refresh operation, refresh rate is programmable ? energy-saving capabilities ? self-refresh, power down and deep power down modes supported ? error detection ? refresh error interrupt ? sdram power-up initialization by software ? cas latency of 1, 2 and 3 supported ? auto precharge command not used 8.2.4 error corrected code controller ? hardware error corrected code generation ? detection and correction by software ? supports nand flash and smartmedia devices with 8- or 16-bit data path ? supports nand flash and smartmedia with page sizes of 528,1056, 2112 and 4224 bytes specified by software ? supports 1 bit correction for a page of 512, 1024, 2112 and 4096 bytes with 8- or 16-bit data path ? supports 1 bit correction per 512 bytes of data for a page size of 512, 2048 and 4096 bytes with 8-bit data path ? supports 1 bit correction per 256 bytes of data for a page size of 512, 2048 and 4096 bytes with 8-bit data path
29 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 9. system controller the system controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. the system controller user interface also embeds the registers that configure the matrix and a set of registers for the chip configuration. the chip configuration registers configure the ebi chip select assignment and voltage range for external memories. the system controller?s peripherals are all mapped within the highest 16 kb of address space, between addresses 0xffff e800 and 0xffff ffff. however, all the registers of system controller are mapped on the top of the address space. all the registers of the system controller can be addressed from a single pointer by using the stan- dard arm instruction set, as the load/store instruction have an indexing mode of 4 kb. figure 9-1 on page 30 shows the system controller block diagram. figure 8-1 on page 21 shows the mapping of the user interfaces of the system controller peripherals.
30 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 9.1 system controller block diagram figure 9-1. at91sam9xe128/256/5 12 system controller block diagram bod nrst slck advanced interrupt controller real-time timer periodic interval timer reset controller pa0-pa31 periph_nreset system controller watchdog timer wdt_fault wdrproc pio controllers power management controller xin xout pllrca mainck pllack pit_irq mck proc_nreset wdt_irq periph_irq[2..4] periph_nreset periph_clk[2..27] pck mck pmc_irq nirq nfiq rtt_irq embedded peripherals periph_clk[2..4] pck[0-1] in out enable arm926ej-s slck slck irq0-irq2 fiq irq0-irq2 fiq periph_irq[6..24] periph_irq[2..24] int int periph_nreset periph_clk[6..24] jtag_nreset por_ntrst proc_nreset periph_nreset dbgu_txd dbgu_rxd pit_irq dbgu_irq pmc_irq rstc_irq wdt_irq rstc_irq slck boundary scan tap controller jtag_nreset debug pck debug idle debug bus matrix mck periph_nreset proc_nreset backup_nreset periph_nreset idle debug unit dbgu_irq mck dbgu_rxd periph_nreset dbgu_txd rtt_alarm shutdown controller slck rtt0_alarm backup_nreset shdn wkup 4 general-purpose backup registers backup_nreset xin32 xout32 pllbck pb0-pb31 pc0-pc31 vddbu powered vddcore powered ntrst por main osc plla vddbu por slow clock osc pllb por_ntrst vddbu rtt_irq udpck usb device port udpck periph_nreset periph_clk[10] periph_irq[10] usb host port periph_nreset periph_clk[20] periph_irq[20] uhpck uhpck rc osc oscsel vddcore flash_wrdis flash_poe gpnvm[1] cal gpnvm[2] bod_rst_en embedded flash flash_poe gpnvm[1..3] flash_wrdis security_bit(gpnvm0) cal gpnvm[3] vddcore efc2_irq
31 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 9.2 reset controller ? based on two power-on reset cells ? one on vddbu and one on vddcore ? status of the last reset ? either general reset (vddbu rising), wake-up reset (vddcore rising), software reset, user reset or watchdog reset ? controls the internal resets and the nrst pin output ? allows shaping a reset signal for the external devices 9.3 brownout detector and power-on reset the at91sam9xe128/256/512 embeds one brownout detection circuit and power-on reset cells. the power-on reset are supplied with and monitor vddcore and vddbu. signals (flash_poe and flash_wrdis) are provided to the flash to prevent any code corruption during power-up or po wer-down sequences or if browno uts occur on the vddcore power supply. the power-on reset cell has a limited-accuracy threshold at around 1.5v. its output remains low during power-up until vddcore go es over this voltag e level. this signal goes to the reset con- troller and allows a full re-initialization of the device. the brownout detector monitors th e vddcore level during operatio n by comparing it to a fixed trigger level. it secures system operations in the most difficult environments and prevents code corruption in case of brownout on the vddcore. when the brownout detector is enabled and vddcor e decreases to a value below the trigger level (vbot-), the brownout output is immediately activated. for more details on vbot, see the table ?brownout detector characteristics? in the section ?at91sam9xe128/256/512 electrical characteristics? in the full datasheet. when vddcore increases above the trigger level (vbot+, defined as vbot + vhyst), the reset is released. the brownout detector only detects a drop if the voltage on vddcore stays below the threshold voltage for longer than about 1s. the vddcore threshold voltage has a hysteresis of about 50 mv typical, to ensure spike free brownout detection. the typical value of the brownout detector threshold is 1.55v with an accu- racy of 2% and is factory calibrated. the brownout detector is low-power, as it cons umes less than 12 a static current. however, it can be deactivated to save its static current. in this case, it consumes less than 1 a. the deac- tivation is configured through the gpnvmbit[1] of the flash. additional information can be found in the ?electrical characteristics? section of the product datasheet. 9.4 shutdown controller ? shutdown and wake-up logic ? software programmable assertion of the shdn pin ? deassertion programmable on a wkup pin level change or on alarm
32 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 9.5 clock generator ? embeds a low power 32,768 hz slow cloc k oscillator and a low-power rc oscillator selectable with oscsel signal ? provides the permanent slow clock slck to the system ? embeds the ma in oscillator ? oscillator bypass feature ? supports 3 to 20 mhz crystals ? embeds 2 plls ? pll a outputs 80 to 240 mhz clock ? pll b outputs 70 mhz to 130 mhz clock ? both integrate an input divider to increase output accuracy ? pllb embeds its own filter 9.6 power management controller ?provides: ? the processor clock pck ? the master clock mck, in particular to the matrix and the memory interfaces ? the usb device clock udpck ? independent peripheral clocks, typically at the frequency of mck ? 2 programmable clock outputs: pck0, pck1 ? five flexible operating modes: ? normal mode, processor and peripherals running at a programmable frequency ? idle mode, processor stopped waiting for an interrupt ? slow clock mode, processor and peripherals running at low frequency ? standby mode, mix of idle and backup mode, peripheral running at low frequency, processor stopped waiting for an interrupt ? backup mode, main power supplies off, vddbu powered by a battery 9.7 periodic interval timer ? includes a 20-bit periodic coun ter, with less than 1 s accuracy ? includes a 12-bit interval overlay counter ? real time os or linux ? /windowsce ? compliant tick generator 9.8 watchdog timer ? 16-bit key-protected only-once-programmable counter ? windowed, prevents the processor to be in a dead-lock on the watchdog access 9.9 real-time timer ? real-time timer with 32-bit free-running back-up counter ? integrates a 16-bit programmable prescaler running on slow clock ? alarm register capable to generate a wake-up of the system through the shutdown controller
33 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 9.10 general-purpose back-up registers ? four 32-bit backup general-purpose registers 9.11 advanced interrupt controller ? controls the interrupt lines (nirq and nfiq) of the arm processor ? thirty-two individually maskable and vectored interrupt sources ? source 0 is reserved for the fast interrupt input (fiq) ? source 1 is reserved for system peripherals (pit, rtt, pmc, dbgu, etc.) ? programmable edge-triggered or level-sensitive internal sources ? programmable positive/negative edge-triggered or high/low level-sensitive ? three external sources plus the fast interrupt signal ? 8-level priority controller ? drives the normal interrupt of the processor ? handles priority of the interrupt sources 1 to 31 ? higher priority interrupts can be served during service of lower priority interrupt ? vectoring ? optimizes interrupt service routine branch and execution ? one 32-bit vector register per interrupt source ? interrupt vector register reads the corresponding current interrupt vector ?protect mode ? easy debugging by preventing automatic operations when protect modeis are enabled ?fast forcing ? permits redirecting any normal interrupt source on the fast interrupt of the processor 9.12 debug unit ? composed of two functions ?two-pin uart ? debug communication channel (dcc) support ?two-pin uart ? implemented features are 100% compatible with the standard atmel usart ? independent receiver and transmitter with a common programmable baud rate generator ? even, odd, mark or space parity generation ? parity, framing and overrun error detection ? automatic echo, local loopback and remote loopback channel modes ? support for two pdc channels with connection to receiver and transmitter ? debug communication channel support ? offers visibility of and interrupt trigge r from commrx and commtx signals from the arm processor?s ice interface
34 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 9.13 chip identification ?chip id: ? 0x329aa3a0 for the sam9xe512 ? 0x329a93a0 for the sam9xe256 ? 0x329973a0 for the sam9xe128 ? jtag id: 05b1_c03f ? arm926 tap id: 0x0792603f
35 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 10. peripherals 10.1 user interface the peripherals are mapped in the upper 256 mbytes of the address space between the addresses 0xfffa 0000 and 0xfffc ffff. each us er peripheral is allocated 16 kbytes of address space. a complete memory map is presented in figure 8-1 on page 21 . 10.2 peripheral identifier the at91sam9xe128/256/512 embeds a wide range of peripherals. table 10-1 defines the peripheral identifiers of the at91sam9xe128/256/512. a peripheral identifier is required for the control of the peripheral interrupt with the advanced interrupt controller and for the control of the peripheral clock with the power management controller. note: setting aic, sysc, uhp, adc and irq0-2 bits in the clock set/clear registers of the pmc has no effect. the adc clock is automatically started for the first conversion. in sleep mode the adc clock is automatically stopped after each conversion. table 10-1. at91sam9xe128/256/512 peripheral identifiers peripheral id peripheral mnemonic peripheral name external interrupt 0 aic advanced interrupt controller fiq 1 sysc system controller interrupt 2 pioa parallel i/o controller a 3 piob parallel i/o controller b 4 pioc parallel i/o controller c 5 adc analog-to-digital converter 6us0 usart 0 7us1 usart 1 8us2 usart 2 9 mci multimedia card interface 10 udp usb device port 11 twi0 two wire interface 0 12 spi0 serial peripheral interface 0 13 spi1 serial peripheral interface1 14 ssc synchronous serial controller 15 - reserved 16 - reserved 17 tc0 timer/counter 0 18 tc1 timer/counter 1 19 tc2 timer/counter 2 20 uhp usb host port 21 emac ethernet mac 22 isi image sensor interface 23 us3 usart 3 24 us4 usart 4 25 twi1 two wire interface 1 26 tc3 timer/counter 3 27 tc4 timer/counter 4 28 tc5 timer/counter 5 29 aic advanced interrupt controller irq0 30 aic advanced interrupt controller irq1 31 aic advanced interrupt controller irq2
36 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 10.2.1 peripheral interrupts and clock control 10.2.1.1 system interrupt the system interrupt in source 1 is the wired-or of the interrupt signals coming from: ? the sdram controller ? the debug unit ? the periodic interval timer ? the real-time timer ? the watchdog timer ? the reset controller ? the power management controller ? enhanced embedded flash controller the clock of these peripherals cannot be deacti vated and peripheral id 1 can only be used within the advanced interrupt controller. 10.2.1.2 external interrupts all external interrupt signals, i.e., the fast interrupt signal fiq or the interrupt signals irq0 to irq2, use a dedicated peripheral id. however, there is no clock control associated with these peripheral ids. 10.3 peripheral signals mu ltiplexing on i/o lines the at91sam9xe128/256/512 features 3 pio controllers, pioa, piob, pioc, which multiplex the i/o lines of the peripheral set. each pio controller controls up to 32 lines. each line can be assigned to one of two peripheral functions, a or b. the multiplexing tables in the following paragraphs define how the i/o lines of the peripherals a and b are multiplexed on the pio controllers. the two columns ?function? and ?comments? have been inserted in this table for the user?s own comments; they may be used to track how pins are defined in an application. note that some peripheral function which are output only, might be duplicated within the both tables. the column ?reset state? indicates whether the pio line resets in i/o mode or in peripheral mode. if i/o is mentioned, the pio line resets in input with the pull-up enabled, so that the device is maintained in a static state as soon as the reset is released. as a result, the bit corre- sponding to the pio line in the register pio_ psr (peripheral status register) resets low. if a signal name is mentioned in the ?reset stat e? column, the pio line is assigned to this func- tion and the corresponding bit in pio_psr resets high. this is the case of pins controlling memories, in particular the address lines, which requ ire the pin to be driven as soon as the reset is released. note that the pull-up resistor is also enabled in this case.
37 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 10.3.1 pio controller a multiplexing note: 1. not available in the 208-lead pqfp package. table 10-2. multiplexing on pio controller a pio controller a application usage i/o line peripheral a peripheral b comments reset state power supply function comments pa0 spi0_miso mcdb0 i/o vddiop0 pa1 spi0_mosi mccdb i/o vddiop0 pa2 spi0_spck i/o vddiop0 pa3 spi0_npcs0 mcdb3 i/o vddiop0 pa4 rts2 mcdb2 i/o vddiop0 pa5 cts2 mcdb1 i/o vddiop0 pa6 mcda0 i/o vddiop0 pa7 mccda i/o vddiop0 pa8 mcck i/o vddiop0 pa9 mcda1 i/o vddiop0 pa10 mcda2 etx2 i/o vddiop0 pa11 mcda3 etx3 i/o vddiop0 pa12 etx0 i/o vddiop0 pa13 etx1 i/o vddiop0 pa14 erx0 i/o vddiop0 pa15 erx1 i/o vddiop0 pa16 etxen i/o vddiop0 pa17 erxdv i/o vddiop0 pa18 erxer i/o vddiop0 pa19 etxck i/o vddiop0 pa20 emdc i/o vddiop0 pa21 emdio i/o vddiop0 pa22 adtrg etxer i/o vddiop0 pa23 twd0 etx2 i/o vddiop0 pa24 twck0 etx3 i/o vddiop0 pa25 tclk0 erx2 i/o vddiop0 pa26 tioa0 erx3 i/o vddiop0 pa27 tioa1 erxck i/o vddiop0 pa28 tioa2 ecrs i/o vddiop0 pa29 sck1 ecol i/o vddiop0 pa 3 0 (1) sck2 rxd4 i/o vddiop0 pa 3 1 (1) sck0 txd4 i/o vddiop0
38 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 10.3.2 pio controller b multiplexing note: 1. not available in the 208-lead pqfp package. table 10-3. multiplexing on pio controller b pio controller b application usage i/o line peripheral a peripheral b comments reset state power supply function comments pb0 spi1_miso tioa3 i/o vddiop0 pb1 spi1_mosi tiob3 i/o vddiop0 pb2 spi1_spck tioa4 i/o vddiop0 pb3 spi1_npcs0 tioa5 i/o vddiop0 pb4 txd0 i/o vddiop0 pb5 rxd0 i/o vddiop0 pb6 txd1 tclk1 i/o vddiop0 pb7 rxd1 tclk2 i/o vddiop0 pb8 txd2 i/o vddiop0 pb9 rxd2 i/o vddiop0 pb10 txd3 isi_d8 i/o vddiop1 pb11 rxd3 isi_d9 i/o vddiop1 pb12 (1) twd1 isi_d10 i/o vddiop1 pb13 (1) twck1 isi_d11 i/o vddiop1 pb14 drxd i/o vddiop0 pb15 dtxd i/o vddiop0 pb16 tk0 tclk3 i/o vddiop0 pb17 tf0 tclk4 i/o vddiop0 pb18 td0 tiob4 i/o vddiop0 pb19 rd0 tiob5 i/o vddiop0 pb20 rk0 isi_d0 i/o vddiop1 pb21 rf0 isi_d1 i/o vddiop1 pb22 dsr0 isi_d2 i/o vddiop1 pb23 dcd0 isi_d3 i/o vddiop1 pb24 dtr0 isi_d4 i/o vddiop1 pb25 ri0 isi_d5 i/o vddiop1 pb26 rts0 isi_d6 i/o vddiop1 pb27 cts0 isi_d7 i/o vddiop1 pb28 rts1 isi_pck i/o vddiop1 pb29 cts1 isi_vsync i/o vddiop1 pb30 pck0 isi_hsync i/o vddiop1 pb31 pck1 isi_mck i/o vddiop1
39 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 10.3.3 pio controller c multiplexing note: 1. not available in the 208-lead pqfp package. table 10-4. multiplexing on pio controller c pio controller c application usage i/o line peripheral a peripheral b comment s reset state power supply function comments pc0 sck3 ad0 i/o vddiop0 pc1 pck0 ad1 i/o vddiop0 pc2 (1) pck1 ad2 i/o vddiop0 pc3 (1) spi1_npcs3 ad3 i/o vddiop0 pc4 a23 spi1_npcs2 a23 vddiom pc5 a24 spi1_npcs1 a24 vddiom pc6 tiob2 cfce1 i/o vddiom pc7 tiob1 cfce2 i/o vddiom pc8 ncs4/cfcs0 rts3 i/o vddiom pc9 ncs5/cfcs1 tiob0 i/o vddiom pc10 a25/cfrnw cts3 a25 vddiom pc11 ncs2 spi0_npcs1 i/o vddiom pc12 (1) irq0 ncs7 i/o vddiom pc13 fiq ncs6 i/o vddiom pc14 ncs3/nandcs irq2 i/o vddiom pc15 nwait irq1 i/o vddiom pc16 d16 spi0_npcs2 i/o vddiom pc17 d17 spi0_npcs3 i/o vddiom pc18 d18 spi1_npcs1 i/o vddiom pc19 d19 spi1_npcs2 i/o vddiom pc20 d20 spi1_npcs3 i/o vddiom pc21 d21 ef100 i/o vddiom pc22 d22 tclk5 i/o vddiom pc23 d23 i/o vddiom pc24 d24 i/o vddiom pc25 d25 i/o vddiom pc26 d26 i/o vddiom pc27 d27 i/o vddiom pc28 d28 i/o vddiom pc29 d29 i/o vddiom pc30 d30 i/o vddiom pc31 d31 i/o vddiom
40 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 10.4 embedded peripherals 10.4.1 serial peripheral interface ? supports communication with serial external devices ? four chip selects with external decoder support allow communication with up to 15 peripherals ? serial memories, such as dataflash and 3-wire eeproms ? serial peripherals, such as adcs, dacs, lcd controllers, can controllers and sensors ? external co-processors ? master or slave serial peripheral bus interface ? 8- to 16-bit programmable data length per chip select ? programmable phase and polarity per chip select ? programmable transfer delays between consecutive transfers and between clock and data per chip select ? programmable delay between consecutive transfers ? selectable mode fault detection ? very fast transfers supported ? transfers with baud rates up to mck ? the chip select line may be left active to speed up transfers on the same device 10.4.2 two-wire interface ? master, multi-master and slave modes supported ? general call supported in slave mode ? connection to pdc channel 10.4.3 usart ? programmable baud rate generator ? 5- to 9-bit full-duplex synchronous or asynchronous serial communications ? 1, 1.5 or 2 stop bits in asynchronous mode or 1 or 2 stop bits in synchronous mode ? parity generation and error detection ? framing error detection, overrun error detection ? msb- or lsb-first ? optional break generation and detection ? by 8 or by 16 oversampling receiver frequency ? hardware handshaking rts-cts ? receiver time-out and transmitter timeguard ? optional multi-drop mode with address generation and detection ? optional manchester encoding ? rs485 with driver control signal ? iso7816, t = 0 or t = 1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit
41 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? irda modulation and demodulation ? communication at up to 115.2 kbps ? test modes ? remote loopback, local loopback, automatic echo 10.4.4 serial synchronous controller ? provides serial synchronous communication links used in audio and telecom applications (with codecs in master or slave modes, i 2 s, tdm buses, magnetic card reader, etc.) ? contains an independent receiver and transmitter and a common clock divider ? offers a configurable frame sync and data length ? receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal ? receiver and transmitter include a data signal , a clock signal and a frame synchronization signal 10.4.5 timer counter ? six 16-bit timer counter channels ? wide range of functions including: ? frequency measurement ? event counting ? interval measurement ? pulse generation ?delay timing ? pulse width modulation ? up/down capabilities ? each channel is user-configurable and contains: ? three external clock inputs ? five internal clock inputs ? two multi-purpose input/output signals ? two global registers that act on all three tc channels 10.4.6 multimedia card interface ? one double-channel multimedia card interface ? compatibility with multimedia ca rd specification version 2.2 ? compatibility with sd memory ca rd specification version 1.0 ? compatibility with sdio specification version v1.0. ? cards clock rate up to master clock divided by 2 ? embedded power management to slow down clock rate when not used ? mci has two slot, each supporting ? one slot for one multimediacard bus (up to 30 cards) or ? one sd memory card ? support for stream, block and multi-block data read and write
42 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 10.4.7 usb host port ? compliance with open hci rev 1.0 specification ? compliance with usb v2.0 full-sp eed and low-speed specification ? supports both low-speed 1.5 mbps and full-speed 12 mbps devices ? root hub integrated with two downstream usb ports in the 217-lfbga package ? two embedded usb transceivers ? supports power management ? operates as a master on the matrix 10.4.8 usb device port ? usb v2.0 full-speed compliant, 12 mbits per second ? embedded usb v2.0 full-speed transceiver ? embedded 2,688-byte dual-port ram for endpoints ? suspend/resume logic ? ping-pong mode (two memory banks) for isochronous and bulk endpoints ? eight general-purpose endpoints ? endpoint 0 and 3: 64 bytes, no ping-pong mode ? endpoint 1, 2, 6, 7: 64 bytes, ping-pong mode ? endpoint 4 and 5: 512 bytes, ping-pong mode ? embedded pad pull-up 10.4.9 ethernet 10/100 mac ? compatibility with ieee standard 802.3 ? 10 and 100 mbits per second data through put capability ? full- and half-duplex operations ? mii or rmii interface to the physical layer ? register interface to address, data, status and control registers ? dma interface, operating as a master on the memory controller ? interrupt generation to signal receive and transmit completion ? 128-byte transmit and 128-byte receive fifos ? automatic pad and crc generation on transmitted frames ? address checking logic to recognize four 48-bit addresses ? support promiscuous mode where all valid frames are copied to memory ? support physical layer management through mdio interface control of alarm and update time/calendar data in 10.4.10 image sensor interface ? itu-r bt. 601/656 8-bit mode external interface support ? support for itu-r bt.656-4 sav and eav synchronization ? vertical and horizontal resolutions up to 2048 x 2048 ? preview path up to 640*480 ? support for packed data formatting for ycbcr 4:2:2 formats
43 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? preview scaler to generate smaller size image 10.4.11 analog-to-digital converter ? 4-channel adc ? 10-bit 312k samples/sec. successive approximation register adc ? -2/+2 lsb integral non linearity, -1/+1 lsb differential non linearity ? individual enable and disable of each channel ? external voltage reference for better accuracy on low voltage inputs ? multiple trigger source ? hardware or software trigger ? external trigger pin ? timer counter 0 to 2 outputs tioa0 to tioa2 trigger ? sleep mode and conversion sequencer ? automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels ? four analog inputs shared with digital signals
44 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary
45 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 11. arm926ej-s processor 11.1 overview the arm926ej-s processor is a member of the arm9 ? family of general-purpose microproces- sors. the arm926ej-s implements arm architectu re version 5tej and is targeted at multi- tasking applications where full memory management, high performance, low die size and low power are all important features. the arm926ej-s processor supports the 32- bit arm and 16-bit thumb instruction sets, enabling the user to trade off between high performance and high code density. it also supports 8-bit java instruction set and includes features fo r efficient execution of java bytecode, provid- ing a java performance similar to a jit (just-in-time compilers), for the next generation of java- powered wireless and embedded devices. it includes an enhanced multiplier design for improved dsp performance. the arm926ej-s processor supports the arm debug architecture and includes logic to assist in both hardware and software debug. the arm926ej-s provides a complete high performance processor subsystem, including: ? an arm9ej-s ? integer core ? a memory management unit (mmu) ? separate instruction and data amba ahb bus interfaces ? separate instruction and data tcm interfaces table 11-1. reference document table owner-reference denomination arm ltd. - dd10198b arm926ejs technical reference manual arm ltd. - dd10222b arm9ej-s technical reference manual
46 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 11.2 block diagram figure 11-1. arm926ej-s internal functional block diagram cp15 system configuration coprocessor external coprocessor interface trace port interface arm9ej-s processor core dtcm interface data tlb instruction tlb itcm interface data cache ahb interface and write buffer instruction cache write data read data instruction fetches data address instruction address data address instruction address instruction tcm data tcm mmu amba ahb external coprocessors etm9
47 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 11.3 arm9ej-s processor 11.3.1 arm9ej-s operating states the arm9ej-s processor can operate in three different states, each with a specific instruction set: ? arm state: 32-bit, word-aligned arm instructions. ? thumb state: 16-bit, halfword-aligned thumb instructions. ? jazelle state: variable length, byte-aligned jazelle instructions. in jazelle state, all instru ction fetches are in words. 11.3.2 switching state the operating state of the arm9ej-s core can be switched between: ? arm state and thumb state using the bx and blx instructions, and loads to the pc ? arm state and jazelle state using the bxj instruction all exceptions are entered, handled and exited in arm state. if an exception occurs in thumb or jazelle states, the processor reverts to arm state. the transition back to thumb or jazelle states occurs automatically on return from the exception handler. 11.3.3 instruction pipelines the arm9ej-s core uses two kinds of pipelines to increase the speed of the flow of instructions to the processor. a five-stage (five clock cycles) pipeline is used for arm and thumb states. it consists of fetch, decode, execute, memory and writeback stages. a six-stage (six clock cycles) pipeline is us ed for jazelle state it consists of fetch, jazelle/decode (two clock cycles), execute, memory and writeback stages. 11.3.4 memory access the arm9ej-s core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. words must be aligned to four-byte boundaries, half-words must be aligned to two-byte boundaries and bytes can be placed on any byte boundary. because of the nature of the pipelines, it is possible for a value to be required for use before it has been placed in the register bank by the actions of an earlier instruction. the arm9ej-s con- trol logic automatically detects these cases and stalls the core or forward data. 11.3.5 jazelle technology the jazelle technology enables direct and efficient execution of java byte codes on arm pro- cessors, providing high performance for the next generation of java-powered wireless and embedded devices. the new java feature of arm9ej-s can be described as a hardware emulation of a jvm (java virtual machine). java mode will appear as another state: instead of executing arm or thumb instructions, it executes java byte codes. the java byte code decoder logic implemented in arm9ej-s decodes 95% of executed byte codes and turns them into ar m instructions without any overhead, while less frequently used byte codes are broken down into optimized sequences of arm instructions. the hardware/software split is invisible to the programmer, invisible to the application and invisible to the operating system . all existing arm registers are re-used in jazelle state and all registers then have particular functions in this mode.
48 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary minimum interrupt latency is maintained across both arm state and java state. since byte codes execution can be restarted, an interrupt automatically triggers the core to switch from java state to arm state for the execution of the interrupt handler. this means that no special provision has to be made for handling interrupts while executing byte codes, whether in hard- ware or in software. 11.3.6 arm9ej-s operating modes in all states, there are seven operation modes: ? user mode is the usual arm program executio n state. it is used for executing most application programs ? fast interrupt (fiq) mode is used for handling fast interrupts. it is suitable for high-speed data transfer or channel process ? interrupt (irq) mode is used for general-purpose interrupt handling ? supervisor mode is a protected mode for the operating system ? abort mode is entered after a data or instruction prefetch abort ? system mode is a privileged user mode for the operating system ? undefined mode is entered when an undefined instruction exception occurs mode changes may be made under software control, or may be brought about by external inter- rupts or exception processing. most application programs execute in user mode. the non-user modes, known as privileged modes, are entered in or der to service interrupts or exceptions or to access protecte d resources.
49 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 11.3.7 arm9ej-s registers the arm9ej-s core has a total of 37 registers. ? 31 general-purpose 32-bit registers ? 6 32-bit status registers table 11-2 shows all the registers in all modes. the arm state register set contains 16 directly-a ccessible registers, r0 to r15, and an additional register, the current program status register (cpsr). registers r0 to r13 are general-purpose registers used to hold either data or address va lues. register r14 is used as a link register that holds a value (return address) of r15 when bl or blx is executed. register r15 is used as a pro- gram counter (pc), whereas the current program status register (cpsr) contains condition code flags and the current mode bits. in privileged modes (fiq, supervisor, abort, irq, undefined), mode-specific banked registers (r8 to r14 in fiq mode or r13 to r14 in the other modes) become available. the corresponding banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und are similarly used to hold the val- table 11-2. arm9tdmi modes and registers layout user and system mode supervisor mode abort mode undefined mode interrupt mode fast interrupt mode r0 r0 r0 r0 r0 r0 r1 r1 r1 r1 r1 r1 r2 r2 r2 r2 r2 r2 r3 r3 r3 r3 r3 r3 r4 r4 r4 r4 r4 r4 r5 r5 r5 r5 r5 r5 r6 r6 r6 r6 r6 r6 r7 r7 r7 r7 r7 r7 r8 r8 r8 r8 r8 r8_fiq r9 r9 r9 r9 r9 r9_fiq r10 r10 r10 r10 r10 r10_fiq r11 r11 r11 r11 r11 r11_fiq r12 r12 r12 r12 r12 r12_fiq r13 r13_svc r13_abort r13_undef r13_irq r13_fiq r14 r14_svc r14_abort r14_undef r14_irq r14_fiq pc pc pc pc pc pc cpsr cpsr cpsr cpsr cpsr cpsr spsr_svc spsr_abor t spsr_unde f spsr_irq spsr_fiq mode-specific banked registers
50 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ues (return address for each mode) of r15 (pc) when interrupts and exceptions arise, or when bl or blx instructions are executed within interrupt or exception routines. there is another reg- ister called saved program status register (spsr) that becomes available in privileged modes instead of cpsr. this register contains condition code flags and the current mode bits saved as a result of the exception that caused entry to the current (privileged) mode. in all modes and due to a software agreement, register r13 is used as stack pointer. the use and the function of all the registers described above should obey arm procedure call standard (apcs) which defines: ? constraints on the use of registers ? stack conventions ? argument passing and result return for more details, refer to arm software development kit. the thumb state register set is a subset of the arm state set. the programmer has direct access to: ? eight general-purpose registers r0-r7 ? stack pointer, sp ? link register, lr (arm r14) ?pc ? cpsr there are banked re gisters sps, lrs and spsrs for each priv ileged mode (for more details see the arm9ej-s technical reference manual, revision r1p2 page 2-12). 11.3.7.1 status registers the arm9ej-s core contains one cpsr, and fi ve spsrs for exception handlers to use. the program status registers: ? hold information about the most recently performed alu operation ? control the enabling and disabling of interrupts ? set the processor operation mode figure 11-2. status register format figure 11-2 shows the status register format, where: ? n: negative, z: zero, c: carry, and v: overflow are the four alu flags nz cv q jift mode reserved mode bits thumb state bit fiq disable irq disable jazelle state bit reserved sticky overflow overflow carry/borrow/extend zero negative/less than 31 30 29 28 27 24 7 6 5 0
51 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? the sticky overflow (q) flag can be set by certain multiply and fractional arithmetic instructions like qadd, qdadd, qsub, qdsub, smlaxy, and smlawy needed to achieve dsp operations. the q flag is sticky in that, when set by an instru ction, it remains set unt il explicitly cleared by an msr instruction writing to the cpsr. instructions cannot execute conditionally on the status of the q flag. ? the j bit in the cpsr indicates when the ar m9ej-s core is in jazelle state, where: ? j = 0: the processor is in arm or thumb state, depending on the t bit ? j = 1: the processor is in jazelle state. ? mode: five bits to encode the current processor mode 11.3.7.2 exceptions 11.3.7.3 exception types and priorities the arm9ej-s supports five types of exceptions. each type drives the arm9ej-s in a privi- leged mode. the types of exceptions are: ? fast interrupt (fiq) ? normal interrupt (irq) ? data and prefetched aborts (abort) ? undefined instruction (undefined) ? software interrupt and reset (supervisor) when an exception occurs, the banked version of r14 and the spsr for the exception mode are used to save the state. more than one exception can happen at a time, therefore the arm9ej-s takes the arisen excep- tions according to the following priority order: ? reset (highest priority) ? data abort ?fiq ?irq ?prefetch abort ? bkpt, undefined instruction, and softwa re interrupt (swi) (lowest priority) the bkpt, or undefined instruction, and swi exceptions are mutually exclusive. note that there is one exception in the priority scheme: when fiqs are enabled and a data abort occurs at the same time as an fiq, the arm9ej-s core enters the data abort handler, and pro- ceeds immediately to fiq vector. a normal return from the fiq causes the data abort handler to resume execution. data aborts must have higher priority than fiqs to ensure that the transfer error does not escape detection. 11.3.7.4 exception modes and handling exceptions arise whenever the normal flow of a program must be halted temporarily, for exam- ple, to service an interrupt from a peripheral. when handling an arm exception, the arm9ej-s core performs the following operations:
52 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 1. preserves the address of the next instruction in the appropriate link register that cor- responds to the new mode that has been entered. when the exception entry is from: ? arm and jazelle states, the arm9ej-s copies the address of the next instruction into lr (current pc(r15) + 4 or pc + 8 depending on the exception). ? thumb state, the arm9ej-s writes the value of the pc into lr, offset by a value (current pc + 2, pc + 4 or pc + 8 depending on the exception) that causes the program to resume from the correct place on return. 2. copies the cpsr into the appropr iate spsr. 3. forces the cpsr mode bits to a value that depends on the exception. 4. forces the pc to fetch the next instruction from the relevant exception vector. the register r13 is also banked across exception modes to provide each exception handler with private stack pointer. the arm9ej-s can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. when an exception has completed, the exception handler must move both the return value in the banked lr minus an offset to the pc and the spsr to the cpsr. t he offset value varies according to the type of exception. this action restores both pc and the cpsr. the fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the requirement for register saving wh ich minimizes the overhead of context switching. the prefetch abort is one of the aborts that indicates that the current memory access cannot be completed. when a prefetch abort occurs, the arm9ej-s marks the prefetched instruction as invalid, but does not take the exception until th e instruction reaches the execute stage in the pipeline. if the instruction is not executed, for ex ample because a branch occurs while it is in the pipeline, the abort does not take place. the breakpoint (bkpt) instruction is a new feat ure of arm9ej-s that is destined to solve the problem of the prefetch abort. a breakpoint instruction operates as though the instruction caused a prefetch abort. a breakpoint instruction does not cause the arm9ej-s to take the prefetch abort exception until the instruction reaches the execute stage of the pi peline. if the instruction is not executed, for example because a branch occurs while it is in the pipeline, the breakpoint does not take place. 11.3.8 arm instruction set overview the arm instruction set is divided into: ? branch instructions ? data processing instructions ? status register transfer instructions ? load and store instructions ? coprocessor instructions ? exception-generating instructions arm instructions can be executed conditionally. every instruction contains a 4-bit condition code field (bits[31:28]). for further details, see the arm technical reference manual referenced in table 11-1 on page 45 .
53 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary table gives the arm instruction mnemonic list. arm instruction mnemonic list mnemonic operation mnemonic operation mov move mvn move not add add adc add with carry sub subtract sbc subtract with carry rsb reverse subtract rsc reverse subtract with carry cmp compare cmn compare negated tst test teq test equivalence and logical and bic bit clear eor logical exclusive or orr logical (inclusive) or mul multiply mla multiply accumulate smull sign long multiply umull unsigned long multiply smlal signed long multiply accumulate umlal unsigned long multiply accumulate msr move to status register mrs move from status register b branch bl branch and link bx branch and exchange swi software interrupt ldr load word str store word ldrsh load signed halfword ldrsb load signed byte ldrh load half word strh store half word ldrb load byte strb store byte ldrbt load register byte with translation strbt store register byte with translation ldrt load register with translation s trt store register with translation ldm load multiple stm store multiple swp swap word swpb swap byte mcr move to coprocessor mrc move from coprocessor ldc load to coprocessor stc store from coprocessor cdp coprocessor data processing
54 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 11.3.9 new arm instruction set . notes: 1. a thumb blx contains two consecutiv e thumb instructions, and takes four cycles. 11.3.10 thumb instruction set overview the thumb instruction set is a re-encoded subset of the arm instruction set. the thumb instruction set is divided into: ? branch instructions ? data processing instructions ? load and store instructions ? load and store multiple instructions ? exception-generating instruction table 11-3 shows the thumb instruction set, for fu rther details, see the arm technical refer- ence manual referenced in table 11-1 on page 45 . table 11-4 gives the thumb instruction mnemonic list. table 11-3. new arm instruction mnemonic list mnemonic operation mnemonic operation bxj branch and exchange to java mrrc move double from coprocessor blx (1) branch, link and exchange mcr2 alternative move of arm reg to coprocessor smlaxy signed multiply accumulate 16 * 16 bit mcrr move double to coprocessor smlal signed multiply accumulate long cdp2 alternative coprocessor data processing smlawy signed multiply accumulate 32 * 16 bit bkpt breakpoint smulxy signed multiply 16 * 16 bit pld soft preload, memory prepare to load from address smulwy signed multiply 32 * 16 bit strd store double qadd saturated add stc2 alternative store from coprocessor qdadd saturated add with double ldrd load double qsub saturated subtract ldc2 alternative load to coprocessor qdsub saturated subtract with double clz count leading zeroes table 11-4. thumb instruction mnemonic list mnemonic operation mnemonic operation mov move mvn move not add add adc add with carry sub subtract sbc subtract with carry cmp compare cmn compare negated tst test neg negate
55 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 11.4 cp15 coprocessor coprocessor 15, or system control coprocessor cp15, is used to configure and control all the items in the list below: ? arm9ej-s ? caches (icache, dcache and write buffer) ?tcm ?mmu ? other system options to control these features, cp15 provides 16 additional registers. see table 11-5 . and logical and bic bit clear eor logical exclusive or or r logical (inclusive) or lsl logical shift left lsr logical shift right asr arithmetic shift right ror rotate right mul multiply blx branch, link, and exchange b branch bl branch and link bx branch and exchange swi software interrupt ldr load word str store word ldrh load half word strh store half word ldrb load byte strb store byte ldrsh load signed halfword ldrsb load signed byte ldmia load multiple stmia store multiple push push register to stack pop pop register from stack bcc conditional branch bkpt breakpoint table 11-4. thumb instruction mnemonic list (continued) mnemonic operation mnemonic operation table 11-5. cp15 registers register name read/write 0 id code (1) read/unpredictable 0 cache type (1) read/unpredictable 0 tcm status (1) read/unpredictable 1 control read/write 2 translation table base read/write 3 domain access control read/write 4 reserved none 5 data fault status (1) read/write 5 instruction fault status (1) read/write 6 fault address read/write
56 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary notes: 1. register locations 0,5, and 13 each provid e access to more than one register. the register accessed depends on the value of the opcode_2 field. 2. register location 9 provides access to more than one register. the register accessed depends on the value of the crm field. 7 cache operations read/write 8 tlb operations unpredictable/write 9 cache lockdown (2) read/write 9 tcm region read/write 10 tlb lockdown read/write 11 reserved none 12 reserved none 13 fcse pid (1) read/write 13 context id (1) read/write 14 reserved none 15 test configuration read/write table 11-5. cp15 registers register name read/write
57 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 11.4.1 cp15 registers access cp15 registers can only be accessed in privileged mode by: ? mcr (move to coprocessor from arm register) instruction is used to write an arm register to cp15. ? mrc (move to arm register from coprocessor) instruction is used to read the value of cp15 to an arm register. other instructions like cdp, ldc, stc can cause an undefined instruction exception. the assembler code for these instructions is: mcr/mrc{cond} p15, opcode_1, rd, crn, crm, opcode_2. the mcr, mrc instructions bit pattern is shown below: ? crm[3:0]: specified coprocessor action determines specific coprocessor action. its value is dependen t on the cp15 register used. for details, refer to cp15 spe- cific register behavior. ? opcode_2[7:5] determines specific coprocessor operation code. by default, set to 0. ? rd[15:12]: arm register defines the arm register whose value is transferred to the co processor. if r15 is chosen, the result is unpredictable. ? crn[19:16]: coprocessor register determines the destination coprocessor register. ? l: instruction bit 0 = mcr instruction 1 = mrc instruction ? opcode_1[23:20]: coprocessor code defines the coprocessor specific code. value is c15 for cp15. ? cond [31:28]: condition for more details, see chapter 2 in arm926ej-s trm. 31 30 29 28 27 26 25 24 cond 1110 23 22 21 20 19 18 17 16 opcode_1 l crn 15 14 13 12 11 10 9 8 rd 1111 76543210 opcode_2 1 crm
58 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 11.5 memory management unit (mmu) the arm926ej-s processor implements an enhanced arm architecture v5 mmu to provide vir- tual memory features required by operating systems like symbian ? os, windowsce ? , and linux ? . these virtual memory features are memory access permission controls and virtual to physical address translations. the virtual address generated by the cpu core is converted to a modified virtual address (mva) by the fcse (fast context switch extens ion) using the value in cp15 register13. the mmu translates modified virtual addresses to physical addresses by using a single, two-level page table set stored in physical memory. each entry in the set contains the access permissions and the physical address that correspond to the virtual address. the first level translation tables contain 4096 entries indexed by bits [31:20] of the mva. these entries contain a pointer to either a 1 mb secti on of physical memory along with attribute infor- mation (access permissions, domain, etc.) or an entry in the second level translation tables; coarse table and fine table. the second level translation tables contain tw o subtables, coarse table and fine table. an entry in the coarse table contains a pointer to both large pages and small pages along with access permissions. an entry in the fine table contains a pointer to large, small and tiny pages. table 11-6 shows the different attributes of each page in the physical memory. the mmu consists of: ? access control logic ? translation look-aside buffer (tlb) ? translation table walk hardware 11.5.1 access control logic the access control logic controls access information for every entry in the translation table. the access control logic checks two pieces of access information: domain and access permissions. the domain is the primary access control mechanism for a memory region; there are 16 of them. it defines the conditions necessary for an access to proceed. the domain determines whether the access permissions are used to qualify the access or whether they should be ignored. the second access control mechanism is access permissions that are defined for sections and for large, small and tiny pages. sections and tiny pages have a single set of access permissions whereas large and small pages can be associated with 4 sets of access permissions, one for each subpage (quarter of a page). 11.5.2 translation look-aside buffer (tlb) the translation look-aside buffer (tlb) caches translated entries and thus avoids going through the translation process every time. when the tlb contains an entry for the mva (modi- table 11-6. mapping details mapping name mapping size acce ss permission by subpage size section 1m byte section - large page 64k bytes 4 separated subpages 16k bytes small page 4k bytes 4 separated subpages 1k byte tiny page 1k byte tiny page -
59 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary fied virtual address), the access control logic dete rmines if the access is permitted and outputs the appropriate physical address corresponding to the mva. if access is not permitted, the mmu signals the cpu core to abort. if the tlb does not contain an entry for the mva, the translation table walk hardware is invoked to retrieve the translation information from the translation table in physical memory. 11.5.3 translation table walk hardware the translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets the ph ysical address and access permissions and updates the tlb. the number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access or a page-mapped access. there are three sizes of page-mapped accesses and one size of section-mapped access. page- mapped accesses are for large pages, small pages and tiny pages. the translation process always begins with a level one fetch. a section-mapped access requires only a level one fetch, but a page-mapped access requires an additional level two fetch. for further details on the mmu, please refer to chapter 3 in arm926ej-s technical reference manual. 11.5.4 mmu faults the mmu generates an abort on the following types of faults: ? alignment faults (for data accesses only) ? translation faults ? domain faults ? permission faults the access control mechanism of the mmu detects the conditions that produce these faults. if the fault is a result of memory access, the mmu aborts the access and signals the fault to the cpu core.the mmu retains status and address information about faults generated by the data accesses in the data fault status register and fault address register. it also retains the status of faults generated by instruction fetches in the instruction fault status register. the fault status register (register 5 in cp15) indicates the cause of a data or prefetch abort, and the domain number of the aborted access when it happens. the fault address register (register 6 in cp15) holds the mva associated with the access that caused the data abort. for further details on mmu faults, please refer to chapte r 3 in arm926ej-s technical reference manual.
60 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 11.6 caches and write buffer the arm926ej-s contains a 16-kbyte instruction cache (icache), a 8-kbyte data cache (dcache), and a write buffer. although the icache and dcache share common features, each still has some specific mechanisms. the caches (icache and dcache) are four-way se t associative, addressed, indexed and tagged using the modified virtual address (mva), with a ca che line length of eight words with two dirty bits for the dcache. the icache and dcache provide mechanisms for cache lockdown, cache pollution control, and line replacement. a new feature is now supported by arm926ej-s caches called allocate on read-miss commonly known as wrapping. this feature enables the caches to perform cr itical word first cache refilling. this means that when a request for a word caus es a read-miss, the cache performs an ahb access. instead of loading the whole line (eight words), the cache loads the critical word first, so the processor can reach it quickly, and then the remaining words, no matter where the word is located in the line. the caches and the write buffer are controlled by the cp15 register 1 (control), cp15 register 7 (cache operations) and cp15 register 9 (cache lockdown). 11.6.1 instruction cache (icache) the icache caches fetched instructions to be executed by the processor. the icache can be enabled by writing 1 to i bit of the cp15 register 1 and disabled by writing 0 to this same bit. when the mmu is enabled, all instruction fetches are subject to translation and permission checks. if the mmu is disabled, all instructions fetches are cachable, no protection checks are made and the physical address is flat-mapped to the modified virtual address. with the mva use disabled, context switching incurs icache cleaning and/or invalidating. when the icache is disabled, all instruction fetches appear on external memory (ahb) (see tables 4-1 and 4-2 in page 4-4 in arm926ej-s trm). on reset, the icache entries are invalidated and the icache is disabled. for best performance, icache should be enabled as soon as possible after reset. 11.6.2 data cache (dcache) and write buffer arm926ej-s includes a dcache and a write buffer to reduce the effect of main memory band- width and latency on data access performance. the operations of dcache and write buffer are closely connected. 11.6.2.1 dcache the dcache needs the mmu to be enabled. all data accesses are subject to mmu permission and translation checks. data acce sses that are aborted by the mmu do not cause linefills or data accesses to appear on the amba asb interface. if the mmu is disabled, all data accesses are noncachable, nonbufferable, with no protecti on checks, and appear on the ahb bus. all addresses are flat-mapped, va = mva = pa, whic h incurs dcache cleaning and/or invalidating every time a context switch occurs. the dcache stores the physical address tag (pa tag) from which every line was loaded and uses it when writing modified lines back to external memory. this means that the mmu is not involved in write-back operations. each line (8 words) in the dcache has two dirty bits, one for the first four words and the other one for the second four words. these bits, if set, mark the associated half- lines as dirty. if the
61 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary cache line is replaced due to a linefill or a cache cl ean operation, the dirty bits are used to decide whether all, half or none is written back to memory. dcache can be enabled or disabled by writing either 1 or 0 to bit c in register 1 of cp15 (see tables 4-3 and 4-4 on page 4-5 in arm926ej-s trm). the dcache supports write-through and write-back cache operations, selected by memory region using the c and b bits in the mmu translation tables. the dcache contains an eight data word entr y, single address entry write-back buffer used to hold write-back data for cache line eviction or cleaning of dirty cache lines. the write buffer can hold up to 16 words of data and four separate addresses. dcache and write buffer operations are closely connected as their configuration is set in each section by the page descriptor in the mmu translation table. 11.6.2.2 write buffer the arm926ej-s contains a write buffer that has a 16-word data buffer and a four- address buf- fer. the write buffer is used for all writes to a bufferable region, write-through region and write- back region. it also allows to avoid stalling the processor when writes to external memory are performed. when a store occurs, data is written to the write buffer at core speed (high speed). the write buffer then completes the store to external memory at bus speed (typically slower than the core speed). during this time, the arm9ej-s processor can preform other tasks. dcache and write buffer support write-back and write-through memory regions, controlled by c and b bits in each section and page descriptor within the mmu translation tables. 11.6.2.3 write-though operation when a cache write hit occurs, the dcache line is updated. the updated data is then written to the write buffer which transfers it to external memory. when a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 11.6.2.4 write-back operation when a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-to-date with those in the external memory. when a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory.
62 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 11.7 bus interface unit the arm926ej-s features a bus interface unit (biu) that arbitrates and schedules ahb requests. the biu implements a multi-layer ahb, based on the ahb-lite protocol, that enables parallel access paths between multiple ahb masters and slaves in a system. this is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. the multi-master bus architecture has a number of benefits: ? it allows the development of multi-master systems with an increased bus bandwidth and a flexible architecture. ? each ahb layer becomes simple because it only has one master, so no arbitration or master- to-slave muxing is required. ahb layers, implementing ahb-lite protocol, do not have to support request and grant, nor do they have to support retry and split transactions. ? the arbitration becomes effective when more than one master wants to access the same slave simultaneously. 11.7.1 supported transfers the arm926ej-s processor performs all ahb accesses as single word, bursts of four words, or bursts of eight words. any arm9ej-s core request that is not 1, 4, 8 word s in size is split into packets of these sizes. note that the atmel bus is ahb-lite protocol compliant, hence it does not support split and retry requests. table 11-7 gives an overview of the supported transfers and different kinds of transactions they are used for. 11.7.2 thumb instruction fetches all instructions fetches, regardless of the state of arm9ej-s core, are made as 32-bit accesses on the ahb. if the arm9ej-s is in thumb state, then two instructions can be fetched at a time. 11.7.3 address alignment the arm926ej-s biu performs address alignment checking and aligns ahb addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries. table 11-7. supported transfers hburst[2:0] description single single transfer single transfer of word, half word, or byte: ? data write (ncnb, ncb, wt, or wb that has missed in dcache) ? data read (ncnb or ncb) ? nc instruction fetch (prefetched and non-prefetched) ? page table walk read incr4 four-word incrementing burst half-line cache write-back, instruction pr efetch, if enabled. four-word burst ncnb, ncb, wt, or wb write. incr8 eight-word incrementing burst full-line cache writ e-back, eight-word burst ncnb, ncb, wt, or wb write. wrap8 eight-word wrapping burst cache linefill
63 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 12. at91sam9xe debug and test 12.1 overview the at91sam9xe features a numb er of complementary debug an d test capabilities. a common jtag/ice (in-circuit emulator) port is used for standard debugging functions, such as down- loading code and single-stepping through programs. the debug unit provides a two-pin uart that can be used to upload an application into internal sram. it manages the interrupt handling of the internal commtx and commrx signals t hat trace the activity of the debug communica- tion channel. a set of dedicated deb ug and test input/ou tput pins gives direct acce ss to these capabilities from a pc-based test environment.
64 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 12.2 block diagram figure 12-1. debug and test block diagram ice-rt arm9ej-s pdc dbgu pio drxd dtxd tms tck tdi jtagsel tdo tst reset and test tap: test access port boundary port ice/jtag ta p arm926ej-s por rtck ntrst
65 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 12.3 application examples 12.3.1 debug environment figure 12-2 on page 65 shows a complete debug environment example. the ice/jtag inter- face is used for standard debugging functions, such as downloading code and single-stepping through the program. a software debugger running on a personal computer provides the user interface for configuring a trace port interf ace utilizing the ice/jtag interface. figure 12-2. application debug and trace environment example at91sam9xe-based application board ice/jtag interface host debugger ice/jtag connector at91sam9xe terminal rs232 connector
66 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 12.3.2 test environment figure 12-3 on page 66 shows a test environment example. test vectors are sent and inter- preted by the tester. in this example, the ?board in test? is designed using a number of jtag- compliant devices. these devi ces can be connected to form a single scan chain. figure 12-3. application test environment example 12.4 debug and test pin description tester jtag interface ice/jtag connector test adaptor chip 2 chip n chip 1 at91sam9xe-based application board in test at91sam9xe table 12-1. debug and test pin list pin name function type active level reset/test nrst microcontroller reset input/output low tst test mode select input high ice and jtag ntrst test reset signal input low tck test clock input tdi test data in input tdo test data out output tms test mode select input rtck returned test clock output jtagsel jtag selection input debug unit drxd debug receive data input dtxd debug transmit data output
67 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 12.5 jtag port pins tms, tdi and tck are schmitt trigger inputs and have no pull-up resistors. tdo and rtck are outputs, driven at up to vddiop0, and have no pull-up resistors. the jtagsel pin is used to select the jtag boundary scan when asserted at a high level (tied to vddbu). it integrates a permanent pull-down resistor of about 15 k to gndbu, so that it can be left unconnected for normal operations. all the jtag signals are supplied with vddiop0. 12.6 functional description 12.6.1 test pin one dedicated pin, tst, is used to define the device operating mode. the user must make sure that this pin is tied at low level to ensure normal operating conditions. other values associated with this pin are reserved for manufacturing test. 12.6.2 embedded in-circuit emulator the arm9ej-s embedded in-circuit emulator-rt is supported via the ice/jtag port. it is con- nected to a host computer via an ice interface. debug support is implemented using an arm9ej-s core embedded within the arm926ej-s. the internal state of the arm926ej-s is examined through an ice/jtag port which allows instructions to be serially inserted into the pipeline of the core without using the external data bus. therefore, when in debug state, a store- multiple (stm) can be inse rted into the instruction pipeline. this exports the contents of the arm9ej-s registers. this data can be serially shifted out without affecting the rest of the system. there are two scan chains inside the arm9ej -s processor which support testing, debugging, and programming of the embedded ice-rt. the scan chains are controlled by the ice/jtag port. embedded ice mode is selected when jtagsel is low. it is not possible to switch directly between ice and jtag operations. a chip reset must be performed after jtagsel is changed. for further details on the embedded in-circuit-emulator-rt, see the arm document: arm9ej-s technical reference manual ( ddi 0222a ). 12.6.3 debug unit the debug unit provides a two-pin (dxrd a nd txrd) usart that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum. the debug unit also manages the interrupt handling of the commtx and commrx signals that come from the ice and that trace the activity of the debug communication channel.the debug unit allows blockage of access to the system through the ice interface. a specific register, the debug unit chip id register, gives information about the product version and its internal configuration. the at91sam9xe debug unit chip id value is 0x0198 03a0 on 32-bit width. for further details on the debug unit, see the debug unit section.
68 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 12.6.4 ieee 1149.1 jtag boundary scan ieee 1149.1 jtag boundary scan allows pin-level access independent of the device packaging technology. ieee 1149.1 jtag boundary scan is enabled when jtagsel is high. the sample, extest and bypass functions are implemented. in ic e debug mode, the ar m processor responds with a non-jtag ch ip id that identifi es the processo r to the ice system. this is not ieee 1149.1 jtag-compliant. it is not possible to switch directly between jtag and ice operations. a chip reset must be per- formed after jtagsel is changed. a boundary-scan descriptor language (bsdl) file is provided to set up test. 12.6.4.1 jtag boundary-scan register the boundary-scan register (bsr) contains 484 bits that correspond to active pins and associ- ated control signals. each at91sam9xe input/output pin corresponds to a 3-bit register in the bsr. the output bit contains data that can be fo rced on the pad. the input bit fa cilitates the obse rvability of data applied to the pad. the control bit selects the direction of the pad. table 12-2. at91sam9xe jtag boundary scan register bit number pin name pin type associated bsr cells 307 a0 in/out control 306 input/output 305 a1 in/out control 304 input/output 303 a10 in/out control 302 input/output 301 a11 in/out control 300 input/output 299 a12 in/out control 298 input/output 297 a13 in/out control 296 input/output 295 a14 in/out control 294 input/output 293 a15 in/out control 292 input/output 291 a16 in/out control 290 input/output 289 a17 in/out control 288 input/output 287 a18 in/out control 286 input/output
69 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 285 a19 in/out control 284 input/output 283 a2 in/out control 282 input/output 281 a20 in/out control 280 input/output 279 a21 in/out control 278 input/output 277 a22 in/out control 276 input/output 275 a3 in/out control 274 input/output 273 a4 in/out control 272 input/output 271 a5 in/out control 270 input/output 269 a6 in/out control 268 input/output 267 a7 in/out control 266 input/output 265 a8 in/out control 264 input/output 263 a9 in/out control 262 input/output 261 bms input input 260 cas in/out control 259 input/output 258 d0 in/out control 257 input/output 256 d1 in/out control 255 input/output 254 d10 in/out control 253 input/output 252 d11 in/out control 251 input/output 250 d12 in/out control 249 input/output 248 d13 in/out control 247 input/output table 12-2. at91sam9xe jtag boundary scan register
70 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 246 d14 in/out control 245 input/output 244 d15 in/out control 243 input/output 242 d2 in/out control 241 input/output 240 d3 in/out control 239 input/output 238 d4 in/out control 237 input/output 236 d5 in/out control 235 input/output 234 d6 in/out control 233 input/output 232 d7 in/out control 231 input/output 230 d8 in/out control 229 input/output 228 d9 in/out control 227 input/output 226 nandoe in/out control 225 input/output 224 nandwe in/out control 223 input/output 222 ncs0 in/out control 221 input/output 220 ncs1 in/out control 219 input/output 218 nrd in/out control 217 input/output 216 nrst in/out control 215 input/output 214 nwr0 in/out control 213 input/output 212 nwr1 in/out control 211 input/output 210 nwr3 in/out control 209 input/output 208 oscsel input input table 12-2. at91sam9xe jtag boundary scan register
71 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 207 pa0 in/out control 206 input/output 205 pa1 in/out control 204 input/output 203 pa10 in/out control 202 input/output 201 pa11 in/out control 200 input/output 199 pa12 in/out control 198 input/output 197 pa13 in/out control 196 input/output 195 pa14 in/out control 194 input/output 193 pa15 in/out control 192 input/output 191 pa16 in/out control 190 input/output 189 pa17 in/out control 188 input/output 187 pa18 in/out control 186 input/output 185 pa19 in/out control 184 input/output 183 pa2 in/out control 182 input/output 181 pa20 in/out control 180 input/output 179 pa21 in/out control 178 input/output 177 pa22 in/out control 176 input/output 175 pa23 in/out control 174 input/output 173 pa24 in/out control 172 input/output 171 pa25 in/out control 170 input/output 169 pa26 in/out control 168 input/output table 12-2. at91sam9xe jtag boundary scan register
72 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 167 pa27 in/out control 166 input/output 165 pa28 in/out control 164 input/output 163 pa29 in/out control 162 input/output 161 pa3 in/out control 160 input/output 159 internal 158 internal 157 internal 156 internal 155 pa4 in/out control 154 input/output 153 pa5 in/out control 152 input/output 151 pa6 in/out control 150 input/output 149 pa7 in/out control 148 input/output 147 pa8 in/out control 146 input/output 145 pa9 in/out control 144 input/output 143 pb0 in/out control 142 input/output 141 pb1 in/out control 140 input/output 139 pb10 in/out control 138 input/output 137 pb11 in/out control 136 input/output 135 internal 134 internal 133 internal 132 internal 131 pb14 in/out control 130 input/output 129 pb15 in/out control 128 input/output table 12-2. at91sam9xe jtag boundary scan register
73 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 127 pb16 in/out control 126 input/output 125 pb17 in/out control 124 input/output 123 pb18 in/out control 122 input/output 121 pb19 in/out control 120 input/output 119 pb2 in/out control 118 input/output 117 pb20 in/out control 116 input/output 115 pb21 in/out control 114 input/output 113 pb22 in/out control 112 input/output 111 pb23 in/out control 110 input/output 109 pb24 in/out control 108 input/output 107 pb25 in/out control 106 input/output 105 pb26 in/out control 104 input/output 103 pb27 in/out control 102 input/output 101 pb28 in/out control 100 input/output 99 pb29 in/out control 98 input/output 97 pb3 in/out control 96 input/output 95 pb30 in/out control 94 input/output 93 pb31 in/out control 92 input/output 91 pb4 in/out control 90 input/output 89 pb5 in/out control 88 input/output table 12-2. at91sam9xe jtag boundary scan register
74 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 87 pb6 in/out control 86 input/output 85 pb7 in/out control 84 input/output 83 pb8 in/out control 82 input/output 81 pb9 in/out control 80 input/output 79 pc0 in/out control 78 input/output 77 pc1 in/out control 76 input/output 75 pc10 in/out control 74 input/output 73 pc11 in/out control 72 input/output 71 internal 70 internal 69 pc13 in/out control 68 input/output 67 pc14 in/out control 66 input/output 65 pc15 in/out control 64 input/output 63 pc16 in/out control 62 input/output 61 pc17 in/out control 60 input/output 59 pc18 in/out control 58 input/output 57 pc19 in/out control 56 input/output 55 internal 54 internal 53 pc20 in/out control 52 input/output 51 pc21 in/out control 50 input/output 49 pc22 in/out control 48 input/output table 12-2. at91sam9xe jtag boundary scan register
75 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 47 pc23 in/out control 46 input/output 45 pc24 in/out control 44 input/output 43 pc25 in/out control 42 input/output 41 pc26 in/out control 40 input/output 39 pc27 in/out control 38 input/output 37 pc28 in/out control 36 input/output 35 pc29 in/out control 34 input/output 33 internal 32 internal 31 pc30 in/out control 30 input/output 29 pc31 in/out control 28 input/output 27 pc4 in/out control 26 input/output 25 pc5 in/out control 24 input/output 23 pc6 in/out control 22 input/output 21 pc7 in/out control 20 input/output 19 pc8 in/out control 18 input/output 17 pc9 in/out control 16 input/output 15 ras in/out control 14 input/output 13 rtck out control 12 output 11 sda10 in/out control 10 input/output 09 sdck in/out control 08 input/output table 12-2. at91sam9xe jtag boundary scan register
76 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 12.6.5 jid code register access: read-only ? version[31:28]: product version number set to 0x0. ? part number[27:12]: product part number product part number is 0x5b13 ? manufacturer identity[11:1] set to 0x01f. bit[0] required by ieee std. 1149.1. set to 0x1. jtag id code value is 0x05b1_303f. 07 sdcke in/out control 06 input/output 05 sdwe in/out control 04 input/output 03 shdn out control 02 output 01 tst input input 00 wkup input input table 12-2. at91sam9xe jtag boundary scan register 31 30 29 28 27 26 25 24 version part number 23 22 21 20 19 18 17 16 part number 15 14 13 12 11 10 9 8 part number manufacturer identity 76543210 manufacturer identity 1
77 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 13. at91sam9xe boot program 13.1 overview the boot program integrates different programs permitting download and/or upload into the dif- ferent memories of the product. first, it initializes the debug unit serial port (dbgu) and the usb device port. sam-ba boot is then executed. it waits for transactions either on the usb device, or on the dbgu serial port. 13.2 flow diagram the boot program implements the algorithm in figure 13-1 . figure 13-1. boot program algorithm flow diagram large crystal table sam-ba boot internal rc oscillator yes no main oscillator bypass yes start reduced crystal table no input frequency table character(s) received on dbgu ? run sam-ba boot run sam-ba boot usb enumeration successful ? yes yes no no
78 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 13.3 device initialization initialization follows the steps described below: 1. fiq initialization 2. stack setup for arm supervisor mode 3. external clock detection 4. switch master clock on main oscillator 5. c variable initialization 6. main oscillator frequ ency detection if no external clock detected 7. pll setup: pllb is initialized to generate a 48 mhz clock necessary to use the usb device. a register located in the power management controller (pmc) determines the frequency of the main o scillator and thus the corr ect factor for the pllb. a. if internal rc oscillator is used (osc sel = 0) and main oscillator is active, table 13-1 defines the crystals supported by the boot program when using the internal rc oscillator. note: any other crystal can be used but it prevents using the usb. b. if internal rc oscillator is used (osc sel = 0) and main oscillator is bypassed, table 13-2 defines the frequencies supported by the boot program when bypass- ing main oscillator. note: any other input frequency can be used but it prevents using the usb. c. if an external 32768 hz oscillator is used (oscsel = 1) (oscsel = 1 and bypass mode), table 13-3 defines the crystals supported by the boot program. note: booting on usb or on dbgu is possible with any of these crystals. table 13-1. reduced crystal table (mhz) oscsel = 0 3.0 6.0 18.432 other boot on dbgu yes yes yes yes boot on usb yes yes yes no table 13-2. input frequencies supported by software auto-detection (mhz) oscsel = 0 1.0 2.0 6.0 12.0 25.0 50.0 other boot on dbgu yes yes yes yes yes yes yes boot on usb yes yes yes yes yes yes no table 13-3. large crystal table (mhz) oscsel = 1 3.0 3.2768 3.6864 3.84 4.0 4.433619 4.9152 5.0 5.24288 6.0 6.144 6.4 6.5536 7.159090 7.3728 7.864320 8.0 9.8304 10.0 11.05920 12.0 12.288 13.56 14.31818 14.7456 16.0 16.367667 17.734470 18.432 20.0
79 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 8. initialization of the dbgu serial port (115200 bauds, 8, n, 1) only if oscsel = 1 9. enable the user reset 10. jump to sam-ba boot sequence 11. disable the watchdog 12. initialization of the usb device port figure 13-2. clocks and dbgu configurations end end scan large crystal table (table 15.3 &15.4) yes start internal rc oscillator? (oscsel = 0) no mck = pllb/2 udpck = pllb/2 "romboot>" displayed on dbgu mck = mosc udpck = pllb/2 dbgu not configured yes (dbgu) autobaudrate ? no (usb) mck = mosc udpck = pllb/2 dbgu not configured mck = pllb udpck = xxxx dbgu configured end scan reduced table (table 15.1 &15.2) no
80 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 13.4 sam-ba boot the sam-ba boot principle is to: ? wait for usb device enumeration. ? in parallel, wait for characte r(s) received on the dbgu if mck is configured to 48 mhz (oscsel = 1). ? if not, the autobaudrate sequence is executed in parallel (see figure 13-3 ). figure 13-3. autobaudrate flow diagram ? once the communication interface is identified, the application runs in an infinite loop waiting for different commands as in table 13-4 . device setup character '0x80' received ? no ye s character '0x80' received ? no ye s character '#' received ? ye s run sam-ba boot send character '>' no 1st measurement 2nd measurement test communication uart operational
81 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? write commands: write a byte ( o ), a halfword ( h ) or a word ( w ) to the target. ? address : address in hexadecimal. ? value : byte, halfword or word to write in hexadecimal. ? output : ?>?. ? read commands: read a byte ( o ), a halfword ( h ) or a word ( w ) from the target. ? address : address in hexadecimal ? output : the byte, halfword or word read in hexadecimal following by ?>? ? send a file ( s ): send a file to a specified address ? address : address in hexadecimal ? output : ?>?. note: there is a time-out on this command which is reached when the prompt ?>? appears before the end of the command execution. ? receive a file ( r ): receive data into a file from a specified address ? address : address in hexadecimal ? nbofbytes : number of bytes in hexadecimal to receive ? output : ?>? ?go ( g ): jump to a specified address and execute the code ? address : address to jump in hexadecimal ? output : ?>? ? get version ( v ): return the sam-ba boot version ? output : ?>? table 13-4. commands available through the sam-ba boot command action argument(s) example o write a byte address, value# o 200001,ca# o read a byte address,# o 200001,# h write a half word address, value# h 200002,cafe# h read a half word address,# h 200002,# w write a word address, value# w 200000,cafedeca# w read a word address,# w 200000,# s send a file address,# s 200000,# r receive a file address, nbofbytes# r 200000,1234# g go address# g 200200# v display version no argument v #
82 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 13.4.1 dbgu serial port communication is performed through the dbgu serial port initialized to 115200 baud, 8, n, 1. the send and receive file commands use the xmodem protocol to communicate. any terminal performing this protocol can be used to send th e application file to the target. the size of the binary file to send depends on the sram size embedded in the product. in all cases, the size of the binary file must be lower than the sram si ze because the xmodem protocol requires some sram memory to work. 13.4.2 xmodem protocol the xmodem protocol supported is the 128-byte l ength block. this protocol uses a two-charac- ter crc-16 to guarantee detection of a maximum bit error. xmodem protocol with crc is accurate provided both sender and receiver report successful transmission. each block of the transfer looks like: <255-blk #><--128 da ta bytes--> in which: ? = 01 hex ? = binary number, starts at 01, increments by 1, and wraps 0ffh to 00h (not to 01) ? <255-blk #> = 1?s complement of the blk#. ? = 2 bytes crc16 figure 13-4 shows a transmission using this protocol. figure 13-4. xmodem transfer example 13.4.3 usb device port a 48 mhz usb clock is necessary to use the usb device port. it has been programmed earlier in the device initia lization procedure with pllb configuration. the device uses the usb communication device class (cdc) drivers to take advantage of the installed pc rs-232 software to talk over the usb. the cdc class is implemented in all releases of windows ? , from windows 98se to windows xp. the cdc document, available at host device soh 01 fe data[128] crc crc c ack soh 02 fd data[128] crc crc ack soh 03 fc data[100] crc crc ack eot ack
83 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary www.usb.org, describes a way to implement devices such as isdn modems and virtual com ports. the vendor id is atmel?s vendor id 0x03eb. the product id is 0x6124. these references are used by the host operating system to mount the correct driver. on windows systems, the inf files contain the correspondence between vendor id and product id. atmel provides an inf example to see the device as a new serial port and also provides another custom driver used by the sam-ba application: atm6124.sys. 13.4.3.1 enumeration process the usb protocol is a master/slave protocol. th is is the host that starts the enumeration send- ing requests to the device through the control endpoint. the device handles standard requests as defined in the usb specification. the device also handles some class requests defined in the cdc class. unhandled requests are stalled. 13.4.3.2 communication endpoints there are two communication endpoints and endpoint 0 is used for the enumeration process. endpoint 1 is a 64-byte bulk out endpoint and endpoint 2 is a 64-byte bulk in endpoint. sam- ba boot commands are sent by the host through the endpoint 1. if required, the message is split by the host into several data payloads by the host driver. if the command requires a response, the host can send in transactions to pick up the response. table 13-5. handled standard requests request definition get_descriptor returns the current device configuration value. set_address sets the device address for all future device access. set_configuration sets the device configuration. get_configuration returns the curr ent device configuration value. get_status returns status for the specified recipient. set_feature used to set or enable a specific feature. clear_feature used to clear or disable a specific feature. table 13-6. handled class requests request definition set_line_coding configures dte rate, stop bits, parity and number of character bits. get_line_coding requests current dte rate, stop bits, parity and number of character bits. set_control_line_state rs-232 signal used to tell the dce device the dte device is now present.
84 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 13.4.4 in-application programming (iap) feature the iap feature is a function located in rom that can be called by any software application. when called, this function sends the desired flash command to the eefc and waits for the flash to be ready (looping while the frdy bit is not set in the mc_fsr register). since this function is executed from rom, this allows flash programming (like sector write) to be done by code running in flash. the iap function entry point is retrieved by reading the swi vector in rom (0x100008). this funtion takes one argument in parameter: the command to be sent to the eefc. this function returns the value of the mc_fsr register. iap software code example: (unsigned int) (*iap_function)(unsigned long); void main (void) { unsigned long flashsectornum = 200; unsigned long flash_cmd = 0; unsigned long flash_status = 0; /* initialize the function pointer (retrieve function address from swi vector) */ iap_function = ((unsigned long) (*)(unsigned long)) 0x100008; /* send your data to the sector */ /* build the command to send to efc */ flash_cmd = (0x5a << 24) | (flashsectornum << 8) | at91c_mc_fcmd_ewp; /* call the iap function with appropriate command */ flash_status = iap_function (flash_cmd); }
85 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 13.5 hardware and software constraints ? usb requirements: ? crystal or input frequencies supported by software auto-detection. see table 13-1 , table 13-2 and table 13-3 on page 78 for more informations. table 13-7 contains a list of pins that are driven during the boot program execution. these pins are driven during the boot sequence. table 13-7. pins driven during boot program execution peripheral pin pio line dbgu drxd piob14 dbgu dtxd piob15
86 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary
87 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 14. fast flash programming interface (ffpi) 14.1 description the fast flash programming interface provides tw o solutions - parallel or serial - for high-vol- ume programming using a standard gang programmer. the parallel interface is fully handshaked and the device is considered to be a standard eeprom. additionally, the parallel protocol offers an optimized access to all t he embedded flash functionalities. the serial inter- face uses the standard ieee 1149.1 jtag protocol. it offers an optimized access to all the embedded flash functionalities. although the fast flash programming mode is a dedicated mode for high volume programming, this mode not designed for in-situ programming. 14.2 parallel fast flash programming 14.2.1 device configuration in fast flash programming mode, the device is in a specific test mode. only a certain set of pins is significant. other pins must be left unconnected. figure 14-1. parallel programming interface ncmd pgmncmd rdy pgmrdy noe pgmnoe nvalid pgmnvalid mode[3:0] pgmm[3:0] data[15:0] pgmd[15:0] xin tst vddio pgmen0 pgmen1 0 - 50mhz vddio vddcore vddio vddpll vddflash gnd gnd vddio pgmen2 table 14-1. signal description list signal name function type active level comments power vddflash flash power supply power vddio i/o lines power supply power vddcore core power supply power vddpll pll power supply power gnd ground ground
88 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 14.2.2 signal names depending on the mode settings, data is latched in different internal registers. when mode is equal to cmde, then a new command (strobed on data[15:0] signals) is stored in the command register. clocks xin main clock input. this input can be tied to gnd. in this case, the device is clocked by the internal rc oscillator. input 32khz to 50mhz test tst test mode select input high must be connected to vddio pgmen0 test mode select input high must be connected to vddio pgmen1 test mode select input high must be connected to vddio pgmen2 test mode select input low must be connected to gnd pio pgmncmd valid command available input low pulled-up input at reset pgmrdy 0: device is busy 1: device is ready for a new command output high pulled-up input at reset pgmnoe output enable (active high) input low pulled-up input at reset pgmnvalid 0: data[15:0] is in input mode 1: data[15:0] is in output mode output low pulled-up input at reset pgmm[3:0] specifies data type (see table 14-2 ) input pulled-up input at reset pgmd[15:0] bi-directional data bus input/output pulled-up input at reset table 14-1. signal description list (continued) signal name function type active level comments table 14-2. mode coding mode[3:0] symbol data 0000 cmde command register 0001 addr0 address register lsbs 0010 addr1 0011 addr2 0100 addr3 address register msbs 0101 data data register default idle no register
89 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 14.2.3 entering programming mode the following algorithm puts the devi ce in parallel programming mode: ? apply gnd, vddio, vddcore, vddflash and vddpll. ? apply xin clock within t por_reset if an external clock is available. ?wait for t por_reset ? start a read or write handshaking. note: after reset, the device is clocked by the internal rc oscillator. before clearing rdy signal, if an external clock ( > 32 khz) is connected to xin, then the device switches on the external clock. else, xin input is not considered. a highe r frequency on xin speeds up the programmer handshake. 14.2.4 programmer handshaking an handshake is defined for read and write operations. when the device is ready to start a new operation (rdy signal set), the programmer star ts the handshake by clearing the ncmd signal. the handshaking is achieved once nc md signal is high and rdy is high. 14.2.4.1 write handshaking for details on the write handshaking sequence, refer to figure 14-2 and table 14-4 . table 14-3. command bit coding data[15:0] symbol command executed 0x0011 read read flash 0x0012 wp write page flash 0x0022 wpl write page and lock flash 0x0032 ewp erase page and write page 0x0042 ewpl erase page and write page then lock 0x0013 ea erase all 0x0014 slb set lock bit 0x0024 clb clear lock bit 0x0015 glb get lock bit 0x0034 sgpb set general purpose nvm bit 0x0044 cgpb clear general purpose nvm bit 0x0025 ggpb get general purpose nvm bit 0x0054 sse set security bit 0x0035 gse get security bit 0x001f wram write memory 0x001e gve get version
90 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 14-2. parallel programming timing, write sequence 14.2.4.2 read handshaking for details on the read handshaking sequence, refer to figure 14-3 and table 14-5 . figure 14-3. parallel programming timing, read sequence ncmd rdy noe nvalid data[15:0] mode[3:0] 1 2 3 4 5 table 14-4. write handshake step programmer action device action data i/o 1 sets mode and data signals waits for ncmd low input 2 clears ncmd signal latches mode and data input 3 waits for rdy low clears rdy signal input 4 releases mode and data signals executes command and polls ncmd high input 5 sets ncmd signal executes command and polls ncmd high input 6 waits for rdy high sets rdy input ncmd rdy noe nvalid data[15:0] mode[3:0] 1 2 3 4 5 6 7 9 8 addr adress in z data out 10 11 xin 12 13
91 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 14.2.5 device operations several commands on the flash memory are available. these commands are summarized in table 14-3 on page 89 . each command is driven by the programmer through the parallel inter- face running several read/write handshaking sequences. when a new command is executed, the previous one is automatically achieved. thus, chaining a read command after a write automatically flushes the load buffer in the flash. 14.2.5.1 flash read command this command is used to read the contents of the flash memory. the read command can start at any valid address in the memory plane and is optimized for consecutive reads. read hand- shaking can be chained; an internal address buffer is automatically increased. table 14-5. read handshake step programmer action device action data i/o 1 sets mode and data signals waits for ncmd low input 2 clears ncmd signal latch mode and data input 3 waits for rdy low clears rdy signal input 4 sets data signal in tristate waits for noe low input 5 clears noe signal tristate 6 waits for nvalid low sets data bus in output mode and outputs the flash contents. output 7 clears nvalid signal output 8 reads value on data bus waits for noe high output 9 sets noe signal output 10 waits for nvalid high sets data bus in input mode x 11 sets data in output mode sets nvalid signal input 12 sets ncmd signal waits for ncmd high input 13 waits for rdy high sets rdy signal input table 14-6. read command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde read 2 write handshaking addr0 memory address lsb 3 write handshaking addr1 memory address 4 read handshaking data *memory address++ 5 read handshaking data *memory address++ ... ... ... ... n write handshaking addr0 memory address lsb n+1 write handshaking addr1 memory address
92 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 14.2.5.2 flash write command this command is used to write the flash contents. the flash memory plane is organized into several pages. data to be written are stored in a load buffer that corresponds to a flash memory page. the load buffer is automatically flushed to the flash: ? before access to any page other than the current one ? when a new command is validated (mode = cmde) the write page command (wp) is optimized for consecutive writes. write handshaking can be chained; an internal address buffer is automatically increased. the flash command write page and lock (wpl) is equivalent to the flash write command. however, the lock bit is automatically set at the end of the flash write operation. as a lock region is composed of several pages, the programmer writes to the first pages of the lock region using flash write commands and writes to the last page of the lock region using a flash write and lock command. the flash command erase page and write (ewp) is equivalent to the flash write command. however, before programming the load buffer, the page is erased. the flash command erase page and write the lock (ewpl) combines ewp and wpl commands. 14.2.5.3 flash full erase command this command is used to erase the flash memory planes. n+2 read handshaking data *memory address++ n+3 read handshaking data *memory address++ ... ... ... ... table 14-6. read command step handshake sequence mode[3:0] data[15:0] table 14-8. write command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde wp or wpl or ewp or ewpl 2 write handshaking addr0 memory address lsb 3 write handshaking addr1 memory address 4 write handshaking data *memory address++ 5 write handshaking data *memory address++ ... ... ... ... n write handshaking addr0 memory address lsb n+1 write handshaking addr1 memory address n+2 write handshaking data *memory address++ n+3 write handshaking data *memory address++ ... ... ... ...
93 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary all lock regions must be unlocked before the full erase command by using the clb command. otherwise, the erase command is aborted and no page is erased. 14.2.5.4 flash lock commands lock bits can be set using wpl or ewpl co mmands. they can also be set by using the set lock command (slb) . with this command, several lock bits can be activated. a bit mask is pro- vided as argument to the command. when bit 0 of the bit mask is set, then the first lock bit is activated. in the same way, the clear lock command (clb) is used to clear lock bits. all the lock bits are also cleared by the ea command. lock bits can be read using get lock bit command (glb) . the n th lock bit is active when the bit n of the bit mask is set.. 14.2.5.5 flash general-purpose nvm commands general-purpose nvm bits (gp nvm bits) can be set using the set gpnvm command (sgpb) . this command also activates gp nvm bits. a bit mask is provided as argument to the com- mand. when bit 0 of the bit mask is set, then the first gp nvm bit is activated. in the same way, the clear gpnvm command (cgpb) is used to clear general-purpose nvm bits. all the general-purpose nvm bits are also cleared by the ea command. the general-pur- pose nvm bit is deactivated when the correspo nding bit in the pattern value is set to 1. table 14-9. full erase command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde ea 2 write handshaking data 0 table 14-10. set and clear lock bit command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde slb or clb 2 write handshaking data bit mask table 14-11. get lock bit command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde glb 2 read handshaking data lock bit mask status 0 = lock bit is cleared 1 = lock bit is set table 14-12. set/clear gp nvm command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde sgpb or cgpb 2 write handshaking data gp nvm bit pattern value
94 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary general-purpose nvm bits can be read using the get gpnvm bit command (ggpb) . the n th gp nvm bit is active when bit n of the bit mask is set.. 14.2.5.6 flash security bit command a security bit can be set using the set security bit command (sse). once the security bit is active, the fast flash programming is disabled. no other command can be run. an event on the erase pin can erase the security bit once th e contents of the flash have been erased. once the security bit is set, it is not possible to access ffpi. the only way to erase the security bit is to erase the flash. in order to erase the flash, the user must perform the following: ? power-off the chip ? power-on the chip with tst = 0 ? assert erase during a period of more than 220 ms ? power-off the chip then it is possible to return to ffpi mode and check that flash is erased. 14.2.5.7 memory write command this command is used to perform a write access to any memory location. the memory write command (wram) is optimized for consecutive writes. write handshaking can be chained; an internal address buffer is automatically increased. table 14-13. get gp nvm bit command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde ggpb 2 read handshaking data gp nvm bit mask status 0 = gp nvm bit is cleared 1 = gp nvm bit is set table 14-14. set security bit command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde sse 2 write handshaking data 0 table 14-15. write command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde wram 2 write handshaking addr0 memory address lsb 3 write handshaking addr1 memory address 4 write handshaking data *memory address++ 5 write handshaking data *memory address++ ... ... ... ... n write handshaking addr0 memory address lsb
95 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 14.2.5.8 get version command the get version (gve) command retrieves the version of the ffpi interface. n+1 write handshaking addr1 memory address n+2 write handshaking data *memory address++ n+3 write handshaking data *memory address++ ... ... ... ... table 14-15. write command (continued) step handshake sequence mode[3:0] data[15:0] table 14-16. get version command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde gve 2 write handshaking data version
96 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 14.3 serial fast flash programming the serial fast flash programming interface is based on ieee std. 1149.1 ?standard test access port and boundary-scan architecture?. refe r to this standard for an explanation of terms used in this chapter and for a description of the tap controller states. in this mode, data read/written from/to the embedded flash of the device are transmitted through the jtag interface of the device. 14.3.1 device configuration in serial fast flash programming mode, the device is in a specific test mode. only a distinct set of pins is significant. other pins must be left unconnected. figure 14-4. serial programming tdi tdo tms tck xin tst vddio pgmen0 pgmen1 0-50mhz vddio vddcore vddio vddpll vddflash gnd vddio gnd pgmen2 table 14-17. signal description list signal name function type active level comments power vddflash flash power supply power vddio i/o lines power supply power vddcore core power supply power vddpll pll power supply power gnd ground ground clocks xin main clock input. this input can be tied to gnd. in this case, the device is clocked by the internal rc oscillator. input 32 khz to 50 mhz
97 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 14.3.2 entering serial programming mode the following algorithm puts the device in serial programming mode: ? apply gnd, vddio, vddcore, vddflash and vddpll. ? apply xin clock within t por_reset + 32(t sclk ) if an external clock is available. ?wait for t por_reset . ? reset the tap controller clocking 5 tck pulses with tms set. ? shift 0x2 into the ir register (ir is 4 bits long, lsb first) without going through the run-test- idle state. ? shift 0x2 into the dr register (dr is 4 bits long, lsb first) without going through the run- test-idle state. ? shift 0xc into the ir register (ir is 4 bits long, lsb first) without going through the run-test- idle state. note: after reset, the device is clocked by the internal rc oscillator. before clearing rdy signal, if an external clock ( > 32 khz) is connected to xin, t hen the device will switch on the external clock. else, xin input is not considered. an high er frequency on xin speeds up the programmer handshake. test tst test mode select input high must be connected to vddio. pgmen0 test mode select input high must be connected to vddio pgmen1 test mode select input high must be connected to vddio pgmen2 test mode select input low must be connected to gnd jtag tck jtag tck input - pulled-up input at reset tdi jtag test data in input - pulled-up input at reset tdo jtag test data out output - tms jtag test mode select input - pulled-up input at reset table 14-17. signal description list (continued) signal name function type active level comments table 14-18. reset tap controller and go to select-dr-scan tdi tms tap controller state x1 x1 x1 x1 x 1 test-logic reset x 0 run-test/idle xt 1 select-dr-scan
98 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 14.3.3 read/write handshake the read/write handshake is done by carrying out read/write operations on two registers of the device that are accessible through the jtag: ? debug comms control register: dccr ? debug comms data register: dcdr access to these registers is done through the ta p 38-bit dr register comprising a 32-bit data field, a 5-bit address field and a read/write bit. the data to be written is scanned into the 32-bit data field with the address of the register to the 5-bit address field and 1 to the read/write bit. a register is read by scanning its address into th e address field and 0 into the read/write bit, going through the update-dr tap state, then scanning out the data. refer to the arm7tdmi reference manuel for more information on comm channel operations. figure 14-5. tap 8-bit dr register a read or write takes place when the tap controller enters update-dr state. refer to the ieee 1149.1 for more details on jtag operations. ? the address of the debug comms control register is 0x04. ? the address of the debug comms data register is 0x05. the debug comms control register is read-only and allows synchronized handshaking between the processor and the debugger. ? bit 1 (w): denotes whether the programmer can read a data through the debug comms data register. if the device is busy w = 0, then the programmer must poll until w = 1. ? bit 0 (r): denotes whether the programmer can send data from the debug comms data register. if r = 1, data previously placed there through the scan chain has not been collected by the device and so the programmer must wait. the write handshake is done by polling the debug comms control register until the r bit is cleared. once cleared, data can be written to the debug comms data register. the read handshake is do ne by polling the debug co mms control register until the w bit is set. once set, data can be read in the debug comms data register. 14.3.4 device operations several commands on the flash memory are available. these commands are summarized in table 14-3 on page 89 . commands are run by the programmer through the serial interface that is reading and writing the debug comms registers. tdi tdo 4 0 r/w address 31 data 0 address decoder debug comms control register debug comms data register 32 5
99 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 14.3.4.1 flash read command this command is used to read the flash content s. the memory map is accessible through this command. memory is seen as an array of words (32-bit wide). the read command can start at any valid address in the memory plane. this address must be word-aligned . the address is automatically incremented. 14.3.4.2 flash write command this command is used to write the flash contents. the address transmitted must be a valid flash address in the memory plane. the flash memory plane is organized into several pages. data to be written is stored in a load buffer that corresponds to a flash memory page. the load buffer is automatically flushed to the flash: ? before access to any page than the current one ? at the end of the number of words transmitted the write page command (wp) is optimized for consecutive wr ites. write handshaking can be chained; an internal address buffer is automatically increased. flash write page and lock command (wpl) is equivalent to the flash write command. how- ever, the lock bit is automatically set at the end of the flash write operation. as a lock region is composed of several pages, the programmer writes to the first pages of the lock region using flash write commands and writes to the last page of the lock region using a flash write and lock command. flash erase page and write command (ewp) is equivalent to the flash write command. how- ever, before programming the load buffer, the page is erased. flash erase page and write the lock command (ewpl) combines ewp and wpl commands. table 14-19. read command read/write dr data write (number of words to read) << 16 | read write address read memory [address] read memory [address+4] ... ... read memory [address+(number of words to read - 1)* 4] table 14-20. write command read/write dr data write (number of words to write) << 16 | (wp or wpl or ewp or ewpl) write address write memory [address] write memory [address+4] write memory [address+8] write memory [address+(number of words to write - 1)* 4]
100 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 14.3.4.3 flash full erase command this command is used to erase the flash memory planes. all lock bits must be deactivated before using the full erase command. this can be done by using the clb command. 14.3.4.4 flash lock commands lock bits can be set using wpl or ewpl co mmands. they can also be set by using the set lock command (slb) . with this command, several lock bits can be activated at the same time. bit 0 of bit mask corresponds to the first lock bit and so on. in the same way, the clear lock command (clb) is used to clear lock bits. all the lock bits can also be cleared by the ea command. lock bits can be read using get lock bit command (glb) . when a bit set in the bit mask is returned, then the corresponding lock bit is active. 14.3.4.5 flash general-purpose nvm commands general-purpose nvm bits (gp nvm) can be set with the set gpnvm command (sgpb) . using this command, several gp nvm bits can be activated at the same time. bit 0 of bit mask corre- sponds to the first gpnvm bit and so on. in the same way, the clear gpnvm command (cgpb) is used to clear gp nvm bits. all the general-purpose nvm bits are also cleared by the ea command. table 14-21. full erase command read/write dr data write ea table 14-22. set and clear lock bit command read/write dr data write slb or clb write bit mask table 14-23. get lock bit command read/write dr data write glb read bit mask table 14-24. set and clear general-purpose nvm bit command read/write dr data write sgpb or cgpb write bit mask
101 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary gp nvm bits can be read using get gpnvm bit command (ggpb) . when a bit set in the bit mask is returned, then the corresponding gpnvm bit is set. 14.3.4.6 flash security bit command security bits can be set using set security bit command (sse). once the security bit is active, the fast flash programming is disabled. no othe r command can be run. only an event on the erase pin can erase the security bit once th e contents of the flash have been erased. once the security bit is set, it is not possible to access ffpi. the only way to erase the security bit is to erase the flash. in order to erase the flash, the user must perform the following: ? power-off the chip ? power-on the chip with tst = 0 ? assert erase during a period of more than 220 ms ? power-off the chip then it is possible to return to ffpi mode and check that flash is erased. 14.3.4.7 memory write command this command is used to perform a write access to any memory location. the memory write command (wram) is optimized for consecutive writes. an internal address buffer is automatically increased. table 14-25. get general-purpose nvm bit command read/write dr data write ggpb read bit mask table 14-26. set security bit command read/write dr data write sse table 14-27. write command read/write dr data write (number of words to write) << 16 | (wram) write address write memory [address] write memory [address+4] write memory [address+8] write memory [address+(number of words to write - 1)* 4]
102 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 14.3.4.8 get version command the get version (gve) command retrieves the version of the ffpi interface. table 14-28. get version command read/write dr data write gve read version
103 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 15. reset controller (rstc) 15.1 description the reset controller (rstc), based on power-on reset cells, handles all the resets of the sys- tem without any external components. it reports which reset occurred last. the reset controller also drives independently or simultaneously the external reset and the peripheral and processor resets. a brownout detection is also available to preven t the processor from falling into an unpredictable state. 15.2 block diagram figure 15-1. reset controller block diagram 15.3 functional description 15.3.1 reset controller overview the reset controller is made up of an nrst manager, a brownout manager, a startup counter and a reset state manager. it runs at slow clock and generates the following reset signals: ? proc_nreset: processor reset line. it also resets the watchdog timer. ? backup_nreset: affects all the peripherals powered by vddbu. ? periph_nreset: affects the whole set of embedded peripherals. ? nrst_out: drives the nrst pin. nrst startup counter proc_nreset wd_fault periph_nreset backup_neset slck reset state manager reset controller rstc_irq nrst manager exter_nreset nrst_out backup supply por main supply por wdrproc user_reset brown_out bod_rst_en brownout manager bod_reset
104 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary these reset signals are asserted by the reset cont roller, either on external events or on soft- ware action. the reset state manager controls the generation of reset signals and provides a signal to the nrst manager when an assertion of the nrst pin is required. the nrst manager shapes the nrst assertion du ring a programmable ti me, thus controlling external device resets. the startup counter waits for the complete crystal oscillator startu p. the wait de lay is given by the crystal oscillator startup time maximum value that can be foun d in the section crystal oscil- lator characteristics in the electrical characteristics section of the product documentation. the reset controller mode register (rstc_mr), allowing the configuration of the reset con- troller, is powered with vddbu, so that its configuration is saved as long as vddbu is on. 15.3.2 nrst manager the nrst manager samples the nrst input pin and drives this pin low when required by the reset state manager. figure 15-2 shows the block diagram of the nrst manager. figure 15-2. nrst manager 15.3.2.1 nrst signal or interrupt the nrst manager samples the nrst pin at slow clock speed. when the line is detected low, a user reset is reported to the reset state manager. however, the nrst manager can be programmed to not trigger a reset when an assertion of nrst occurs. writing the bit ursten at 0 in rstc_mr disables the user reset trigger. the level of the pin nrst can be read at any ti me in the bit nrstl (nrst level) in rstc_sr. as soon as the pin nrst is asserted, the bit ur sts in rstc_sr is set. this bit clears only when rstc_sr is read. the reset controller can also be programmed to generate an interrupt instead of generating a reset. to do so, the bit urstien in rstc_mr must be written at 1. 15.3.2.2 nrst external reset control the reset state manager asserts the signal ext_nreset to assert the nrst pin. when this occurs, the ?nrst_out? signal is driven low by the nrst manager for a time programmed by the field erstl in rstc_mr. this assertion duration, named externa l_reset_length, lasts external reset timer ursts ursten erstl exter_nreset urstien rstc_mr rstc_mr rstc_mr rstc_sr nrstl nrst_out nrst rstc_irq other interrupt sources user_reset
105 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 2 (erstl+1) slow clock cycles. this gives the approximate duration of an assertion between 60 s and 2 seconds. note that erstl at 0 defines a two-cycle duration for the nrst pulse. this feature allows the reset controller to shape the nrst pin level, and thus to guarantee that the nrst line is driven low for a time compliant with potential external devices connected on the system reset. as the field is within rstc_mr, which is backed -up, this field can be used to shape the system power-up reset for devi ces requiring a longer startup time than the slow clock oscillator. 15.3.3 brownout manager brownout detection prevents the processor from falling into an unpredictable state if the power supply drops below a certain level. when vddcore drops below the brownout threshold, the brownout manager requests a brownout re set by asserting the bod_reset signal. the programmer can disable the brownout reset by setting low the bod_rst_en input signal, i.e., by locking the corresponding general-purpose nvm bit in the flash. when the brownout reset is disabled, no reset is performed. instead, the brownout detection is reported in the bit bodsts of rstc_sr. bodsts is set and clears only when rstc_sr is read. the bit bodsts can trigger an interrupt if the bit bodien is set in the rstc_mr. at factory, the brownout reset is disabled. figure 15-3. brownout manager 15.3.4 reset states the reset state manager handles the different reset sources and generates the internal reset signals. it reports the reset status in the field rsttyp of the status register (rstc_sr). the update of the field rsttyp is performed when the processor reset is released. 15.3.4.1 general reset a general reset occurs when vddbu and vddcore are powered on. the backup supply por cell output rises and is filtered with a startup counter, which operates at slow clock. the pur- pose of this counter is to make sure the slow clock oscillator is stable before starting up the device. the length of startup ti me is hardcoded to comply with the slow clock oscillator startup time. after this time, the processor clock is released at slow clock and all the other signals remain valid for 3 cycles for proper processor and logic reset. then, all the reset signals are released and the field rsttyp in rstc_sr reports a general reset. as the rstc_mr is reset, the nrst line rises 2 cycles after the backup_nreset, as erstl defaults at value 0x0. rstc_irq brown_out bod_reset bod_rst_en bodien rstc_mr bodsts rstc_sr other interrupt sources
106 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary when vddbu is detected low by the backup suppl y por cell, all resets signals are immedi- ately asserted, even if the main supply por cell does not report a main supply shutdown. vddbu only activates the backup_nreset signal. the backup_nreset must be released so that any other reset can be generated by vddcore (main supply por output). figure 15-4 shows how the general reset affects the reset signals. figure 15-4. general reset state slck periph_nreset proc_nreset backup supply por output nrst (nrst_out) external reset length = 2 cycles startup time mck processor startup = 3 cycles backup_nreset any freq. rsttyp xxx 0x0 = general reset xxx main supply por output bms sampling
107 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 15.3.4.2 wake-up reset the wake-up reset occurs when the main supply is down. when the main supply por output is active, all the reset signals are asserted except backup_nreset. when the main supply pow- ers up, the por output is resynchronized on slow clock. the processor clock is then re-enabled during 3 slow clock cycles, depending on the requirements of the arm processor. at the end of this delay, the processor and other reset signals rise. the field rsttyp in rstc_sr is updated to report a wake-up reset. the ?nrst_out? remains asserted for ext ernal_reset_length cycles. as rstc_mr is backed-up, the programmed number of cycles is applicable. when the main supply is detected falling, the re set signals are immediately asserted. this tran- sition is synchronous with the output of the main supply por. figure 15-5. wake-up state 15.3.4.3 user reset the user reset is entered when a low level is detected on the nrst pin and the bit ursten in rstc_mr is at 1. the nrst inpu t signal is resynchronized with slck to insure proper behav- ior of the system. the user reset is entered as soon as a low level is detected on nrst. the processor reset and the peripheral reset are asserted. the user reset is left when nrst rises, after a two-cycle resynchronization time and a 3-cycle processor startup. the processor clock is re-enabled as soon as nrst is confirmed high. slck periph_nreset proc_nreset main supply por output nrst (nrst_out) external reset length = 4 cycles (erstl = 1) mck processor startup = 3 cycles backup_nreset any freq. resynch. 2 cycles rsttyp xxx 0x1 = wakeup reset xxx
108 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary when the processor reset signal is released, the rsttyp field of the status register (rstc_sr) is loaded with the value 0x4, indicating a user reset. the nrst manager guarantees that the nrst line is asserted for external_reset_length slow clock cycles, as programmed in the field erstl. how- ever, if nrst does not rise after extern al_reset_length because it is driven low externally, the internal reset lines remain asserted until nrst actually rises. figure 15-6. user reset state 15.3.4.4 brownout reset when the brown_out/bod_reset signal is asserted, the reset state manager immediately enters the brownout reset. in this state, the processo r, the peripheral and the external reset lines are asserted. the brownout reset is left 3 slow clock cycles after the rising edge of brown_out/bod_reset after a two-cycle resynchronization. an external reset is also triggered. when the processor reset is released, the field rsttyp in rstc_sr is loaded with the value 0x5, thus indicating that the last reset is a brownout reset. slck periph_nreset proc_nreset nrst nrst (nrst_out) >= external reset length mck processor startup = 3 cycles any freq. resynch. 2 cycles rsttyp any xxx resynch. 2 cycles 0x4 = user reset
109 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 15-7. brownout reset state 15.3.4.5 software reset the reset controller offers several commands used to assert the different reset signals. these commands are performed by writing the control register (rstc_cr) with the following bits at 1: ? procrst: writing procrst at 1 resets the processor and the watchdog timer. ? perrst: writing perrst at 1 resets all the embedded peripherals, including the memory system, and, in particular, the remap command. the peripheral reset is generally used for debug purposes. except for debug purposes, perrst must always be used in conjunction with procrst (perrst and procrst set both at 1 simultaneously.) ? extrst: writing extrst at 1 asserts low the nrst pin during a time defined by the field erstl in the mode register (rstc_mr). the software reset is entered if at least one of these bits is set by the software. all these com- mands can be performed independently or simultaneously. the software reset lasts 3 slow clock cycles. the internal reset signals are asserted as soon as the register write is performed. this is detected on the master clock (mck). they are released when the software reset is left, i.e.; syn- chronously to slck. if extrst is set, the nrst_out signal is asserted depending on the programming of the field erstl. however, the result ing falling edge on nrst does not lead to a user reset. slck periph_nreset proc_nreset brown_out or bod_reset nrst (nrst_out) external reset length 8 cycles (erstl=2) mck processor startup = 3 cycles any freq. rsttyp any xxx 0x5 = brownout reset resynch. 2 cycles
110 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary if and only if the procrst bit is set, the reset controller reports the software status in the field rsttyp of the status register (rstc_sr). other software resets are not reported in rsttyp. as soon as a software operation is detected, the bit srcmp (software reset command in prog- ress) is set in the status register (rstc_sr). it is cleared as soon as the software reset is left. no other software reset can be performed while the srcmp bit is set, and writing any value in rstc_cr has no effect. figure 15-8. software reset 15.3.4.6 watchdog reset the watchdog reset is entered when a watchdog fault occurs. this state lasts 3 slow clock cycles. when in watchdog reset, assertion of t he reset signals depends on the wdrproc bit in wdt_mr: ? if wdrproc is 0, the processor reset and the peripheral reset are asserted. the nrst line is also asserted, depending on the programming of the field erstl. however, the resulting low level on nrst does not result in a user reset state. ? if wdrproc = 1, only the processor reset is asserted. the watchdog timer is reset by the proc_nreset si gnal. as the watchdog fault always causes a processor reset if wdrsten is set, the watc hdog timer is always reset after a watchdog reset, and the watchdog is enabled by default and with a period set to a maximum. when the wdrsten in wdt_mr bit is reset, the watchdog fault has no impact on the reset controller. slck periph_nreset if perrst=1 proc_nreset if procrst=1 write rstc_cr nrst (nrst_out) if extrst=1 external reset length 8 cycles (erstl=2) mck processor startup = 3 cycles any freq. rsttyp any xxx 0x3 = software reset resynch. 1 cycle srcmp in rstc_sr
111 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 15-9. watchdog reset 15.3.5 reset state priorities the reset state manager manages the following priorities between the different reset sources, given in descending order: ? backup reset ? wake-up reset ?brownout reset ? watchdog reset ? software reset ? user reset particular cases are listed below: ? when in user reset: ? a watchdog event is impossible because the watchdog timer is being reset by the proc_nreset signal. ? a software reset is impossible, since the processor reset is being activated. ? when in software reset: ? a watchdog event has priority over the current state. ? the nrst has no effect. ? when in watchdog reset: ? the processor reset is active and so a software reset cannot be programmed. ? a user reset cannot be entered. 15.3.6 reset controller status register the reset controller status register (rstc_sr) provides several status fields: only if wdrproc = 0 slck periph_nreset proc_nreset wd_fault nrst (nrst_out) external reset length 8 cycles (erstl=2) mck processor startup = 3 cycles any freq. rsttyp any xxx 0x2 = watchdog reset
112 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? rsttyp field: this field gives the type of the last reset, as explained in previous sections. ? srcmp bit: this field indicates that a software reset command is in progress and that no further software reset should be performed until the end of the current one. this bit is automatically cleared at the end of the current software reset. ? nrstl bit: the nrstl bit of the status register gives the level of the nrst pin sampled on each mck rising edge. ? ursts bit: a high-to-low transition of the nrst pin sets the ursts bit of the rstc_sr register. this transition is also detected on the master clock (mck) rising edge (see figure 15-10 ). if the user reset is disabled (ursten = 0) and if the interruption is enabled by the urstien bit in the rstc_mr register, the ursts bit triggers an interrupt. reading the rstc_sr status register resets the ursts bit and clears the interrupt. ? bodsts bit: this bit indicates a brownout detection when the brownout reset is disabled (bod_rst_en = 0). it triggers an interrupt if the bit bodien in the rstc_mr register enables the interrupt. reading the rstc_sr register resets the bodsts bit and clears the interrupt. figure 15-10. reset controller status and interrupt mck nrst nrstl 2 cycle resynchronization 2 cycle resynchronization ursts read rstc_sr peripheral access rstc_irq if (ursten = 0) and (urstien = 1)
113 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 15.4 reset controller (rstc) user interface note: 1. the reset value of rstc_sr either reports a general reset or a wake-up reset depending on last rising power supply. table 15-1. register mapping offset register name access reset back-up reset 0x00 control register rstc_cr write-only - 0x04 status register rstc_sr read-only 0x0000_0001 0x0000_0000 0x08 mode register rstc_mr read-write - 0x0000_0000
114 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 15.4.1 reset controller control register name: rstc_cr address: 0xfffffd00 access type: write-only ? procrst: processor reset 0 = no effect. 1 = if key is correct, resets the processor. ? perrst: peripheral reset 0 = no effect. 1 = if key is correct, resets the peripherals. ? extrst: external reset 0 = no effect. 1 = if key is correct, asserts the nrst pin. ?key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ? 76543210 ????extrstperrst?procrst
115 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 15.4.2 reset controller status register name: rstc_sr address: 0xfffffd04 access type: read-only ? ursts: user reset status 0 = no high-to-low edge on nrst happened since the last read of rstc_sr. 1 = at least one high-to-low transition of nrst has been detected since the last read of rstc_sr. ? bodsts: brownout detection status 0 = no brownout high-to-low transition happened since the last read of rstc_sr. 1 = a brownout high-to-low transition has be en detected since the last read of rstc_sr. ? rsttyp: reset type reports the cause of the last processor reset. r eading this rstc_sr does not reset this field. ? nrstl: nrst pin level registers the nrst pin level at master clock (mck). ? srcmp: software reset command in progress 0 = no software command is being performed by the reset controller. the reset controller is ready for a software command. 1 = a software reset command is being performed by the reset controller. the reset controller is busy. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ??????srcmpnrstl 15 14 13 12 11 10 9 8 ????? rsttyp 76543210 ???????bodstsursts rsttyp reset type comments 0 0 0 general reset both vddcore and vddbu rising 0 0 1 wake up reset vddcore rising 0 1 0 watchdog reset watchdog fault occurred 0 1 1 software reset processor re set required by the software 1 0 0 user reset nrst pin detected low 1 0 1 brownout reset brownout reset occurred
116 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 15.4.3 reset controller mode register name: rstc_mr address: 0xfffffd08 access type: read-write ? ursten: user reset enable 0 = the detection of a low level on the pin nrst does not generate a user reset. 1 = the detection of a low level on the pin nrst triggers a user reset. ? urstien: user reset interrupt enable 0 = usrts bit in rstc_sr at 1 has no effect on rstc_irq. 1 = usrts bit in rstc_sr at 1 asserts rstc_irq if ursten = 0. ? bodien: brownout detection interrupt enable 0 = bodsts bit in rstc_sr at 1 has no effect on rstc_irq. 1 = bodsts bit in rstc_sr at 1 asserts rstc_irq. ? erstl: external reset length this field defines the external reset length. the external reset is asserted during a time of 2 (erstl+1) slow clock cycles. this allows assertion duration to be programmed between 60 s and 2 seconds. ?key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ???????bodien 15 14 13 12 11 10 9 8 ???? erstl 76543210 ? ? urstien ? ? ? ursten
117 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 16. real-time timer (rtt) 16.1 description the real-time timer is built around a 32-bit coun ter and used to count elapsed seconds. it gen- erates a periodic interrupt and/or triggers an alarm on a programmed value. 16.2 block diagram figure 16-1. real-time timer 16.3 functional description the real-time timer is used to count elapsed seconds. it is built around a 32-bit counter fed by slow clock divided by a programmable 16-bit va lue. the value can be programmed in the field rtpres of the real-time mode register (rtt_mr). programming rtpres at 0x00008000 corresponds to feeding the real-time counter with a 1 hz signal (if the slow clock is 32.768 hz). the 32-bit counter can count up to 2 32 seconds, corre- sponding to more than 136 years, then roll over to 0. the real-time timer can also be used as a free -running timer with a lower time-base. the best accuracy is achieved by writing rtpres to 3. programming rtpres to 1 or 2 is possible, but may result in losing status events because the st atus register is clear ed two slow clock cycles after read. thus if the rtt is configured to trigger an interrupt, the interrupt occurs during 2 slow clock cycles after reading rtt_sr. to prevent se veral executions of the interrupt handler, the interrupt must be disabled in the interrupt ha ndler and re-enabled when the status register is clear. slck rtpres rttinc alms 16-bit divider 32-bit counter almv = crtv rtt_mr rtt_vr rtt_ar rtt_sr rttincien rtt_mr 0 10 almien rtt_int rtt_mr set set rtt_sr read rtt_sr reset reset rtt_mr reload rtt_alarm rttrst rtt_mr rttrst
118 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary the real-time timer value (crtv) can be read at any time in the register rtt_vr (real-time value register). as this value can be updated asynchronously from the master clock, it is advis- able to read this register twice at the same value to improve accuracy of the returned value. the current value of the counter is compared with the value written in the alarm register rtt_ar (real-time alarm register). if the counter value matches the alarm, the bit alms in rtt_sr is set. the alarm register is set to its maximum value, corresponding to 0xffff_ffff, after a reset. the bit rttinc in rtt_sr is set each time the real-time timer counter is incremented. this bit can be used to start a periodic interrupt, the period being one second when the rtpres is pro- grammed with 0x8000 and slow clock equal to 32.768 hz. reading the rtt_sr status register resets the rttinc and alms fields. writing the bit rttrst in rtt_mr immediately re loads and restarts the clock divider with the new programmed value. this also resets the 32-bit counter. note: because of the asynchronism between the slow clock (sclk) and the system clock (mck): 1) the restart of the counter and the reset of the rtt_vr current value register is effective only 2 slow clock cycles after the write of th e rttrst bit in the rtt_mr register. 2) the status register fl ags reset is taken into account only 2 sl ow clock cycles after the read of the rtt_sr (status register). figure 16-2. rtt counting prescaler almv almv-1 0 almv+1 0 rtpres - 1 rtt apb cycle read rtt_sr alms (rtt_sr) apb interface mck rttinc (rtt_sr) almv+2 almv+3 ... apb cycle
119 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 16.4 real-time timer (rtt) user interface table 16-1. register mapping offset register name access reset 0x00 mode register rtt_mr read-write 0x0000_8000 0x04 alarm register rtt_ar read-write 0xffff_ffff 0x08 value register rtt_vr read-only 0x0000_0000 0x0c status register rtt_sr read-only 0x0000_0000
120 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 16.4.1 real-time timer mode register register name: rtt_mr address: 0xfffffd20 access type: read/write ? rtpres: real-time timer prescaler value defines the number of slck periods required to increment the real-time timer. rtpres is defined as follows: rtpres = 0: the prescaler period is equal to 2 16 . rtpres 0: the prescaler period is equal to rtpres. ? almien: alarm interrupt enable 0 = the bit alms in rtt_sr has no effect on interrupt. 1 = the bit alms in rtt_sr asserts interrupt. ? rttincien: real-time timer increment interrupt enable 0 = the bit rttinc in rtt_sr has no effect on interrupt. 1 = the bit rttinc in r tt_sr asserts interrupt. ? rttrst: real-time timer restart 1 = reloads and restarts the clock divider with the new programmed value. this also resets the 32-bit counter. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?????rttrstrttincienalmien 15 14 13 12 11 10 9 8 rtpres 76543210 rtpres
121 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 16.4.2 real-time timer alarm register register name: rtt_ar address: 0xfffffd24 access type: read/write ? almv: alarm value defines the alarm value (almv+1) compared with the real-time timer. 16.4.3 real-time timer value register register name: rtt_vr address: 0xfffffd28 access type: read-only ? crtv: current real-time value returns the current value of the real-time timer. 31 30 29 28 27 26 25 24 almv 23 22 21 20 19 18 17 16 almv 15 14 13 12 11 10 9 8 almv 76543210 almv 31 30 29 28 27 26 25 24 crtv 23 22 21 20 19 18 17 16 crtv 15 14 13 12 11 10 9 8 crtv 76543210 crtv
122 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 16.4.4 real-time timer status register register name: rtt_sr address: 0xfffffd2c access type: read-only ? alms: real-time alarm status 0 = the real-time alarm has not occured since the last read of rtt_sr. 1 = the real-time alarm occured since the last read of rtt_sr. ? rttinc: real-time timer increment 0 = the real-time timer has not been incremented since the last read of the rtt_sr. 1 = the real-time timer has been incremented since the last read of the rtt_sr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????rttincalms
123 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 17. periodic interval timer (pit) 17.1 description the periodic interval timer (pit) provides the operating system?s scheduler interrupt. it is designed to offer maximum accuracy and efficient management, even for systems with long response time . 17.2 block diagram figure 17-1. periodic interval timer 20-bit counter mck/16 piv pit_mr cpiv pit_pivr picnt 12-bit adder 0 0 read pit_pivr cpiv picnt pit_piir pits pit_sr set reset pitien pit_mr pit_irq 1 0 1 0 mck prescaler = ?
124 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 17.3 functional description the periodic interval timer aims at providing pe riodic interrupts for use by operating systems. the pit provides a programmable overflow counter and a reset-on-read feature. it is built around two counters: a 20-bit cpiv counter and a 12-bit picnt counter. both counters work at master clock /16. the first 20-bit cpiv counter increments from 0 up to a programmable overflow value set in the field piv of the mode register (pit_mr). when the counter cpiv reaches this value, it resets to 0 and increments the periodic interval counter, picnt. the status bit pits in the status regis- ter (pit_sr) rises and triggers an interrupt , provided the interrupt is enabled (pitien in pit_mr). writing a new piv value in pit_mr does not reset/restart the counters. when cpiv and picnt values are obtained by reading the periodic interval value register (pit_pivr), the overflow counter (picnt) is rese t and the pits is cleared, thus acknowledging the interrupt. the value of picnt gives the number of periodic intervals elapsed since the last read of pit_pivr. when cpiv and picnt values are obtained by reading the periodic interval image register (pit_piir), there is no effect on the counters cpiv and picnt, nor on the bit pits. for exam- ple, a profiler can read pit_piir without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading pit_pivr. the pit may be enabled/disabled using the pite n bit in the pit_mr register (disabled on reset). the piten bit only becomes effective when the cpiv value is 0. figure 17-2 illustrates the pit counting. after the pit enable bit is re set (piten= 0), the cpiv goes on counting until the piv value is reached, and is then reset. pit restarts counting, only if the piten is set again. the pit is stopped when the core enters debug state.
125 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 17-2. enabling/disabling pit with piten mck prescaler piv piv - 1 0 piten 10 0 15 cpiv 1 restarts mck prescaler 0 1 apb cycle read pit_pivr 0 picnt pits (pit_sr) mck apb interface apb cycle
126 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 17.4 periodic interval time r (pit) user interface table 17-1. register mapping offset register name access reset 0x00 mode register pit_mr read-write 0x000f_ffff 0x04 status register pit_sr read-only 0x0000_0000 0x08 periodic interval value register pit_pivr read-only 0x0000_0000 0x0c periodic interval image register pit_piir read-only 0x0000_0000
127 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 17.4.1 periodic interval timer mode register register name: pit_mr address: 0xfffffd30 access type: read/write ? piv: periodic interval value defines the value compared with the primary 20-bit counter of the periodic interval timer (cpiv). the period is equal to (piv + 1). ? piten: period interval timer enabled 0 = the periodic interval timer is disabled when the piv value is reached. 1 = the periodic interval timer is enabled. ? pitien: periodic interval timer interrupt enable 0 = the bit pits in pit_sr has no effect on interrupt. 1 = the bit pits in pit_sr asserts interrupt. 31 30 29 28 27 26 25 24 ??????pitienpiten 23 22 21 20 19 18 17 16 ???? piv 15 14 13 12 11 10 9 8 piv 76543210 piv
128 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 17.4.2 periodic interval timer status register register name: pit_sr address: 0xfffffd34 access type: read-only ? pits: periodic interval timer status 0 = the periodic interval timer has not reached piv since the last read of pit_pivr. 1 = the periodic interval timer has reached piv since the last read of pit_pivr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????pits
129 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 17.4.3 periodic interval timer value register register name: pit_pivr address: 0xfffffd38 access type: read-only reading this register clears pits in pit_sr. ? cpiv: current periodic interval value returns the current value of the periodic interval timer. ? picnt: periodic interval counter returns the number of occurences of periodic intervals since the last read of pit_pivr. 31 30 29 28 27 26 25 24 picnt 23 22 21 20 19 18 17 16 picnt cpiv 15 14 13 12 11 10 9 8 cpiv 76543210 cpiv
130 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 17.4.4 periodic interval timer image register register name: pit_piir address: 0xfffffd3c access type: read-only ? cpiv: current periodic interval value returns the current value of the periodic interval timer. ? picnt: periodic interval counter returns the number of occurences of periodic intervals since the last read of pit_pivr. 31 30 29 28 27 26 25 24 picnt 23 22 21 20 19 18 17 16 picnt cpiv 15 14 13 12 11 10 9 8 cpiv 76543210 cpiv
131 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 18. watch dog timer (wdt) 18.1 description the watchdog timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. it features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 khz). it can generate a general reset or a processor reset only. in addition, it can be stopped while the processor is in debug mode or idle mode. 18.2 block diagram figure 18-1. watchdog timer block diagram = 0 10 set reset read wdt_sr or reset wdt_fault (to reset controller) set reset wdfien wdt_int wdt_mr slck 1/128 12-bit down counter current value wdd wdt_mr <= wdd wdv wdrstt wdt_mr wdt_cr reload wdunf wderr reload write wdt_mr wdt_mr wdrsten
132 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 18.3 functional description the watchdog timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. it is supplied with vddcore. it re starts with initial values on processor reset. the watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field wdv of the mode register (wdt_m r). the watchdog timer uses the slow clock divided by 128 to establish the maximum watchdo g period to be 16 seconds (with a typical slow clock of 32.768 khz). after a processor reset, the value of wdv is 0xfff, corresponding to the maximum value of the counter with the external reset generation enabled (field wdrsten at 1 after a backup reset). this means that a default watchdog is running at reset, i.e., at power-up. the user must either disable it (by setting the wddis bit in wd t_mr) if he does not expect to use it or must reprogram it to meet the maximum watchdog period the application requires. the watchdog mode register (wdt_mr) can be written only once. only a processor reset resets it. writing the wdt_mr register reloads the timer with the newly programmed mode parameters. in normal operation, the user reloads the watchdog at regular intervals before the timer under- flow occurs, by writing the control register (wdt_cr) with the bit wdrstt to 1. the watchdog counter is then immediately reloaded from wdt_mr and restarted, and the slow clock 128 divider is reset and restarted. the wdt_cr register is write-protected. as a result, writing wdt_cr without the correct hard-coded key has no effect. if an underflow does occur, the ?wdt_fault? signal to the reset controller is asserted if the bit wdrsten is set in the mode register (wdt_mr). moreover, the bit wdunf is set in the watchdog status register (wdt_sr). to prevent a software deadlock that continuously triggers the watchdog, the reload of the watchdog must occur while the watchdog c ounter is within a window between 0 and wdd, wdd is defined in the watchdog mode register wdt_mr. any attempt to restart the watchdog while the watchdog counter is between wdv and wdd results in a watchdog error, even if the watchdog is disabled. the bit wderr is updated in the wdt_sr and the ?wdt_fault? signal to the reset controller is asserted. note that this feature can be disabled by programming a wdd value greater than or equal to the wdv value. in such a configuration, restarti ng the watchdog timer is permitted in the whole range [0; wdv] and does not generate an error. this is the default configuration on reset (the wdd and wdv values are equal). the status bits wdunf (watchdog underflow ) and wderr (watchdog error) trigger an inter- rupt, provided the bit wdfien is set in the mode register. the signal ?wdt_fault? to the reset controller causes a watchdog reset if the wdrsten bit is set as already explained in the reset controller programmer datasheet. in that case, the processor and the watchdog timer are reset, and the wderr and wdunf flags are reset. if a reset is generated or if wdt_sr is read, the status bits are reset, the interrupt is cleared, and the ?wdt_fault? signal to the reset controller is deasserted. writing the wdt_mr reloads and restarts the down counter. while the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits wdidlehlt and wddbghlt in the wdt_mr.
133 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 18-2. watchdog behavior 0 wdv wdd wdt_cr = wdrstt watchdog fault normal behavior watchdog error watchdog underflow fff if wdrsten is 1 if wdrsten is 0 forbidden window permitted window
134 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 18.4 watchdog timer (wdt) user interface table 18-1. register mapping offset register name access reset 0x00 control register wdt_cr write-only - 0x04 mode register wdt_mr read-write once 0x3fff_2fff 0x08 status register wdt_sr read-only 0x0000_0000
135 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 18.4.1 watchdog timer control register register name: wdt_cr address: 0xfffffd40 access type: write-only ? wdrstt: watchdog restart 0: no effect. 1: restarts the watchdog. ?key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????wdrstt
136 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 18.4.2 watchdog timer mode register register name: wdt_mr address: 0xfffffd44 access type: read-write once ? wdv: watchdog counter value defines the value loaded in the 12-bit watchdog counter. ? wdfien: watchdog fault interrupt enable 0: a watchdog fault (underflow or error) has no effect on interrupt. 1: a watchdog fault (underflow or error) asserts interrupt. ? wdrsten: watchdog reset enable 0: a watchdog fault (underflow or error) has no effect on the resets. 1: a watchdog fault (underflow or error) triggers a watchdog reset. ? wdrproc: watchdog reset processor 0: if wdrsten is 1, a watchdog fault (underflow or error) activates all resets. 1: if wdrsten is 1, a watchdog fault (underflow or error) activates the processor reset. ? wdd: watchdog delta value defines the permitted range for reloading the watchdog timer. if the watchdog timer value is less than or equal to w dd, writing wdt_cr with wdrs tt = 1 restarts the timer. if the watchdog timer value is greater than wdd, writing wdt_cr with wdrstt = 1 causes a watchdog error. ? wddbghlt: watchdog debug halt 0: the watchdog runs when the processor is in debug state. 1: the watchdog stops when the processor is in debug state. ? wdidlehlt: watchdog idle halt 0: the watchdog runs when the system is in idle mode. 1: the watchdog stops when the system is in idle state. 31 30 29 28 27 26 25 24 wdidlehlt wddbghlt wdd 23 22 21 20 19 18 17 16 wdd 15 14 13 12 11 10 9 8 wddis wdrproc wdrsten wdfien wdv 76543210 wdv
137 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? wddis: watchdog disable 0: enables the watchdog timer. 1: disables the watchdog timer.
138 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 18.4.3 watchdog timer status register register name: wdt_sr address: 0xfffffd48 access type: read-only ? wdunf: watchdog underflow 0: no watchdog underflow occurred since the last read of wdt_sr. 1: at least one watchdog underflow occurred since the last read of wdt_sr. ? wderr: watchdog error 0: no watchdog error occurred since the last read of wdt_sr. 1: at least one watchdog error occurred since the last read of wdt_sr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????wderrwdunf
139 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 19. shutdown controller (shdwn) 19.1 description the shutdown controller controls the pow er supplies vddio and vddcore and the wake-up detection on debounced input lines. 19.2 block diagram figure 19-1. shutdown contro ller block diagram 19.3 i/o lines description 19.4 product dependencies 19.4.1 power management the shutdown controller is continuously clock ed by slow clock. the power management con- troller has no effect on the behavior of the shutdown controller. 19.5 functional description the shutdown controller manages the main power supply. to do so, it is supplied with vddbu and manages wake-up input pins and one output pin, shdn . shutdown wake-up shutdown output controller shdn wkup0 shdw wkmode0 shutdown controller rtt alarm rttwken shdw_mr shdw_mr shdw_cr cptwk0 wakeup0 rttwk shdw_sr shdw_sr set set reset reset read shdw_sr read shdw_sr slck table 19-1. i/o lines description name description type wkup0 wake-up 0 input input shdn shutdown output output
140 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary a typical application connects the pin shdn to the shutdown input of the dc/dc converter pro- viding the main power supplies of the system , and especially vddcore and/or vddio. the wake-up inputs (wkup0) connect to any push-buttons or signal that wake up the system. the software is able to control the pin shdn by writing the shutdown control register (shdw_cr) with the bit shdw at 1. the shutdow n is taken into account only 2 slow clock cycles after the write of shdw_ cr. this register is password-protected and so the value written should contain the correct key for the command to be taken into account. as a result, the system should be powered down. a level change on wkup0 is used as wake-up. wake-up is configured in the shutdown mode register (shdw_mr). the transition detector can be programmed to detect either a positive or negative transition or any level change on wkup 0. the detection can also be disabled. pro- gramming is performed by defining wkmode0. moreover, a debouncing circuit can be programmed for wkup0. the debouncing circuit filters pulses on wkup0 shorter than the programmed number of 16 slck cycles in cptwk0 of the shdw_mr register. if the programmed level change is detected on a pin, a counter starts. when the counter reaches the value programmed in the corresponding field, cptwk0, the shdn pin is released. if a new input change is detected before the counter reaches the corre- sponding value, the counter is stopped and cleared. wakeup0 of the status register (shdw_sr) reports the detection of the programmed events on wkup0 with a reset after the read of shdw_sr. the shutdown controller can be programmed so as to activate the wake-up using the rtt alarm (the detection of the rising edge of the rt t alarm is synchronized with slck). this is done by writing the shdw_mr register using the rttwken fields. when enabled, the detec- tion of the rtt alarm is reported in the rttwk bi t of the shdw_sr status register. it is reset after the read of shdw_sr. when using the rtt alarm to wake up the system, the user must ensure that the rtt alar m status flag is clear ed before shutting down the system. otherwise, no rising edge of the status flag may be detected and the wake-up fails.
141 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 19.6 shutdown controller (shdwn) user interface table 19-2. register mapping offset register name access reset 0x00 shutdown control register shdw_cr write-only - 0x04 shutdown mode register shdw_mr read-write 0x0000_0003 0x08 shutdown status register shdw_sr read-only 0x0000_0000
142 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 19.6.1 shutdown control register register name: shdw_cr address: 0xfffffd10 access type: write-only ? shdw: shutdown command 0 = no effect. 1 = if key is correct, asserts the shdn pin. ?key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????shdw
143 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 19.6.2 shutdown mode register register name: shdw_mr address: 0xfffffd14 access type: read/write ? wkmode0: wake-up mode 0 ? cptwk0: counter on wake-up 0 defines the number of 16 slow clock cycles, the level detection on the corresponding input pin shall last before the wake- up event occurs. because of the inte rnal synchronization of wkup0, the shdn pin is released (cptwk x 16 + 1) slow clock cycles after the event on wkup. ? rttwken: real-time timer wake-up enable 0 = the rtt alarm signal has no effect on the shutdown controller. 1 = the rtt alarm signal forces the de-assertion of the shdn pin. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????rttwken 15 14 13 12 11 10 9 8 ???? 76543210 cptwk0 ? ? wkmode0 wkmode[1:0] wake-up inpu t transition selection 0 0 none. no detection is performed on the wake-up input 0 1 low to high level 1 0 high to low level 1 1 both levels change
144 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 19.6.3 shutdown status register register name: shdw_sr address: 0xfffffd18 access type: read-only ? wakeup0: wake-up 0 status 0 = no wake-up event occurred on the corresponding wake-up input since the last read of shdw_sr. 1 = at least one wake-up event occurred on the corresponding wake-up input since the last read of shdw_sr. ? rttwk: real-time timer wake-up 0 = no wake-up alarm from the rtt occurred since the last read of shdw_sr. 1 = at least one wake-up alarm from the rtt occurred since the last read of shdw_sr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????w akeup0
145 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 20. enhanced embedded flash controller (eefc) 20.1 description the enhanced embedded flash controller (eefc) ensures the interface of the flash block with the 32-bit internal bus. its 128-bit wide memory interface increases performance. it also man- ages the programming, erasing, locking and unlo cking sequences of the flash using a full set of commands. one of the commands returns the embedded flash descriptor definition that informs the system about the flash organization, thus making the software generic. 20.2 product dependencies 20.2.1 power management the enhanced embedded flash controller (eefc) is continuously clocked. the power man- agement controller has no effect on its behavior. 20.2.2 interrupt sources the enhanced embedded flash controller (eefc) interrupt line is connected to the system controller internal source of the advanced interrupt controller. using the enhanced embedded flash controller (eefc) interrupt requires the aic to be programmed first. the eefc interrupt is generated only on frdy bit rising. to know th e flash status, eefc flash status register should be read each time a system inte rrupt (sysirq, periph id = 0) occurs. 20.3 functional description 20.3.1 embedded flash organization the embedded flash interfaces directly with the 32-bit internal bus. the embedded flash is composed of: ? one memory plane organized in several pages of the same size. ? two 128-bit read buffers used for code read optimization. ? one 128-bit read buffer used for data read optimization. ? one write buffer that manages page programming. the write buffer size is equal to the page size. this buffer is write-only and accessible all along the 1 mbyte address space, so that each word can be written to its final address. ? several lock bits used to protect write/erase operation on several pages (lock region). a lock bit is associated with a lock region composed of several pages in the memory plane. ? several bits that may be set and cleared through the enhanced embedded flash controller (eefc) interface, called general purpose non volatile memory bits (gpnvm bits). the embedded flash size, the page size, the lock regions organization and gpnvm bits defini- tion are described in the product definition section. the enhanced embedded flash controller (eefc) returns a descriptor of the flash controlled after a get descriptor command issued by the application (see ?getting embedded flash descriptor? on page 151 ).
146 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 20-1. embedded flash organization start address page 0 lock region 0 lock region 1 memory plane page (m-1) lock region (n-1) page (n*m-1) start address + flash size -1 lock bit 0 lock bit 1 lock bit (n-1)
147 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 20.3.2 read operations an optimized controller manages embedded flash reads, thus increasing performance when the processor is running in arm and thumb mode by means of the 128-bit wide memory interface. the flash memory is accessible through 8-, 16- and 32-bit reads. as the flash block size is smaller than the addr ess space reserved for the internal memory area, the embedded flash wraps around the address space and appears to be repeated within it. the read operations can be performed with or without wait states. wait states must be pro- grammed in the field fws (flash read wait state) in the flash mode register (eefc_fmr). defining fws to be 0 enables the single-cycle access of the embedded flash. refer to the elec- trical characteristics for more details. 20.3.2.1 code read optimization a system of 2 x 128-bit buffers is added in order to optimize sequential code fetch. note: immediate consecutive code read accesses are not mandatory to benefit from this optimization. figure 20-2. code read optimization in arm mode for fws = 0 note: when fws is equal to 0, all the accesses are perform ed in a single-cycle access. flash access buffer 0 (128bits) master clock arm request (32-bit) xxx data to arm bytes 0-15 bytes 16-31 bytes 32-47 bytes 0-15 buffer 1 (128bits) bytes 32-47 bytes 0-3 bytes 4-7 bytes 8-11 bytes 12-15 bytes 16-19 bytes 20-23 bytes 24-27 xxx xxx bytes 16-31 @byte 0 @byte 4 @byte 8 @byte 12 @byte 16 @byte 20 @byte 24 @byte 28 @byte 32 bytes 28-31
148 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 20-3. code read optimization in arm mode for fws = 3 note: when fws is included between 1 and 3, in case of sequent ial reads, the first access takes (fws+1) cycles, the other ones o nly 1 cycle. figure 20-4. code read optimization in arm mode for fws = 4 note: when fws is included between 4 and 10, in case of sequential reads, the first access takes (fws+1) cycles, each first acce ss of the 128-bit read (fws-2) cycles, and the others only 1 cycle. flash access buffer 0 (128bits) master clock arm request (32-bit) data to arm buffer 1 (128bits) 0-3 xxx xxx bytes 16-31 @byte 0 @4 @8 bytes 0-15 bytes 16-31 bytes 32-47 bytes 48-63 xxx bytes 0-15 4-7 8-11 12-15 @12 @16 @20 24-27 28-31 32-35 36-39 16-19 20-23 40-43 44-47 @24 @28 @32 @36 @40 @44 @48 @52 bytes 32-47 48-51 flash access buffer 0 (128bits) master clock arm request (32-bit) data to arm buffer 1 (128bits) 0-3 xxx xxx bytes 16-31 @byte 0 @4 @8 bytes 0-15 bytes 16-31 bytes 32-47 xxx bytes 0-15 4-7 8-11 12-15 @12 @16 @20 24-27 16-19 20-23 @24 @28 @32 @36 @40 bytes 32-47 bytes 48-63 28-31 32-35 36-39
149 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 20.3.2.2 data read optimization the organization of the flash in 128 bits is associated with two 128-bit prefetch buffers and one 128-bit data read bu ffer, thus providing maximum system pe rformance. this buffer is added in order to start access at the following data during the second read. this speeds up sequential data reads if, for example, fws is equal to 1 (see figure 20-5 ). note: no consecutive data read accesses are ma ndatory to benefit from this optimization. figure 20-5. data read optimization in arm mode for fws = 1 flash access buffer (128bits) master clock arm request (32-bit) xxx data to arm bytes 0-15 bytes 16-31 bytes 0-15 bytes 0-3 4-7 8-11 12-15 16-19 20-23 xxx bytes 16-31 @byte 0 @ 4 @ 8 @ 12 @ 16 @ 20 @ 24 @ 28 @ 32 @ 36 xxx bytes 32-47 24-27 28-31 32-35
150 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 20.3.3 flash commands the enhanced embedded flash controller (eefc) offers a set of commands such as program- ming the memory flash, locking and unlocking lock regions, consecutive programming and locking and full flash erasing, etc. commands and read operations can be performed in parallel only on different memory planes. code can be fetched from one memory plane while a write or an erase operation is performed on another. in order to perform one of these commands, the flash command register (eefc_fcr) has to be written with the correct command using the field fcmd. as soon as the eefc_fcr register is written, the frdy flag and the field fvalue in the eefc_frr register are automatically cleared . once the current command is achieved, then the frdy flag is automatically set. if an interrupt has been enabled by setting the bit frdy in eefc_fmr, the interrupt line of the sys- tem controller is activated. all the commands are protected by the same keyw ord, which has to be written in the 8 highest bits of the eefc_fcr register. writing eefc_fcr with data that does not contain the correct key and/or with an invalid com- mand has no effect on the whole memory pl ane, but the fcmde flag is set in the eefc_fsr register. this flag is automatically cleared by a read access to the eefc_fsr register. when the current command writes or erases a page in a locked region, the command has no effect on the whole memory plane, but the flocke flag is set in the eefc_fsr register. this flag is automatically cleared by a read access to the eefc_fsr register. table 20-1. set of commands command value mnemonic get flash descriptor 0x0 getd write page 0x1 wp write page and lock 0x2 wpl erase page and write page 0x3 ewp erase page and write page then lock 0x4 ewpl erase all 0x5 ea set lock bit 0x8 slb clear lock bit 0x9 clb get lock bit 0xa glb set gpnvm bit 0xb sgpb clear gpnvm bit 0xc cgpb get gpnvm bit 0xd ggpb
151 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 20-6. command state chart 20.3.3.1 getting embedded flash descriptor this command allows the system to learn about the flash organization. the system can take full advantage of this information. for instance, a device could be replaced by one with more flash capacity, and so the software is able to adapt itself to the new configuration. to get the embedded flash descriptor, the application writes the getd command in the eefc_fcr register. the first word of the descr iptor can be read by the software application in the eefc_frr register as soon as the frdy flag in the eefc_fsr register rises. the next reads of the eefc_frr register provide the following word of the descriptor. if extra read oper- check if frdy flag set no yes read status: mc_fsr write fcmd and pagenb in flash command register check if flocke flag set check if frdy flag set no read status: mc_fsr yes yes locking region violation no check if fcmde flag set yes no bad keyword violation command successfull
152 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ations to the eefc_frr register are done after the last word of the descriptor has been returned, then the eefc_frr register value is 0 until the next valid command. 20.3.3.2 write commands several commands can be used to program the flash. flash technology requires that an erase is done before programming. the full memory plane can be erased at the same time, or several pages can be erased at the same time (refer to ?erase commands? on page 153 ). also, a page erase can be automatically done before a page write using ewp or ewpl commands. after programming, the page (the whole lock region) can be locked to prevent miscellaneous write or erase sequences. the lock bit can be automatically set after page programming using wpl or ewpl commands. data to be written are stored in an internal latch buffer. the size of the latch buffer corresponds to the page size. the latch buffer wraps around within the internal memory area address space and is repeated as many times as the number of pages within this address space. note: writing of 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption. write operations are performed in a number of wait states equal to the number of wait states for read operations. data are written to the latch buffer before the programming command is written to the flash command register eefc_fcr. the sequence is as follows: ? write the full page, at any page address, within the internal memory area address space. ? programming starts as soon as the page number and the programming command are written to the flash command register. the frdy bit in the flash programming status register (eefc_fsr) is auto matically cleared. ? when programming is completed, the bit frdy in the flash programming status register (eefc_fsr) rises. if an interrupt has been enabled by setting the bit frdy in eefc_fmr, the interrupt line of the syst em controller is activated. two errors can be detected in the eefc_fsr register after a programming sequence: table 20-2. flash descriptor definition symbol word index description fl_id 0 flash interface description fl_size 1 flash size in bytes fl_page_size 2 page size in bytes fl_nb_plane 3 number of planes. fl_plane[0] 4 number of bytes in the first plane. ... fl_plane[fl_nb_plane-1] 4 + fl_nb_plane - 1 number of bytes in the last plane. fl_nb_lock 4 + fl_nb_plane number of lock bits. a bit is associated with a lock region. a lock bit is used to prevent write or erase operations in the lock region. fl_lock[0] 4 + fl_nb_plane + 1 number of bytes in the first lock region. ...
153 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? a command error: a bad keyword has been written in the eefc_fcr register. ? a lock error: the page to be programmed belongs to a locked region. a command must be previously run to unlock the corresponding region. by using the wp command, a page can be programmed in several steps if it has been erased before (see figure 20-7 ). figure 20-7. example of partial page programming 20.3.3.3 erase commands erase commands are allowed only on unlocked regions. the erase sequence is: ? erase starts as soon as one of the erase commands and the farg field are written in the flash command register. ? when the programming completes, the frdy bit in the flash programming status register (eefc_fsr) rises. if an interrupt has been enabled by setting the bit frdy in eefc_fmr, the interrupt line of the syst em controller is activated. two errors can be detected in the eefc_fsr register after a programming sequence: ? a command error: a bad keyword has been written in the eefc_fcr register. ? a lock error: at least one page to be erased belongs to a locked region. the erase command has been refused, no page has been erased. a command must be previously run to unlock the corresponding region. 20.3.3.4 lock bit protection lock bits are associated with several pages in the embedded flash memory plane. this defines lock regions in the embedded flash memory plane. they prevent writing/erasing protected pages. the lock sequence is: ? the set lock command (slb) and a page number to be protected are written in the flash command register. erase all flash programming of the second part of page y programming of the third part of page y 32-bit wide 32-bit wide 32-bit wide x words ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ... ca fe ca fe ca fe ca fe ca fe ca fe ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ca fe ca fe ca fe ca fe ca fe ca fe de ca de ca de ca de ca de ca de ca ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff step 1. step 2. step 3. ... ... ... ... ... ... ... ... ... ... ... x words x words x words so page y erased
154 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? when the locking completes, the bit frdy in the flash programming status register (eefc_fsr) rises. if an interrupt has been enabled by setting the bit frdy in eefc_fmr, the interrupt line of the syst em controller is activated. ? if the lock bit number is greater than the total number of lock bits, then the command has no effect. the result of the slb command can be checked running a glb (get lock bit) command. one error can be detected in the eefc_fsr register after a programming sequence: ? a command error: a bad keyword has been written in the eefc_fcr register. it is possible to clear lock bits previously set. then the locked region can be erased or pro- grammed. the unlock sequence is: ? the clear lock command (clb) and a page number to be unprotected are written in the flash command register. ? when the unlock completes, the bit frdy in the flash programming status register (eefc_fsr) rises. if an interrupt has been enabled by setting the bit frdy in eefc_fmr, the interrupt line of the syst em controller is activated. ? if the lock bit number is greater than the total number of lock bits, then the command has no effect. one error can be detected in the eefc_fsr register after a programming sequence: ? a command error: a bad keyword has been written in the eefc_fcr register. the status of lock bits can be returned by the enhanced embedded flash controller (eefc). the get lock bit status sequence is: ? the get lock bit command (glb) is written in the flash command register. farg field is meaningless. ? when the command completes, the bit frdy in the flash programming status register (eefc_fsr) rises. if an interrupt has been enabled by setting the bit frdy in eefc_fmr, the interrupt line of the syst em controller is activated. ? lock bits can be read by the software application in the eefc_frr register. the first word read corresponds to the 32 first lock bits, next reads providing the next 32 lock bits as long as it is meaningful. extra reads to the eefc_frr register return 0. for example, if the third bit of the first word read in the eefc_frr is set, then the third lock region is locked. one error can be detected in the eefc_fsr register after a programming sequence: ? a command error: a bad keyword has been written in the eefc_fcr register. note: access to the flash in read is permitted when a set, clear or get lock bit command is performed. 20.3.3.5 gpnvm bit gpnvm bits do not interfere with the embedded fl ash memory plane. refer to the product defi- nition section for information on the gpnvm bit action. the set gpnvm bit sequence is: ? start the set gpnvm bit command (sgpb) by writing the flash command register with the sgpb command and the number of the gpnvm bit to be set.
155 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? when the gpvnm bit is set, the bit frdy in the flash programming status register (eefc_fsr) rises. if an interrupt was enabled by setting the bit frdy in eefc_fmr, the interrupt line of the system controller is activated. ? if the gpnvm bit number is greater than the total number of gpnvm bits, then the command has no effect. the result of the sgpb command can be checked by running a ggpb (get gpnvm bit) command. one error can be detected in the eefc_fsr register after a programming sequence: ? a command error: a bad keyword has been written in the eefc_fcr register. it is possible to clear gpnvm bits previo usly set. the clear gpnvm bit sequence is: ? start the clear gpnvm bit command (cgpb) by writing the flash command register with cgpb and the number of the gpnvm bit to be cleared. ? when the clear completes, the bit frdy in the flash programming status register (eefc_fsr) rises. if an interrupt has been enabled by setting the bit frdy in eefc_fmr, the interrupt line of the syst em controller is activated. ? if the gpnvm bit number is greater than the total number of gpnvm bits, then the command has no effect. one error can be detected in the eefc_fsr register after a programming sequence: ? a command error: a bad keyword has been written in the eefc_fcr register. the status of gpnvm bits can be returned by the enhanced embedded flash controller (eefc). the sequence is: ? start the get gpnvm bit command by writing the flash command register with ggpb. the farg field is meaningless. ? when the command completes, the bit frdy in the flash programming status register (eefc_fsr) rises. if an interrupt has been enabled by setting the bit frdy in eefc_fmr, the interrupt line of the syst em controller is activated. ? gpnvm bits can be read by the software application in the eefc_frr register. the first word read corresponds to the 32 first gpnvm bits, following reads provide the next 32 gpnvm bits as long as it is meaningful. extr a reads to the eefc_frr register return 0. for example, if the third bit of the first word read in the eefc_frr is set, then the third gpnvm bit is active. one error can be detected in the eefc_fsr register after a programming sequence: ? a command error: a bad keyword has been written in the eefc_fcr register. note: access to the flash in read is permitted w hen a set, clear or get gpnvm bit command is performed. 20.3.3.6 security bit protection when the security is enabled, ac cess to the flash, either through the ice interface or through the fast flash programming interface, is forbi dden. this ensures the confidentiality of the code programmed in the flash. the security bit is gpnvm0. disabling the security bit can only be achieved by asserti ng the erase pin at 1, and after a full flash erase is performed. when the security bit is deactivated, all accesses to the flash are permitted.
156 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 20.4 enhanced embedded flash controll er (eefc) user interface the user interface of the enhanced embedded flash controller (eefc) is integrated within the system controller with base address 0xffff fa00 . table 20-3. register mapping offset register name access reset state 0x00 eefc flash mode register eefc _fmr read-write 0x0 0x04 eefc flash command register eefc _fcr write-only ? 0x08 eefc flash status register eefc _fsr read-only 0x00000001 0x0c eefc flash result register eefc _frr read-only 0x0 0x10 reserved ? ? ?
157 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 20.4.1 eefc flash mode register register name : eefc_fmr address: 0xfffffa00 access type : read-write offset :0x60 ? frdy: ready interrupt enable 0: flash ready does not generate an interrupt. 1: flash ready (to accept a new command) generates an interrupt. ? fws: flash wait state this field defines the number of wait states for read and write operations: number of cycles for read/write operations = fws+1 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???? fws 76543210 ? ?????frdy
158 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 20.4.2 eefc flash command register register name : eefc_fcr address: 0xfffffa04 access type : write-only offset :0x64 ? fcmd: flash command this field defines the flash commands. refer to ?flash commands? on page 150 . ? farg: flash command argument ? fkey: flash writing protection key this field should be written with the value 0x5a to enable the command defined by the bits of the register. if the field is wri t- ten with a different value, the write is not performed and no action is started. 31 30 29 28 27 26 25 24 fkey 23 22 21 20 19 18 17 16 farg 15 14 13 12 11 10 9 8 farg 76543210 fcmd erase command for erase all command, this field is meaningless. programming command farg defines the page number to be programmed. lock command farg defines the page number to be locked. gpnvm command farg defines the gpnvm number. get commands field is meaningless.
159 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 20.4.3 eefc flash status register register name : eefc_fsr address: 0xfffffa08 access type : read-only offset :0x68 ? frdy: flash ready status 0: the enhanced embedded flash controller (eefc) is busy. 1: the enhanced embedded flash controller (eefc) is ready to start a new command. when it is set, this flags triggers an interrupt if the frdy flag is set in the eefc_fmr register. this flag is automatically cleared when the en hanced embedded flash controller (eefc) is busy. ? fcmde: flash command error status 0: no invalid commands and no bad keywords were written in the flash mode register eefc_fmr. 1: an invalid command and/or a bad keyword was/were written in the flash mode register eefc_fmr. this flag is automatically cleared when eefc_fsr is read or eefc_fcr is written. ? flocke: flash lock error status 0: no programming/erase of at least one locked region has happened since the last read of eefc_fsr. 1: programming/erase of at least one locked region has happened since the last read of eefc_fsr. this flag is automatically cleared when eefc_fsr is read or eefc_fcr is written. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????flockefcmdefrdy
160 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 20.4.4 eefc flash result register register name : eefc_frr address: 0xfffffa0c access type : read-only offset :0x6c ? fvalue: flash result value the result of a flash command is returned in this register. if the size of the result is greater than 32 bits, then the next resulting value is accessible at the next register read. 31 30 29 28 27 26 25 24 fvalue 23 22 21 20 19 18 17 16 fvalue 15 14 13 12 11 10 9 8 fvalue 76543210 fvalue
161 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 21. at91sam9xe bus matrix 21.1 description bus matrix implements a multi-layer ahb, based on ahb-lite protocol, that enables parallel access paths between multiple ah b masters and slaves in a syst em, which increases the over- all bandwidth. bus matrix interconnects 6 ahb masters to 5 ahb slaves. the normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency). the bus matrix user interf ace is compliant with arm ? advance peripheral bus and provides a chip configuration user interface with registers that allow the bus matrix to support application specific features. 21.2 memory mapping bus matrix provides one decoder for every ahb master interface. the decoder offers each ahb master several memory mappings. in fact, depending on the product, each memory area may be assigned to several slaves. booting at the same address while using different ahb slaves (i.e., external ram, internal rom or internal flash, etc.) becomes possible. the bus matrix user interface provides mast er remap control regist er (matrix_mrcr) that allows to perform remap action for every master independently. 21.3 special bus granting techniques the bus matrix provides some speculative bus granting techniques in order to anticipate access requests from some masters. this mechanism a llows to reduce latency at first accesses of a burst or single transfer. the bus granting mechanism allows to set a default master for every slave. at the end of the current access, if no other re quest is pending, the slave remains connected to its associated default master. a slave can be as sociated with three kinds of default masters: no default master, last access master and fixed default master. 21.3.1 no default master at the end of the current access, if no other request is pending, the slave is disconnected from all masters. no default ma ster suits low power mode. 21.3.2 last access master at the end of the current access, if no other re quest is pending, the slave remains connected to the last master that performed an access request. 21.3.3 fixed default master at the end of the current access, if no other request is pending, the slave connects to itsfixed default master. unlike last access master, the fixed master doesn?t change unless the user mod- ifies it by a software acti on (field fixed_defmstr of the related matrix_scfg). to change from one kind of default master to another, the bus matrix user interface provides the slave configuration registers, one for each slave, that allow to set a default master for each slave. the slave configuration register contains two fields: defmstr_type and fixed_defmstr. the 2- bit defmstr_type field allows to choose the default master type (no default, last access master, fixed default master) whereas the 4-bit
162 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary fixed_defmstr field allows to choose a fixed default master provided that defmstr_type is set to fixed default master. please refer to the bus matrix user interface description. 21.4 arbitration the bus matrix provides an arbitration mechani sm that allows to reduce latency when conflict cases occur, basically when two or more masters try to access the same sl ave at the same time. one arbiter per ahb slave is provided, allowing to arbitrate each slave differently. the bus matrix provides to the user the possi bility to choose between 2 arbitration types, and this for each slave: 1. round-robin arbitration (the default) 2. fixed priority arbitration this choice is given through the field arbt of the slave configuration registers (matrix_scfg). each algorithm may be complemented by selecting a default master configuration for each slave. when a re-arbitration has to be done, it is realiz ed only under some spec ific conditions detailed in the following paragraph. 21.4.1 arbitration rules each arbiter has the ability to arbi trate between two or more differ ent master?s requests. in order to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitra- tion may only take place during the following cycles: 1. idle cycles: when a slave is not connected to any master or is connected to a master which is not currently accessing it. 2. single cycles: when a slave is currently doing a single access. 3. end of burst cycles: when the current cycle is the last cycle of a burst transfer. for defined length burst, predicted end of burst match the size of the transfer but is man- aged differently for undefined length burst (see ?undefined length burst arbitration? on page iv.). 4. slot cycle limit: when the slot cycle counter has reach the limit value indicating that the current master access is too long and must be breaked (see section 21.4.1.2 ?slot cycle limit arbitration? on page 163 ). 21.4.1.1 undefined length burst arbitration in order to avoid too long slave handling durin g undefined length bursts (incr), the bus matrix provides specific logic in order to re-arbitrate before the end of the incr transfer. a predicted end of burst is used as for defined length burst transfer, which is selected between the following: 1. infinite: no predicted end of burst is generated and therefore incr burst transfer will never be broken. 2. four beat bursts: predicted end of burst is generated at the end of each four beat boundary inside incr transfer. 3. eight beat bursts: predicted end of burst is generated at the end of each eight beat boundary inside incr transfer. 4. sixteen beat bursts: predicted end of burst is generated at the end of each sixteen beat boundary inside incr transfer.
163 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary this selection can be done through the field ulbt of the master configuration registers (matrix_mcfg). 21.4.1.2 slot cycle limit arbitration the bus matrix contains specific logic to break too long accesses such as very long bursts on a very slow slave (e.g. an external low speed memory). at the beginning of the burst access, a counter is loaded with the value previously written in the slot_cycle field of the related slave configuration register (matrix_scfg) and decreased at each clock cycle. when the counter reaches zero, the arbiter has the ab ility to re-arbitrate at the end of the current byte, half word or word transfer. 21.4.2 round-robin arbitration this algorithm allows the bus matrix arbiters to dispatch the requests from different masters to the same slave in a round-robin manner. if two or more master?s requests arise at the same time, the master with the lowest number is first serviced then the others are serviced in a round- robin manner. there are three round-robin algorithms implemented: ? round-robin arbitration without default master ? round-robin arbitration with last access master ? round-robin arbitration with fixed default master 21.4.2.1 round-robin arbitration without default master this is the main algorithm used by bus matrix arbiters. it allows the bus matrix to dispatch requests from different masters to the same slave in a pure round-robin manner. at the end of the current access, if no other request is pending, the slave is disconnected from all masters. this configuration incurs one latency cycle for the first access of a burst. arbitration without default master can be used for masters that perform significant bursts. 21.4.2.2 round-robin arbitration with last access master this is a biased round-robin algorithm used by bus matrix arbiters. it allows the bus matrix to remove the one latency cycle for the last master that accessed the slave. at the end of the cur- rent transfer, if no other master request is pending, the slave remains connected to the last master that performs the acce ss. other non privileged masters will still get one latency cycle if they want to access the same slave. this technique can be used for masters that mainly perform single accesses. 21.4.2.3 round-robin arbitration with fixed default master this is another biased round-robin algorithm, it allows the bus matrix arbiters to remove the one latency cycle for the fixed default master per slav e. at the end of the current access, the slave remains connected to its fixed default master. requests attempted by this fixed default master do not cause any latency whereas other non privileged masters get one latency cycle. this tech- nique can be used for masters that mainly perform single accesses. 21.4.3 fixed priority arbitration this algorithm allows the bus matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defin ed by the user. if two or more master?s requests are active at the same time, the master with the highest priority number is serviced first. if two or
164 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary more master?s requests with the same priority are active at the same time, the master with the highest number is serviced first. for each slave, the priority of each master may be defined through the priority registers for slaves (matrix_pras and matrix_prbs).
165 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 21.5 bus matrix (matrix) user interface table 21-1. register mapping offset register name access reset value 0x0000 master configuration register 0 matrix_mcfg0 read-write 0x00000000 0x0004 master configuration register 1 matrix_mcfg1 read-write 0x00000000 0x0008 master configuration register 2 matrix_mcfg2 read-write 0x00000000 0x000c master configuration register 3 matrix_mcfg3 read-write 0x00000000 0x0010 master configuration register 4 matrix_mcfg4 read-write 0x00000000 0x0014 master configuration register 5 matrix_mcfg5 read-write 0x00000000 0x0018 - 0x003c reserved ? ? ? 0x0040 slave configuration register 0 matrix_scfg0 read-write 0x00010010 0x0044 slave configuration register 1 matrix_scfg1 read-write 0x00050010 0x0048 slave configuration register 2 matrix_scfg2 read-write 0x00000010 0x004c slave configuration register 3 matrix_scfg3 read-write 0x00000010 0x0050 slave configuration register 4 matrix_scfg4 read-write 0x00000010 0x0054 - 0x007c reserved ? ? ? 0x0080 priority register a for slave 0 matrix_pras0 read-write 0x00000000 0x0084 reserved ? ? ? 0x0088 priority register a for slave 1 matrix_pras1 read-write 0x00000000 0x008c reserved ? ? ? 0x0090 priority register a for slave 2 matrix_pras2 read-write 0x00000000 0x0094 reserved ? ? ? 0x0098 priority register a for slave 3 matrix_pras3 read-write 0x00000000 0x009c reserved ? ? ? 0x00a0 priority register a for slave 4 matrix_pras4 read-write 0x00000000 0x00a8 - 0x00fc reserved ? ? ? 0x0100 master remap control register matrix_mrcr read-write 0x00000000 0x0104 - 0x010c reserved ? ? ?
166 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 21.5.1 bus matrix master configuration registers register name: matrix_mcfg0...matrix_mcfg5 address: 0xffffee00 access type: read-write ? ulbt : undefined length burst type 0: infinite length burst no predicted end of burst is generated and therefore incr bursts coming from this master cannot be broken. 1: single access the undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the incr burst. 2: four beat burst the undefined length burst is split into 4-beat burst allowing rearbitration at each 4-beat burst end. 3: eight beat burst the undefined length burst is split into 8-beat burst allowing rearbitration at each 8-beat burst end. 4: sixteen beat burst the undefined length burst is split into 16-beat burst allowing rearbitration at each 16-beat burst end. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????? ulbt
167 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 21.5.2 bus matrix slave configuration registers register name: matrix_scfg0...matrix_scfg4 address: 0xffffee40 access type: read-write ? slot_cycle : maximum number of allowed cycles for a burst when the slot_cycle limit is reach for a burst it may be broken by another master trying to access this slave. this limit has been placed to avoid locking very slow slave by when very long burst are used. this limit should not be very small thou gh. unreasonable small value will break ev ery burst and bus matrix will spend its time to arbitrate without performing any data transfer. 16 cycles is a reasonable value for slot_cycle. ? defmastr_type : default master type 0: no default master at the end of current slave access, if no other master request is pending, the slave is disconnected from all masters. this results in having a one cycle latency for the firs t acccess of a burst transfe r or for a single access. 1: last default master at the end of current slave access, if no other master request is pending, the slave stay connected with the last master hav- ing accessed it. this results in not having the one cycle latency when the last master re-tries access on the slave again. 2: fixed default master at the end of the current slave access, if no other master request is pending, the slave connects to the fixed master which number has been written in the fixed_defmstr field. this results in not having the one cycle latency when the fixed master re-tries access on the slave again. ? fixed_defmstr : fixed default master this is the number of the default master for this slave. only used if defmastr_type is 2. specifying the number of a master which is not connected to the selected slave is equivale nt to setting defmastr_type to 0. ? arbt : arbitration type 0: round-robin arbitration 1: fixed priority arbitration 2: reserved 3: reserved 31 30 29 28 27 26 25 24 ?????? arbt 23 22 21 20 19 18 17 16 ? fixed_defmstr defmstr_type 15 14 13 12 11 10 9 8 ???????? 76543210 slot_cycle
168 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 21.5.3 bus matrix priority registers for slaves register name: matrix_prs0...matrix_prs4 access type: read-write ? mxpr : master x priority fixed prority of master x for access to the selected slave.the higher the number, the higher the priority. 21.5.4 bus matrix master remap control register register name: matrix_mrcr address: 0xffffef00 access type: read-write reset: 0x0000_0000 ? rcbx : remap command bit for ahb master x 0 : disable remapped address decoding for the selected master 1 : enable remapped address decoding for the selected master 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?? m5pr ?? m4pr 15 14 13 12 11 10 9 8 ?? m3pr ?? m2pr 76543210 ?? m1pr ?? m0pr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????? - 76543210 ??????rcb1rcb0
169 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 21.6 chip configuration user interface table 21-2. chip configuration user interface offset register name access reset value 0x0110 - 0x0118 reserved ? ? ? 0x011c ebi chip select assignement register ebi_csa read-write 0x00010000 0x0130 - 0x01fc reserved ? ? ?
170 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 21.6.1 ebi chip select assignement register register name: ebi_csa access type: read-write reset: 0x0001_0000 ? ebi_cs1a: ebi chip select 1 assignment 0 = ebi chip select 1 is assigned to the static memory controller. 1 = ebi chip select 1 is assigned to the sdram controller. ? ebi_cs3a: ebi chip select 3 assignment 0 = ebi chip select 3 is only assigned to the static memory controller and ebi_ncs3 behaves as defined by the smc. 1 = ebi chip select 3 is assigned to the static memory controller and the smartmedia logic is activated. ? ebi_cs4a: ebi chip select 4 assignment 0 = ebi chip select 4 is only assigned to the static memory controller and ebi_ncs4 behaves as defined by the smc. 1 = ebi chip select 4 is assigned to the static memory controller and the compactflash logic (first slot) is activated. ? ebi_cs5a: ebi chip select 5 assignment 0 = ebi chip select 5 is only assigned to the static memory controller and ebi_ncs5 behaves as defined by the smc. 1 = ebi chip select 5 is assigned to the static memory co ntroller and the compactflash logic (second slot) is activated. ? ebi_dbpuc: ebi data bus pull-up configuration 0 = ebi d0 - d15 data bus bits are interna lly pulled-up to the vddiom0 power supply. 1 = ebi d0 - d15 data bus bits are not internally pulled-up. ? vddiomsel: memory voltage selection 0 = memories are 1.8v powered. 1 = memories are 3.3v powered. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????vddiomsel 15 14 13 12 11 10 9 8 ???????ebi_dbpuc 76543210 ? ? ebi_cs5a ebi_cs4a ebi_cs3a ? ebi_cs1a ?
171 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 22. at91sam9xe128/256/512 external bus interface 22.1 description the external bus interface (ebi) is designed to ensure the successful data transfer between several external devices and the em bedded memory controller of an arm ? -based device. the static memory, sdram and ecc controllers are all featured external memory controllers on the ebi. these external memory controllers are capable of handling several types of external memory and peripheral devices, such as sram, prom, eprom, eeprom, flash, and sdram. the ebi also supports the compactflash and the nand flash protocols via integrated circuitry that greatly reduces the requirements for external components. furthermore, the ebi handles data transfers with up to six external devices, each assigned to six address spaces defined by the embedded memory controller. data transfers are performed through a 16-bit or 32-bit data bus, an address bus of up to 26 bits, up to eight chip select lines (ncs[7:0]) and several control pins that are generally multiplexed between the different external memory controllers.
172 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 22.2 block diagram 22.2.1 external bus interface figure 22-1 shows the organization of the external bus interface. figure 22-1. organization of the external bus interface external bus interface d[15:0] a[15:2], a[22:18] pio mux logic user interface chip select assignor static memory controller sdram controller bus matrix apb ahb address decoders a16/ba0 a0/nbs0 a1/nwr2/nbs2 a17/ba1 ncs0 nrd/noe/cfoe ncs1/sdcs nwr0/nwe/cfwe nwr1/nbs1/cfior nwr3/nbs3/cfiow sdck sdcke ras cas sdwe d[31:16] a[25:23] cfrnw/a25 ncs4/cfcs0 ncs5/cfcs1 ncs2/ncs6/ncs7 cfce1 cfce2 nwait sda10 nandoe nandwe nand flash logic compactflash logic ecc controller ncs3/nandcs
173 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 22.3 i/o lines description table 22-1. ebi i/o lines description name function type active level ebi ebi_d0 - ebi_d31 data bus i/o ebi_a0 - ebi_a25 address bus output ebi_nwait external wait signal input low smc ebi_ncs0 - ebi_ncs7 chip select lines output low ebi_nwr0 - ebi_nwr3 wri te signals output low ebi_noe output enable output low ebi_nrd read signal output low ebi_nwe write enable output low ebi_nbs0 - ebi_nbs3 byte mask signals output low ebi for compactflash support ebi_cfce1 - ebi_cfce2 compactf lash chip enable output low ebi_cfoe compactflash output enable output low ebi_cfwe compactflash write enable output low ebi_cfior compactflash i/o read signal output low ebi_cfiow compactflash i/o write signal output low ebi_cfrnw compactflash read not write signal output ebi_cfcs0 - ebi_cfcs1 compactflash chip select lines output low ebi for nand flash support ebi_nandcs nand flash chip select line output low ebi_nandoe nand flash output enable output low ebi_nandwe nand flash write enable output low sdram controller ebi_sdck sdram clock output ebi_sdcke sdram clock enable output high ebi_sdcs sdram controller chip select line output low ebi_ba0 - ebi_ba1 bank select output ebi_sdwe sdram write enable output low ebi_ras - ebi_cas row and column signal output low ebi_nwr0 - ebi_nwr3 wri te signals output low ebi_nbs0 - ebi_nbs3 byte mask signals output low ebi_sda10 sdram address 10 line output
174 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary the connection of some signals through the mux logic is not direct and depends on the memory controller in use at the moment. table 22-2 on page 174 details the connections between the two memory controllers and the ebi pins. table 22-2. ebi pins and memory controllers i/o lines connections ebix pins sdramc i/o lines smc i/o lines ebi_nwr1/nbs1/cfior nbs1 nwr1/nub ebi_a0/nbs0 not supported smc_a0/nlb ebi_a1/nbs2/nwr2 not supported smc_a1 ebi_a[11:2] sdramc_a[9:0] smc_a[11:2] ebi_sda10 sdramc_a10 not supported ebi_a12 not supported smc_a12 ebi_a[14:13] sdramc_a [12:11] smc_a[14:13] ebi_a[22:15] not supported smc_a[22:15] ebi_a[25:23] not supported smc_a[25:23] ebi_d[31:0] d[31:0] d[31:0]
175 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 22.4 application example 22.4.1 hardware interface table 22-3 on page 175 details the connections to be applied between the ebi pins and the external devices for each memory controller. notes: 1. nwr1 enables upper byte writes. nwr0 enables lower byte writes. 2. nwrx enables corresponding byte x writes. (x = 0,1,2 or 3) 3. nbs0 and nbs1 enable respectively lower and upper bytes of the lower 16-bit word. 4. nbs2 and nbs3 enable respectively lower and upper bytes of the upper 16-bit word. 5. bex: byte x enable (x = 0,1, 2 or 3) table 22-3. ebi pins and external static devices connections signals: ebi_ pins of the interfaced device 8-bit static device 2 x 8-bit static devices 16-bit static device 4 x 8-bit static devices 2 x 16-bit static devices 32-bit static device controller smc d0 - d7 d0 - d7 d0 - d7 d0 - d7 d0 - d7 d0 - d7 d0 - d7 d8 - d15 ? d8 - d15 d8 - d15 d8 - d15 d8 - 15 d8 - 15 d16 - d23 ? ? ? d16 - d23 d16 - d23 d16 - d23 d24 - d31 ? ? ? d24 - d31 d24 - d31 d24 - d31 a0/nbs0 a0 ? nlb ? nlb (3) be0 (5) a1/nwr2/nbs2 a1 a0 a0 we (2) nlb (4) be2 (5) a2 - a22 a[2:22] a[1:21] a[1:21] a[0:20] a[0:20] a[0:20] a23 - a25 a[23:25] a[22:24] a[22:24] a[21:23] a[21:23] a[21:23] ncs0 cs cs cs cs cs cs ncs1/sdcs cs cs cs cs cs cs ncs2 cs cs cs cs cs cs ncs3/nandcs cs cs cs cs cs cs ncs4/cfcs0 cs cs cs cs cs cs ncs5/cfcs1 cs cs cs cs cs cs ncs6 cs cs cs cs cs cs ncs7 cs cs cs cs cs cs nrd/cfoe oe oe oe oe oe oe nwr0/nwe we we (1) we we (2) we we nwr1/nbs1 ? we (1) nub we (2) nub (3) be1 (5) nwr3/nbs3 ? ? ? we (2) nub (4) be3 (5)
176 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary table 22-4. ebi pins and external devices connections signals: ebi_ pins of the interfaced device sdram compactflash (ebi only) compactflash true ide mode (ebi only) nand flash controller sdramc smc d0 - d7 d0 - d7 d0 - d7 d0 - d7 i/o0-i/o7 d8 - d15 d8 - d15 d8 - 15 d8 - 15 i/o8-i/o15 d16 - d31 d16 - d31 ? ? ? a0/nbs0 dqm0 a0 a0 ? a1/nwr2/nbs2 dqm2 a1 a1 ? a2 - a10 a[0:8] a[2:10] a[2:10] ? a11 a9 ? ? ? sda10 a10 ? ? ? a12 ? ? ? ? a13 - a14 a[11:12] ? ? ? a15 ? ? ? ? a16/ba0 ba0 ? ? ? a17/ba1 ba1 ? ? ? a18 - a20 ? ? ? ? a21 ? ? ? ale a22 ? reg reg cle a23 - a24 ? ? ? ? a25 ? cfrnw (1) cfrnw (1) ? ncs0 ? ? ? ? ncs1/sdcs cs ? ? ? ncs2 ? ? ? ? ncs3/nandcs ? ? ? ? ncs4/cfcs0 ? cfcs0 (1) cfcs0 (1) ? ncs5/cfcs1 ? cfcs1 (1) cfcs1 (1) ? ncs6 ? ? ? ? ncs7 ? ? ? ? nandoe ? ? ? re nandwe ? ? ? we nrd/cfoe ? oe ? ? nwr0/nwe/cfwe ? we we ? nwr1/nbs1/cfior dqm1 ior ior ? nwr3/nbs3/cfiow dqm3 iow iow ? cfce1 ? ce1 cs0 ?
177 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary note: 1. not directly connected to the compactflash slot. permit s the control of the bidirectional buffer between the ebi data bu s and the compactflash slot. 2. any pio line. cfce2 ? ce2 cs1 ? sdck clk ? ? ? sdcke cke ? ? ? ras ras ? ? ? cas cas ? ? ? sdwe we ? ? ? nwait ? wait wait ? pxx (2) ? cd1 or cd2 cd1 or cd2 ? pxx (2) ???ce pxx (2) ???rdy table 22-4. ebi pins and external devices connections (continued) signals: ebi_ pins of the interfaced device sdram compactflash (ebi only) compactflash true ide mode (ebi only) nand flash controller sdramc smc
178 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 22.4.2 connection examples figure 22-2 shows an example of connections be tween the ebi and external devices. figure 22-2. ebi connections to memory devices 22.5 product dependencies 22.5.1 i/o lines the pins used for interfacing the external bus interface may be multiplexed with the pio lines. the programmer must first program the pio controller to assign the external bus interface pins to their peripheral function. if i/o lines of the external bus interface are not used by the applica- tion, they can be used for other purposes by the pio controller. 22.6 functional description the ebi transfers data between the internal ahb bus (handled by the bus matrix) and the exter- nal memories or peripheral devices. it controls the waveforms and the parameters of the external address, data and control buses and is composed of the following elements: ? the static memory controller (smc) ? the sdram controller (sdramc) ebi d0-d31 a2-a15 ras cas sdck sdcke sdwe a0/nbs0 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 nwr1/nbs1 a1/nwr2/nbs2 nwr3/nbs3 ncs1/sdcs d0-d7 d8-d15 a16/ba0 a17/ba1 a18-a25 a10 sda10 sda10 a2-a11, a13 ncs0 ncs2 ncs3 ncs4 ncs5 a16/ba0 a17/ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 a10 sda10 a2-a11, a13 a16/ba0 a17/ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 d16-d23 d24-d31 a10 sda10 a2-a11, a13 a16/ba0 a17/ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 a10 sda10 a2-a11, a13 a16/ba0 a17/ba1 nbs0 nbs1 nbs3 nbs2 nrd/noe nwr0/nwe 128k x 8 sram 128k x 8 sram d0-d7 d0-d7 a0-a16 a0-a16 a1-a17 a1-a17 cs cs oe we d0-d7 d8-d15 oe we nrd/noe a0/nwr0/nbs0 nrd/noe nwr1/nbs1 sdwe sdwe sdwe sdwe
179 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? the ecc controller (ecc) ? a chip select assignment feature that assigns an ahb address space to the external devices ? a multiplex controller circuit that shares the pins between the different memory controllers ? programmable compactflash support logic ? programmable nand flash support logic 22.6.1 bus multiplexing the ebi offers a complete set of control signal s that share the 32-bit data lines, the address lines of up to 26 bits and the control signals through a multiplex logic operating in function of the memory area requests. multiplexing is specifically organized in or der to guarantee the maintenance of the address and output control lines at a stable state while no ex ternal access is being pe rformed. mult iplexing is also designed to respect the data float times defined in the memory controllers. furthermore, refresh cycles of the sdram are executed independently by the sdram controller without delaying the other external memory controller accesses. 22.6.2 pull-up control the ebi_csa registers in the chip configuration user interface permit enabling of on-chip pull- up resistors on the data bus lines not multiplexed with the pio controller lines. the pull-up resis- tors are enabled after reset. setting the ebi_dbpuc bit disables the pull-up resistors on the d0 to d15 lines. enabling the pull-up resistor on the d16-d31 lines can be performed by program- ming the appropriate pio controller. 22.6.3 static memory controller for information on the static memory controller, refer to the static me mory controller section. 22.6.4 sdram controller for information on the sdram contro ller, refer to the sdram section. 22.6.5 ecc controller for information on the ecc contro ller, refer to the ecc section. 22.6.6 compactflash support the external bus interface integrates circuitry that interfaces to compactflash devices. the compactflash logic is driven by the st atic memory controller (smc) on the ncs4 and/or ncs5 address space. programming the ebi_cs 4a and/or ebi_cs5a bit of the ebi_csa reg- ister in the chip configuration user interface to the appropriate value enables this logic. for details on this register, refer to the in the bus matrix section. access to an external compact- flash device is then made by accessing the address space reserved to ncs4 and/or ncs5 (i.e., between 0x5000 0000 and 0x5fff ffff for ncs4 and between 0x6000 0000 and 0x6fff ffff for ncs5). all compactflash modes (attribute memory, common memory, i/o and true ide) are sup- ported but the signals _iois16 (i/o and true ide modes) and _ata sel (true ide mode) are not handled.
180 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 22.6.6.1 i/o mode, common memory mode, attribute memory mode and true ide mode within the ncs4 and/or ncs5 address space, the current transfer address is used to distinguish i/o mode, common memory mode, attribute memory mode and true ide mode. the different modes are accessed through a specific memory mapping as illustrated on figure 22-3 . a[23:21] bits of the transfer address are used to select the desired mode as described in table 22-5 on page 180 . figure 22-3. compactflash memory mapping note: the a22 pin is used to drive the reg signal of the compactflash device (except in true ide mode). 22.6.6.2 cfce1 and cfce2 signals to cover all types of access, the smc must be al ternatively set to drive 8-bit data bus or 16-bit data bus. the odd byte access on the d[7:0] bus is only possible when the smc is configured to drive 8-bit memory devices on the corresponding ncs pin (ncs4 or ncs5). the chip select register (dbw field in the corresponding chip select register) of the ncs4 and/or ncs5 address space must be set as shown in table 22-6 to enable the required access type. nbs1 and nbs0 are the byte selection signals from smc and are available when the smc is set in byte select mode on the corresponding chip select. table 22-5. compactflash mode selection a[23:21] mode base address 000 attribute memory 010 common memory 100 i/o mode 110 true ide mode 111 alternate true ide mode cf address space attribute memory mode space common memory mode space i/o mode space true ide mode space true ide alternate mode space offset 0x00e0 0000 offset 0x00c0 0000 offset 0x0080 0000 offset 0x0040 0000 offset 0x0000 0000
181 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary the cfce1 and cfce2 waveforms are identical to the corresponding ncsx waveform. for details on these waveforms and timings, refer to the static memory controller section. 22.6.6.3 read/write signals in i/o mode and true ide mode, the compactflash logic drives the read and write command signals of the smc on cfior and cfiow signals, while the cfoe and cfwe signals are deac- tivated. likewise, in common memory mode and attribute memory mode, the smc signals are driven on the cfoe and cfwe signals, while the cfior and cfiow are deactivated. figure 22-4 on page 182 demonstrates a schematic representation of this logic. attribute memory mode, common memory mode and i/o mode are supported by setting the address setup and hold time on the ncs4 (and/or ncs5) chip select to the appropriate values. table 22-6. cfce1 and cfce2 truth table mode cfce2 cfce1 dbw comment smc access mode attribute memory nbs1 nbs0 16 bits access to even byte on d[7:0] byte select common memory nbs1 nbs0 16bits access to even byte on d[7:0] access to odd byte on d[15:8] byte select 1 0 8 bits access to odd byte on d[7:0] i/o mode nbs1 nbs0 16 bits access to even byte on d[7:0] access to odd byte on d[15:8] byte select 1 0 8 bits access to odd byte on d[7:0] true ide mode task file 1 0 8 bits access to even byte on d[7:0] access to odd byte on d[7:0] data register 1 0 16 bits access to even byte on d[7:0] access to odd byte on d[15:8] byte select alternate true ide mode control register alternate status read 01 don?t care access to even byte on d[7:0] don?t care drive address 0 1 8 bits access to odd byte on d[7:0] standby mode or address space is not assigned to cf 11? ? ?
182 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 22-4. compactflash read/write control signals 22.6.6.4 multiplexing of compactflash signals on ebi pins table 22-8 on page 182 and table 22-9 on page 183 illustrate the multiple xing of the compact- flash logic signals with other ebi signals on the ebi pins. the ebi pins in table 22-8 are strictly dedicated to the compactflash interface as so on as the ebi_cs4a and/or ebi_cs5a field of the ebi_csa register in the chip configuration user interface is set. these pins must not be used to drive any other memory devices. the ebi pins in table 22-9 on page 183 remain shared between all memory areas when the cor- responding compactflash interface is enabled (ebi_cs4a = 1 and/or ebi_cs5a = 1). smc nrd_noe nwr0_nwe a23 cfior cfiow cfoe cfwe 1 1 compactflash logic external bus interface 1 1 1 0 a22 1 0 1 0 1 0 table 22-7. compactflash mode selection mode base address cfoe cfwe cfior cfiow attribute memory common memory nrd nwr0_nwe 1 1 i/o mode 1 1 nrd nwr0_nwe true ide mode 0 1 nrd nwr0_nwe table 22-8. dedicated compactflash interface multiplexing pins compactflash signals ebi signals cs4a = 1 cs5a = 1 cs4a = 0 cs5a = 0 ncs4/cfcs0 cfcs0 ncs4 ncs5/cfcs1 cfcs1 ncs5
183 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 22.6.6.5 application example figure 22-5 on page 184 illustrates an example of a comp actflash application. cfcs0 and cfrnw signals are not directly connected to the compactflash slot 0, but do control the direc- tion and the output enable of the buffers between the ebi and the compactflash device. the timing of the cfcs0 signal is identical to the ncs4 signal. moreover, the cfrnw signal remains valid throughout the transfer, as does the address bus. the compactflash _wait sig- nal is connected to the nwait input of the static memory controller. for details on these waveforms and timings, refer to the static memory controller section. table 22-9. shared compactflash interface mu ltiplexing pins access to compactflash device access to other ebi devices compactflash sign als ebi signals nrd/cfoe cfoe nrd nwr0/nwe/cfwe cfwe nwr0/nwe nwr1/nbs1/cfior cfior nwr1/nbs1 nwr3/nbs3/cfiow cfiow nwr3/nbs3 a25/cfrnw cfrnw a25
184 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 22-5. compactflash application example 22.6.7 nand flash support external bus interface integrate circuitr y that interfaces to nand flash devices. 22.6.7.1 external bus interface the nand flash logic is driven by the static memory controller on the ncs3 address space. programming the ebi_cs3a field in the ebi_csa register in the chip configuration user inter- face to the appropriate value enables the nand flash logic. for details on this register, refer to the bus matrix section. access to an external nand flash device is then made by accessing the address space reserved to ncs3 (i.e., between 0x4000 0000 and 0x4fff ffff). the nand flash logic drives the read and write command signals of the smc on the nandoe and nandwe signals when the ncs3 signal is active. nandoe and nandwe are invalidated as soon as the transfer address fails to lie in the ncs3 address space. see figure ?nand flash signal multiplexing on ebi pins? on page 185 for more information. for details on these wave- forms, refer to the static memory controller section. compactflash connector ebi d[15:0] /oe dir _cd1 _cd2 /oe d[15:0] a25/cfrnw ncs4/cfcs0 cd (pio) a[10:0] a22/reg noe/cfoe a[10:0] _reg _oe _we _iord _iowr _ce1 _ce2 nwe/cfwe nwr1/cfior nwr3/cfiow cfce1 cfce2 _wait nwait
185 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 22-6. nand flash signal multiplexing on ebi pins 22.6.7.2 nand flash signals the address latch enable and command latch enable signals on the nand flash device are driven by address bits a22 and a21 of the ebi a ddress bus. the user should note that any bit on the ebi address bus can also be used for this purpose. the command, address or data words on the data bus of the nand flash device are di stinguished by using their address within the ncsx address space. the chip enable (ce) signal of the device and the ready/busy (r/b) sig- nals are connected to pio lines. the ce signal then remains asserted even when ncsx is not selected, preventing the device from returning to standby mode. smc nrd_noe nwr0_nwe nandoe nandwe nand flash logic ncsx nandwe nandoe
186 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 22-7. nand flash application example note: the external bus interface is also able to support 16-bit devices. d[7:0] ale nandwe nandoe noe nwe a[22:21] cle ad[7:0] pio r/b ebi ce nand flash pio ncsx/nandcs not connected
187 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 22.7 implementation examples all the hardware configurations are given for illustration only. th e user should refer to the mem- ory manufacturer web site to check device availability." 22.7.1 16-bit sdram figure 22-8. hardware configuration 22.7.1.1 software configuration the following configuration has to be performed: ? assign the ebi cs1 to the sdram controller by setting the bit ebi_cs1a in the ebi chip select assignment register locate d in the bus matrix memory space. ? initialize the sdram controller depending on the sdram device and system bus frequency. the data bus width is to be programmed to 16 bits. the sdram initialization sequence is described in the ?sdram device initia lisation? part of the sdram controller. d13 d12 d8 d7 d3 d11 d2 d14 d4 d0 ras d1 d10 cas sda10 sdck d9 sdwe sdcke d5 d15 d6 a4 a9 a14 a5 a2 a6 a3 ba0 a10 a13 a8 ba1 a7 a11 a0 ras cas sda10 sdwe sdcke sdck cfior_nbs1_nwr1 sdcs_ncs1 ba0 ba1 d[0..15] a[0..14] 3v3 (not used a12) c6 100nf c6 100nf c4 100nf c4 100nf u1 u1 a0 23 a1 24 a2 25 a3 26 a4 29 a5 30 a6 31 a7 32 a8 33 a9 34 a10 22 ba0 20 a12 36 dq0 2 dq1 4 dq2 5 dq3 7 dq4 8 dq5 10 dq6 11 dq7 13 dq8 42 dq9 44 dq10 45 dq11 47 dq12 48 dq13 50 dq14 51 dq15 53 vdd 1 vss 28 vss 41 vddq 3 vdd 27 n.c 40 clk 38 cke 37 dqml 15 dqmh 39 cas 17 ras 18 we 16 cs 19 vddq 9 vddq 43 vddq 49 vssq 6 vssq 12 vssq 46 vssq 52 vdd 14 vss 54 a11 35 ba1 21 c2 100nf c2 100nf c1 100nf c1 100nf c5 100nf c5 100nf c3 100nf c3 100nf c7 100nf c7 100nf
188 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 22.7.2 32-bit sdram 22.7.2.1 hardware configuration 22.7.2.2 software configuration the following configuration has to be performed: ? assign the ebi cs1 to the sdram controller by setting the bit ebi_cs1a in the ebi chip select assignment register locate d in the bus matrix memory space. ? initialize the sdram controller depending on the sdram device and system bus frequency. the data bus width is to be programmed to 32 bits. the data lines d[16..31] are multiplexed with pio lines and thus the dedicated pios must be programmed in peripheral mode in the pio controller. the sdram initialization sequence is described in the ?sdram device initia lisation? part of the sdram controller. cas sdcke sdck ras sdwe sda10 d13 d18 d12 d22 d8 d7 d3 d28 d11 d26 d21 d2 d14 d4 d24 d0 d23 ras d27 d1 d19 d10 d31 d17 cas sda10 d25 d29 d16 sdck d9 d20 sdwe sdcke d5 d30 d15 d6 a5 ba0 a2 a11 a7 a4 a9 a14 a8 a1 a5 a2 ba1 a13 a6 a3 a3 a10 ba0 a10 a13 a8 ba1 a6 a4 a14 a9 a7 a11 a0 ras cas sda10 sdwe sdcke sdck cfiow_nbs3_nwr3 cfior_nbs1_nwr1 sdcs_ncs1 ba0 ba1 d[0..31] a[0..14] 3v3 3v3 (not used a12) c5 100nf c5 100nf c12 100nf c12 100nf c14 100nf c14 100nf c3 100nf c3 100nf c10 100nf c10 100nf c8 100nf c8 100nf c7 100nf c7 100nf c6 100nf c6 100nf c11 100nf c11 100nf c13 100nf c13 100nf c4 100nf c4 100nf c2 100nf c2 100nf c9 100nf c9 100nf u1 u1 a0 23 a1 24 a2 25 a3 26 a4 29 a5 30 a6 31 a7 32 a8 33 a9 34 a10 22 ba0 20 a12 36 dq0 2 dq1 4 dq2 5 dq3 7 dq4 8 dq5 10 dq6 11 dq7 13 dq8 42 dq9 44 dq10 45 dq11 47 dq12 48 dq13 50 dq14 51 dq15 53 vdd 1 vss 28 vss 41 vddq 3 vdd 27 n.c 40 clk 38 cke 37 dqml 15 dqmh 39 cas 17 ras 18 we 16 cs 19 vddq 9 vddq 43 vddq 49 vssq 6 vssq 12 vssq 46 vssq 52 vdd 14 vss 54 a11 35 ba1 21 u2 u2 a0 23 a1 24 a2 25 a3 26 a4 29 a5 30 a6 31 a7 32 a8 33 a9 34 a10 22 ba0 20 a12 36 dq0 2 dq1 4 dq2 5 dq3 7 dq4 8 dq5 10 dq6 11 dq7 13 dq8 42 dq9 44 dq10 45 dq11 47 dq12 48 dq13 50 dq14 51 dq15 53 vdd 1 vss 28 vss 41 vddq 3 vdd 27 n.c 40 clk 38 cke 37 dqml 15 dqmh 39 cas 17 ras 18 we 16 cs 19 vddq 9 vddq 43 vddq 49 vssq 6 vssq 12 vssq 46 vssq 52 vdd 14 vss 54 a11 35 ba1 21 c1 100nf c1 100nf
189 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 22.7.3 8-bit nandflash hardware configuration 22.7.3.1 software configuration the following configuration has to be performed: ? assign the ebi cs3 to the nandflash by setting the bit ebi_cs3a in the ebi chip select assignment register located in the bus matrix memory space ? reserve a21 / a22 for ale / cle functions. address and command latches are controlled respectively by setting to 1 the address bit a21 and a22 during accesses. ? configure a pio line as an input to manage the ready/busy signal. ? configure static memory controller cs3 setu p, pulse, cycle and mode accordingly to nandflash timings, the data bus width and the system bus frequency. d6 d0 d3 d4 d2 d1 d5 d7 nandoe nandwe (any pio) (any pio) ale cle d[0..7] 3v3 3v3 c1 100nf c1 100nf u1 u1 we 18 n.c 6 vcc 37 ce 9 re 8 n.c 20 wp 19 n.c 5 n.c 1 n.c 2 n.c 3 n.c 4 n.c 21 n.c 22 n.c 23 n.c 24 r/b 7 n.c 26 n.c 27 n.c 28 i/o0 29 n.c 34 n.c 35 vss 36 pre 38 n.c 39 vcc 12 vss 13 ale 17 n.c 11 n.c 10 n.c 14 n.c 15 cle 16 n.c 25 n.c 33 i/o1 30 i/o3 32 i/o2 31 n.c 47 n.c 46 n.c 45 i/o7 44 i/o6 43 i/o5 42 i/o4 41 n.c 40 n.c 48 r1 10k r1 10k r2 10k r2 10k c2 100nf c2 100nf
190 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 22.7.4 16-bit nandflash hardware configuration 22.7.4.1 software configuration the software configuration is the same as for an 8-bit nandflash except the data bus width pro- grammed in the mode register of the static memory controller. d6 d0 d3 d4 d2 d1 d5 d7 d14 d8 d11 d12 d10 d9 d13 d15 nandoe nandwe (any pio) ale cle d[0..15] (any pio) 3v3 3v3 c1 100nf c1 100nf u1 u1 we 18 n.c 6 vcc 37 ce 9 re 8 n.c 20 wp 19 n.c 5 n.c 1 n.c 2 n.c 3 n.c 4 n.c 21 n.c 22 n.c 23 n.c 24 r/b 7 i/o0 26 i/o8 27 i/o1 28 i/o9 29 n.c 34 n.c 35 n.c 36 pre 38 n.c 39 vcc 12 vss 13 ale 17 n.c 11 n.c 10 n.c 14 n.c 15 cle 16 vss 25 i/o11 33 i/o2 30 i/o3 32 i/o10 31 i/o15 47 i/o7 46 i/o14 45 i/o6 44 i/o13 43 i/o5 42 i/o12 41 i/o4 40 vss 48 r1 10k r1 10k r2 10k r2 10k c2 100nf c2 100nf
191 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 22.7.5 nor flash on ncs0 hardware configuration 22.7.5.1 software configuration the default configuration for the static memory controller, byte select mode, 16-bit data bus, read/write controlled by chip select, allows boot on 16-bit non-volatile memory at slow clock. for another configuration, configure the static memory controller cs0 setup, pulse, cycle and mode depending on flash timings and system bus frequency. a21 a22 a1 a2 a3 a4 a5 a6 a7 a8 a15 a9 a12 a13 a11 a10 a14 a16 d6 d0 d3 d4 d2 d1 d5 d7 d14 d8 d11 d12 d10 d9 d13 d15 a17 a20 a18 a19 d[0..15] a[1..22] nrst nwe ncs0 nrd 3v3 3v3 c1 100nf c1 100nf u1 u1 a0 25 a1 24 a2 23 a3 22 a4 21 a5 20 a6 19 a7 18 a8 8 a9 7 a10 6 a11 5 a12 4 a13 3 a14 2 a15 1 a16 48 a17 17 a18 16 a21 9 a20 10 a19 15 we 11 reset 12 wp 14 oe 28 ce 26 vpp 13 dq0 29 dq1 31 dq2 33 dq3 35 dq4 38 dq5 40 dq6 42 dq7 44 dq8 30 dq9 32 dq10 34 dq11 36 dq12 39 dq13 41 dq14 43 dq15 45 vccq 47 vss 27 vss 46 vcc 37 c2 100nf c2 100nf
192 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 22.7.6 compact flash 22.7.6.1 hardware configuration d15 d14 d13 d12 d10 d11 d9 d8 d7 d6 d5 d4 d2 d1 d0 d3 a10 a9 a8 a7 a3 a4 a5 a6 a0 a2 a1 cd1 cd2 cd2 cd1 we oe iowr iord ce2 ce1 reg wait# reset cf_d3 cf_d2 cf_d1 cf_d0 cf_d7 cf_d6 cf_d5 cf_d4 cf_d11 cf_d10 cf_d9 cf_d8 cf_d15 cf_d14 cf_d13 cf_d12 cf_a10 cf_a9 cf_a8 cf_a7 cf_a6 cf_a5 cf_a4 cf_a3 cf_a2 cf_a1 cf_a0 reg we oe iowr iord cf_a10 cf_a9 cf_a8 cf_a7 cf_a6 cf_a5 cf_a4 cf_a3 cf_a2 cf_a1 cf_a0 cf_d4 cf_d13 cf_d15 cf_d14 cf_d12 cf_d11 cf_d10 cf_d9 cf_d8 cf_d7 cf_d6 cf_d5 cf_d3 cf_d2 cf_d1 cf_d0 ce2 ce1 reset rdy/bsy rdy/bsy wait# cfwe (any pio) a25/cfrnw d[0..15] a[0..10] cfcsx a22/reg cfoe cfiow cfior nwait (any pio) cfce2 cfce1 (any pio) 3v3 3v3 3v3 3v3 3v3 3v3 cfirq cfrst memory & i/o mode (cfcs0 or cfcs1) mn2a sn74alvc32 mn2a sn74alvc32 3 1 2 c2 100nf c2 100nf mn1d 74alvch32245 mn1d 74alvch32245 4dir t3 4oe t4 4a1 n5 4a2 n6 4a3 p5 4a4 p6 4a5 r5 4a6 r6 4a7 t6 4a8 t5 4b1 n2 4b2 n1 4b3 p2 4b4 p1 4b5 r2 4b6 r1 4b7 t1 4b8 t2 mn1c 74alvch32245 mn1c 74alvch32245 3dir j3 3oe j4 3a1 j5 3a2 j6 3a3 k5 3a4 k6 3a5 l5 3a6 l6 3a7 m5 3a8 m6 3b1 j2 3b2 j1 3b3 k2 3b4 k1 3b5 l2 3b6 l1 3b7 m2 3b8 m1 r2 47k r2 47k mn3b sn74alvc125 mn3b sn74alvc125 6 4 5 r1 47k r1 47k mn1b 74alvch32245 mn1b 74alvch32245 2dir h3 2oe h4 2a1 e5 2a2 e6 2a3 f5 2a4 f6 2a5 g5 2a6 g6 2a7 h5 2a8 h6 2b1 e2 2b2 e1 2b3 f2 2b4 f1 2b5 g2 2b6 g1 2b7 h2 2b8 h1 vcc gnd mn4 sn74lvc1g125-q1 vcc gnd mn4 sn74lvc1g125-q1 5 1 2 3 4 mn3a sn74alvc125 mn3a sn74alvc125 3 1 2 r3 10k r3 10k mn2b sn74alvc32 mn2b sn74alvc32 6 4 5 mn3c sn74alvc125 mn3c sn74alvc125 8 9 10 r4 10k r4 10k c1 100nf c1 100nf j1 n7e50-7516vy-20 j1 n7e50-7516vy-20 gnd 1 d3 2 d4 3 d5 4 d6 5 d7 6 ce1# 7 a10 8 oe# 9 a9 10 a8 11 a7 12 vcc 13 a6 14 a5 15 a4 16 a3 17 a2 18 a1 19 a0 20 d0 21 d1 22 d2 23 wp 24 cd2# 25 cd1# 26 d11 27 d12 28 d13 29 d14 30 d15 31 ce2# 32 vs1# 33 iord# 34 iowr# 35 we# 36 rdy/bsy 37 vcc 38 csel# 39 vs2# 40 reset 41 wait# 42 inpack# 43 reg# 44 bvd2 45 bvd1 46 d8 47 d9 48 d10 49 gnd 50 mn1a 74alvch32245 mn1a 74alvch32245 1a1 a5 1a2 a6 1a3 b5 1a4 b6 1a5 c5 1a6 c6 1a7 d5 1a8 d6 1dir a3 1oe a4 1b1 a2 1b2 a1 1b3 b2 1b4 b1 1b5 c2 1b6 c1 1b7 d2 1b8 d1 mn3d sn74alvc125 mn3d sn74alvc125 11 12 13
193 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 22.7.6.2 software configuration the following configuration has to be performed: ? assign the ebi cs4 and/or ebi_cs5 to the compactflash slot 0 or/and slot 1 by setting the bit ebi_cs4a or/and ebi_ cs5a in the ebi chip select assignment register located in the bus matrix memory space. ? the address line a23 is to select i/o (a23=1) or memory mode (a23=0) and the address line a22 for reg function. ? a23, cfrnw, cfs0, cfcs1, cfce1 and cfce2 signals are multiplexed with pio lines and thus the dedicated pios must be programmed in peripheral mode in the pio controller. ? configure a pio line as an output for cfrst and two others as an input for cfirq and card detect functions respectively. ? configure smc cs4 and/or smc_cs5 (for slot 0 or 1) setup, pulse, cycle and mode according to compact flash timings and system bus frequency.
194 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 22.7.7 compact flash true ide 22.7.7.1 hardware configuration d15 d14 d13 d12 d10 d11 d9 d8 d7 d6 d5 d4 d2 d1 d0 d3 a10 a9 a8 a7 a3 a4 a5 a6 a0 a2 a1 cd1 cd2 cf_d3 cf_d2 cf_d1 cf_d0 cf_d7 cf_d6 cf_d5 cf_d4 cf_d11 cf_d10 cf_d9 cf_d8 cf_d15 cf_d14 cf_d13 cf_d12 reset# cf_a10 cf_a9 cf_a8 cf_a7 cf_a6 cf_a5 cf_a4 cf_a3 cf_a2 cf_a1 cf_a0 cd2 cd1 iowr iord ce2 ce1 reg we oe iowr iord iordy cf_a0 cf_a2 cf_a1 cf_d4 cf_d13 cf_d15 cf_d14 cf_d12 cf_d11 cf_d10 cf_d9 cf_d8 cf_d7 cf_d6 cf_d5 cf_d3 cf_d2 cf_d1 cf_d0 ce2 ce1 reset# intrq iordy intrq cfwe (any pio) a25/cfrnw d[0..15] a[0..10] cfcsx a22/reg cfoe cfiow cfior nwait (any pio) cfce2 cfce1 (any pio) 3v3 3v3 3v3 3v3 3v3 3v3 3v3 cfirq cfrst true ide mode (cfcs0 or cfcs1) c2 100nf c2 100nf mn1d 74alvch32245 mn1d 74alvch32245 4dir t3 4oe t4 4a1 n5 4a2 n6 4a3 p5 4a4 p6 4a5 r5 4a6 r6 4a7 t6 4a8 t5 4b1 n2 4b2 n1 4b3 p2 4b4 p1 4b5 r2 4b6 r1 4b7 t1 4b8 t2 vcc gnd mn4 sn74lvc1g125-q1 vcc gnd mn4 sn74lvc1g125-q1 5 1 2 3 4 mn3c sn74alvc125 mn3c sn74alvc125 8 9 10 r4 10k r4 10k mn1c 74alvch32245 mn1c 74alvch32245 3dir j3 3oe j4 3a1 j5 3a2 j6 3a3 k5 3a4 k6 3a5 l5 3a6 l6 3a7 m5 3a8 m6 3b1 j2 3b2 j1 3b3 k2 3b4 k1 3b5 l2 3b6 l1 3b7 m2 3b8 m1 r3 10k r3 10k j1 n7e50-7516vy-20 j1 n7e50-7516vy-20 gnd 1 d3 2 d4 3 d5 4 d6 5 d7 6 cs0# 7 a10 8 ata sel# 9 a9 10 a8 11 a7 12 vcc 13 a6 14 a5 15 a4 16 a3 17 a2 18 a1 19 a0 20 d0 21 d1 22 d2 23 iois16# 24 cd2# 25 cd1# 26 d11 27 d12 28 d13 29 d14 30 d15 31 cs1# 32 vs1# 33 iord# 34 iowr# 35 we# 36 intrq 37 vcc 38 csel# 39 vs2# 40 reset# 41 iordy 42 inpack# 43 reg# 44 dasp# 45 pdiag# 46 d8 47 d9 48 d10 49 gnd 50 mn1a 74alvch32245 mn1a 74alvch32245 1a1 a5 1a2 a6 1a3 b5 1a4 b6 1a5 c5 1a6 c6 1a7 d5 1a8 d6 1dir a3 1oe a4 1b1 a2 1b2 a1 1b3 b2 1b4 b1 1b5 c2 1b6 c1 1b7 d2 1b8 d1 mn1b 74alvch32245 mn1b 74alvch32245 2dir h3 2oe h4 2a1 e5 2a2 e6 2a3 f5 2a4 f6 2a5 g5 2a6 g6 2a7 h5 2a8 h6 2b1 e2 2b2 e1 2b3 f2 2b4 f1 2b5 g2 2b6 g1 2b7 h2 2b8 h1 mn2a sn74alvc32 mn2a sn74alvc32 3 1 2 c1 100nf c1 100nf r2 47k r2 47k r1 47k r1 47k mn3b sn74alvc125 mn3b sn74alvc125 6 4 5 mn3d sn74alvc125 mn3d sn74alvc125 11 12 13 mn2b sn74alvc32 mn2b sn74alvc32 6 4 5 mn3a sn74alvc125 mn3a sn74alvc125 3 1 2
195 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 22.7.7.2 software configuration the following configuration has to be performed: ? assign the ebi cs4 and/or ebi_cs5 to the compactflash slot 0 or/and slot 1 by setting the bit ebi_cs4a or/and ebi_ cs5a in the ebi chip select assignment register located in the bus matrix memory space. ? the address line a21 is to select alternate true ide (a21=1) or true ide (a21=0) modes. ? cfrnw, cfs0, cfcs1, cfce1 and cfce2 signals are multiplexed with pio lines and thus the dedicated pios must be programmed in peripheral mode in the pio controller. ? configure a pio line as an output for cfrst and two others as an input for cfirq and card detect functions respectively. ? configure smc cs4 and/or smc_cs5 (for slot 0 or 1) setup, pulse, cycle and mode according to compact flash timings and system bus frequency.
196 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary
197 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23. static memory controller (smc) 23.1 description the static memory controller (smc) generates the signals that control the access to the exter- nal memory devices or peripheral devices. it has 8 chip selects and a 26-bit address bus. the 32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. separate read and write control signals allow for direct memory and peripheral interfacing. read and write signal waveforms are fully parametrizable. the smc can manage wait requests from external devices to extend the current access. the smc is provided with an automatic slow clock mode. in slow clock mode, it switches from user- programmed waveforms to slow-rate specific waveforms on read and write signals. the smc supports asynchronous burst read in page mode access for page size up to 32 bytes. 23.2 i/o lines description 23.3 multiplexed signals table 23-1. i/o line description name description type active level ncs[7:0] static memory controller chip select lines output low nrd read signal output low nwr0/nwe write 0/write enable signal output low a0/nbs0 address bit 0/byte 0 select signal output low nwr1/nbs1 write 1/byte 1 select signal output low a1/nwr2/nbs2 address bit 1/write 2/byte 2 select signal output low nwr3/nbs3 write 3/byte 3 select signal output low a[25:2] address bus output d[31:0] data bus i/o nwait external wait signal input low table 23-2. static memory controller (smc) multiplexed signals multiplexed signal s related function nwr0 nwe byte-write or byte-select access, see ?byte write or byte select access? on page 199 a0 nbs0 8-bit or 16-/32-bit data bus, see ?data bus width? on page 199 nwr1 nbs1 byte-write or byte-select access see ?byte write or byte sele ct access? on page 199 a1 nwr2 nbs2 8-/16-bit or 32-bit data bus, see ?data bus width? on page 199 . byte-write or byte-select access, see ?byte write or byte select access? on page 199 nwr3 nbs3 byte-write or byte-select access see ?byte write or byte sele ct access? on page 199
198 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.4 application example 23.4.1 hardware interface figure 23-1. smc connections to st atic memory devices 23.5 product dependencies 23.5.1 i/o lines the pins used for interfacing the static memory controller may be multiplexed with the pio lines. the programmer must first program the pio controller to assign the static memory con- troller pins to their peripheral function. if i/o lines of the smc are not used by the application, they can be used for other purposes by the pio controller. static memory controller d0-d31 a2 - a25 a0/nbs0 nwr0/nwe nwr1/nbs1 a1/nwr2/nbs2 nwr3/nbs3 128k x 8 sram d0 - d7 a0 - a16 oe we cs d0 - d7 d8-d15 a2 - a18 128k x 8 sram d0-d7 cs d16 - d23 d24-d31 128k x 8 sram d0-d7 cs nwr1/nbs1 nwr3/nbs3 nrd nwr0/nwe 128k x 8 sram d0 - d7 oe we cs nrd a1/nwr2/nbs2 ncs0 ncs1 ncs2 ncs3 ncs4 ncs5 ncs6 ncs7 a2 - a18 a0 - a16 nrd oe we oe we nrd a2 - a18 a0 - a16 a2 - a18 a0 - a16
199 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.6 external memory mapping the smc provides up to 26 address lines, a[25:0]. this allows each chip select line to address up to 64 mbytes of memory. if the physical memory device co nnected on one chip select is smaller than 64 mbytes, it wraps around and appears to be repeated within this space. the smc correctly handles any valid access to the memory devi ce within the page (see figure 23-2 ). a[25:0] is only significant for 8-bit memory, a[25:1 ] is used for 16-bit memory, a[25:2] is used for 32-bit memory. figure 23-2. memory connections for eight external devices 23.7 connection to external devices 23.7.1 data bus width a data bus width of 8, 16, or 32 bits can be selected for each chip select. this option is con- trolled by the field dbw in smc_mode (mode register) for the corresponding chip select. figure 23-3 shows how to connect a 512k x 8-bit memory on ncs2. figure 23-4 shows how to connect a 512k x 16-bit memory on ncs2. figure 23-5 shows two 16-bit memories connected as a single 32-bit memory 23.7.2 byte write or byte select access each chip select with a 16-bit or 32-bit data bus can operate with one of two different types of write access: byte write or byte select access . this is controlled by the bat field of the smc_mode register for the corresponding chip select. nrd nwe a[25:0] d[31:0] 8 or 16 or 32 memory enable memory enable memory enable memory enable memory enable memory enable memory enable memory enable output enable write enable a[25:0] d[31:0] or d[15:0] or d[7:0] ncs3 ncs0 ncs1 ncs2 ncs7 ncs4 ncs5 ncs6 ncs[0] - ncs[7] smc
200 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 23-3. memory connection for an 8-bit data bus figure 23-4. memory connection for a 16-bit data bus figure 23-5. memory connection for a 32-bit data bus smc a0 nwe nrd ncs[2] a0 write enable output enable memory enable d[7:0] d[7:0] a[18:2] a[18:2] a1 a1 smc nbs0 nwe nrd ncs[2] low byte enable write enable output enable memory enable nbs1 high byte enable d[15:0] d[15:0] a[19:2] a[18:1] a[0] a1 d[31:16] smc nbs0 nwe nrd ncs[2] nbs1 d[15:0] a[20:2] d[31:16] nbs2 nbs3 byte 0 enable write enable output enable memory enable byte 1 enable d[15:0] a[18:0] byte 2 enable byte 3 enable
201 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.7.2.1 byte write access byte write access supports one byte write signal per byte of the data bus and a single read signal. note that the smc does not allow boot in byte write access mode. ? for 16-bit devices: the smc provides nwr0 and nwr1 write signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. one single read signal (nrd) is provided. byte write access is used to connect 2 x 8-bit devices as a 16-bit memory. ? for 32-bit devices: nwr0, nwr1, nwr2 and nwr3, are the write signals of byte0 (lower byte), byte1, byte2 and byte 3 (upper byte) respectively. one single read signal (nrd) is provided. byte write access is used to connect 4 x 8-bit devices as a 32-bit memory. byte write option is illustrated on figure 23-6 . 23.7.2.2 byte select access in this mode, read/write operations can be enabled/disabled at a byte level. one byte-select line per byte of the data bus is provided. one nrd and one nwe signal control read and write. ? for 16-bit devices: the smc provides nbs0 and nbs1 selection signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. byte select access is used to connect one 16-bit device. ? for 32-bit devices: nbs0, nbs1, nbs2 and nbs3, are the selection signals of byte0 (lower byte), byte1, byte2 and byte 3 (upper byte) respectively. byte select access is used to connect two 16-bit devices. figure 23-7 shows how to connect two 16-bit devices on a 32-bit data bus in byte select access mode, on ncs3 (bat = byte select access).
202 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 23-6. connection of 2 x 8-bit devices on a 16-bit bus: byte write option 23.7.2.3 signal multiplexing depending on the bat, only the write signals or the byte select signals are used. to save ios at the external bus interface, control signals at the smc interface are multiplexed. table 23-3 shows signal multiplexing depending on the data bus width and the byte access type. for 32-bit devices, bits a0 and a1 are unused. for 16-bit devices, bit a0 of address is unused. when byte select option is selected, nwr1 to nwr3 are unused. when byte write option is selected, nbs0 to nbs3 are unused. smc a1 nwr0 nrd ncs[3] write enable read enable memory enable nwr1 write enable read enable memory enable d[7:0] d[7:0] d[15:8] d[15:8] a[24:2] a[23:1] a[23:1] a[0] a[0]
203 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 23-7. connection of 2x16-bit data bus on a 32-bit data bus (byte select option) smc nwe nrd ncs[3] write enable read enable memory enable nbs0 d[15:0] d[15:0] d[31:16] a[25:2] a[23:0] write enable read enable memory enable d[31:16] a[23:0] low byte enable high byte enable low byte enable high byte enable nbs1 nbs2 nbs3 table 23-3. smc multiplexed signal translation signal name 32-bit bus 16-bit bus 8-bit bus device type 1x32-bit 2x16-bit 4 x 8- bit 1x16-bit 2 x 8-bit 1 x 8-bit byte access type (bat) byte select byte select byte write byte select byte write nbs0_a0 nbs0 nbs0 nbs0 a0 nwe_nwr0 nwe nwe nwr0 nwe nwr0 nwe nbs1_nwr1 nbs1 nbs1 nwr1 nbs1 nwr1 nbs2_nwr2_a1 nbs2 nbs2 nwr2 a1 a1 a1 nbs3_nwr3 nbs3 nbs3 nwr3
204 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.8 standard read and write protocols in the following sections, the byte access type is not considered. byte select lines (nbs0 to nbs3) always have the same timing as the a ad dress bus. nwe represents either the nwe sig- nal in byte select access type or one of the byte write lines (nwr0 to nwr3) in byte write access type. nwr0 to nwr3 have the same ti mings and protocol as nwe. in the same way, ncs represents one of the ncs[0..7] chip select lines. 23.8.1 read waveforms the read cycle is shown on figure 23-8 . the read cycle starts with the address setting on the memory address bus, i.e.: {a[25:2], a1, a0} for 8-bit devices {a[25:2], a1} for 16-bit devices a[25:2] for 32-bit devices. figure 23-8. standard read cycle 23.8.1.1 nrd waveform the nrd signal is characterized by a setu p timing, a pulse width and a hold timing. 1. nrd_setup: the nrd setup time is defined as the setup of address before the nrd falling edge; 2. nrd_pulse: the nrd pulse length is the time between nrd falling edge and nrd rising edge; 3. nrd_hold: the nrd hold time is defined as the hold time of a ddress after the nrd rising edge. a[25:2] nbs0,nbs1, nbs2,nbs3, a0, a1 ncs nrd_setup nrd_pulse nrd_hold mck nrd d[31:0] ncs_rd_setup ncs_rd_pulse ncs_rd_hold nrd_cycle
205 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.8.1.2 ncs waveform similarly, the ncs signal can be divided into a setup time, pulse length and hold time: 1. ncs_rd_setup: the ncs setup time is defined as the setup time of address before the ncs falling edge. 2. ncs_rd_pulse: the ncs pulse length is the time between ncs falling edge and ncs rising edge; 3. ncs_rd_hold: the ncs hold time is defined as the hold time of address after the ncs rising edge. 23.8.1.3 read cycle the nrd_cycle time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change. the total read cycle time is equal to: nrd_cycle = nrd_setup + nrd_pulse + nrd_hold = ncs_rd_setup + ncs_rd_pulse + ncs_rd_hold all nrd and ncs timings are defined separately for each chip select as an integer number of master clock cycles. to ensure that the nrd and ncs timings are coherent, user must define the total read cycle instead of the hold timing. nrd_cycle implicitly defines the nrd hold time and ncs hold time as: nrd_hold = nrd_cycle - nrd setup - nrd pulse ncs_rd_hold = nrd_cycle - ncs_rd_setup - ncs_rd_pulse 23.8.1.4 null delay setup and hold if null setup and hold parame ters are programmed for nrd and/or ncs, nrd and ncs remain active continuously in case of consecutive read cycles in the same memory (see figure 23-9 ).
206 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 23-9. no setup, no hold on nrd and ncs read signals 23.8.1.5 null pulse programming null pulse is not permitted. pulse must be at least set to 1. a null value leads to unpredictable behavior. 23.8.2 read mode as ncs and nrd waveforms are defined independently of one other, the smc needs to know when the read data is available on the data bus. the smc does not compare ncs and nrd tim- ings to know which signal rises first. the r ead_mode parameter in the smc_mode register of the corresponding chip select indicates wh ich signal of nrd and ncs controls the read operation. 23.8.2.1 read is controlled by nrd (read_mode = 1): figure 23-10 shows the waveforms of a read operation of a typical asynchronous ram. the read data is available t pacc after the falling edge of nrd, and turn s to ?z? after the rising edge of nrd. in this case, the read_mode must be set to 1 (read is controlled by nrd), to indicate that data is available with the rising edge of nrd. the smc samples the read data internally on the rising edge of master clock that generates the rising edge of nrd, whatever the pro- grammed waveform of ncs may be. mck nrd_pulse ncs_rd_pulse nrd_cycle nrd_pulse nrd_pulse ncs_rd_pulse ncs_rd_pulse nrd_cycle nrd_cycle a[25:2] nbs0,nbs1, nbs2,nbs3, a0, a1 ncs nrd d[31:0]
207 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 23-10. read_mode = 1: data is sampled by smc before the rising edge of nrd 23.8.2.2 read is controlled by ncs (read_mode = 0) figure 23-11 shows the typical read cycle of an lcd module. the read data is valid t pacc after the falling edge of the ncs signal and remains va lid until the rising edge of ncs. data must be sampled when ncs is raised. in that case, the read_mode must be set to 0 (read is controlled by ncs): the smc internally samples the data on the rising edge of master clock that generates the rising edge of ncs, whatever the programmed waveform of nrd may be. figure 23-11. read_mode = 0: data is sampled by smc before the rising edge of ncs data sampling t pacc mck a[25:2] nbs0,nbs1, nbs2,nbs3, a0, a1 ncs nrd d[31:0] data sampling t pacc mck d[31:0] a[25:2] nbs0,nbs1, nbs2,nbs3, a0, a1 ncs nrd
208 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.8.3 write waveforms the write protocol is similar to the read protocol. it is depicted in figure 23-12 . the write cycle starts with the address setting on the memory address bus. 23.8.3.1 nwe waveforms the nwe signal is characterized by a setu p timing, a pulse width and a hold timing. 1. nwe_setup: the nwe setup time is defined as the setup of address and data before the nwe falling edge; 2. nwe_pulse: the nwe pulse length is the time between nwe falling edge and nwe rising edge; 3. nwe_hold: the nwe hold time is defined as the hold time of address and data after the nwe rising edge. the nwe waveforms apply to all byte-write lines in byte write access mode: nwr0 to nwr3. 23.8.3.2 ncs waveforms the ncs signal waveforms in write operation are not the same that those applied in read opera- tions, but are separately defined: 1. ncs_wr_setup: the ncs setup time is defined as the setup time of address before the ncs falling edge. 2. ncs_wr_pulse: the ncs pulse length is the time between ncs falling edge and ncs rising edge; 3. ncs_wr_hold: the ncs hold time is defined as the hold time of address after the ncs rising edge. figure 23-12. write cycle a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1 ncs nwe_setup nwe_pulse nwe_hold mck nwe ncs_wr_setup ncs_wr_pulse ncs_wr_hold nwe_cycle
209 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.8.3.3 write cycle the write_cycle time is defined as the total durat ion of the write cycle, that is, from the time where address is set on the address bus to the point where address may change. the total write cycle time is equal to: nwe_cycle = nwe_setup + nwe_pulse + nwe_hold = ncs_wr_setup + ncs_wr_pulse + ncs_wr_hold all nwe and ncs (write) timings are defined separately for each chip select as an integer num- ber of master clock cycles. to ensure that the nwe and ncs timings are coherent, the user must define the total wr ite cycle instead of the hold timing. this implicitly defines the nwe hold time and ncs (write) hold times as: nwe_hold = nwe_cycle - nwe_setup - nwe_pulse ncs_wr_hold = nwe_cycle - ncs_wr_setup - ncs_wr_pulse 23.8.3.4 null delay setup and hold if null setup parameters are programmed for nwe and/or ncs, nwe and/or ncs remain active continuously in case of consecutive write cycles in the same memory (see figure 23-13 ). how- ever, for devices that perform write operations on the rising edge of nwe or ncs, such as sram, either a setup or a hold must be programmed. figure 23-13. null setup and hold values of ncs and nwe in write cycle 23.8.3.5 null pulse programming null pulse is not permitted. pulse must be at least set to 1. a null value leads to unpredictable behavior. ncs mck nwe, nwr0, nwr1, nwr2, nwr3 d[31:0] nwe_pulse ncs_wr_pulse nwe_cycle nwe_pulse ncs_wr_pulse nwe_cycle nwe_pulse ncs_wr_pulse nwe_cycle a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1
210 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.8.4 write mode the write_mode parameter in th e smc_mode register of the corresponding chip select indi- cates which signal controls the write operation. 23.8.4.1 write is controlled by nwe (write_mode = 1): figure 23-14 shows the waveforms of a write operation with write_mode set to 1. the data is put on the bus during the pulse and hold steps of the nwe signal. the internal data buffers are turned out after the nwe_setup time, and until the end of the write cycle, regardless of the programmed waveform on ncs. figure 23-14. write_mode = 1. the write op eration is controlled by nwe 23.8.4.2 write is controlle d by ncs (write_mode = 0) figure 23-15 shows the waveforms of a write operation with write_mode set to 0. the data is put on the bus during the pulse and hold steps of the ncs signal. the internal data buffers are turned out after the ncs_wr_setup time, and until the end of the write cycle, regardless of the programmed waveform on nwe. mck d[31:0] ncs a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1 nwe, nwr0, nwr1, nwr2, nwr3
211 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 23-15. write_mode = 0. the write op eration is controlled by ncs 23.8.5 coding timing parameters all timing parameters are defined for one chip select and are grouped together in one smc_register according to their type. the smc_setup register groups the definition of all setup parameters: ? nrd_setup, ncs_rd_setup, nwe_setup, ncs_wr_setup the smc_pulse register groups the definition of all pulse parameters: ? nrd_pulse, ncs_rd_pulse, nwe_pulse, ncs_wr_pulse the smc_cycle register groups the definition of all cycle parameters: ? nrd_cycle, nwe_cycle table 23-4 shows how the timing parameters are coded and their permitted range. mck d[31:0] ncs nwe, nwr0, nwr1, nwr2, nwr3 a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1 table 23-4. coding and range of timing parameters coded value number of bits effective value permitted range coded value effective value setup [5:0] 6 128 x setup[5] + setup[4:0] 0 31 0 128+31 pulse [6:0] 7 256 x pulse[6] + pulse[5:0] 0 63 0 256+63 cycle [8:0] 9 256 x cycle[8:7] + cycle[6:0] 0 127 0 256+127 0 512+127 0 768+127
212 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.8.6 reset values of timing parameters table 23-5 gives the default value of timing parameters at reset. 23.8.7 usage restriction the smc does not check the validity of the user-programmed parameters. if the sum of setup and pulse parameters is larger than the corresponding cycle parameter, this leads to unpre- dictable behavior of the smc. for read operations: null but positive setup and hold of address and nrd and/or ncs can not be guaranteed at the memory interface because of the propagation dela y of theses signals through external logic and pads. if positive setup and hold values must be verified, then it is strictly recommended to pro- gram non-null values so as to cover possible skews between address, ncs and nrd signals. for write operations: if a null hold value is programmed on nwe, the smc can guarantee a positive hold of address, byte select lines, and ncs signal after the rising edge of nwe. this is true for write_mode = 1 only. see ?early read wait state? on page 213 . for read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable behavior. in read and write cycles, the setup and hold time parameters are defined in reference to the address bus. for external devices that require setup and hold time between ncs and nrd sig- nals (read), or between ncs and nwe signals (write), these setup and hold times must be converted into setup and hold times in reference to the address bus. table 23-5. reset values of timing parameters register reset value smc_setup 0x00000000 all setup timings are set to 1 smc_pulse 0x01010101 all pulse timings are set to 1 smc_cycle 0x00010001 the read and write operation last 3 master clock cycles and provide one hold cycle write_mode 1 write is controlled with nwe read_mode 1 read is controlled with nrd
213 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.9 automatic wait states under certain circumstances, the smc automatica lly inserts idle cycles between accesses to avoid bus contention or operation conflict. 23.9.1 chip select wait states the smc always inserts an idle cycle between 2 transfers on separate chip selects. this idle cycle ensures that there is no bus contention between the de-activation of one device and the activation of the next one. during chip select wait state, all control li nes are turned inactive: nbs0 to nbs3, nwr0 to nwr3, ncs[0..7], nrd lines are all set to 1. figure 23-16 illustrates a chip select wait state between access on chip select 0 and chip select 2. figure 23-16. chip select wait state between a read access on ncs0 and a write access on ncs2 23.9.2 early read wait state in some cases, the smc inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. this wait state is not generated in addition to a chip select wait state. the early read cycle thus only occurs between a write and read access to the same memory device (same chip select). an early read wait state is automatically inserted if at least one of the following conditions is valid: ? if the write controlling signal has no hold time and the read controlling signal has no setup time ( figure 23-17 ). a[25:2] nbs0, nbs1, nbs2, nbs3, a0,a1 ncs0 nrd_cycle chip select wait state nwe_cycle mck ncs2 nrd nwe d[31:0] read to write wait state
214 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? in ncs write controlled mode (write_mode = 0), if there is no hold timing on the ncs signal and the ncs_rd_setup parameter is set to 0, regardless of the read mode ( figure 23-18 ). the write operation must end with a ncs rising edge. without an early read wait state, the write operation could not complete properly. ? in nwe controlled mode (write_mode = 1) and if there is no hold timing (nwe_hold = 0), the feedback of the write control signal is used to control address, data, chip select and byte select lines. if the external write control signal is not inactivated as expected due to load capacitances, an early read wait state is inserted and address, data and control signals are maintained one more cycle. see figure 23-19 . figure 23-17. early read wait state: write with no hold followed by read with no setup write cycle early read wait state mck nrd nwe read cycle no setup no hold d[31:0] nbs0, nbs1, nbs2, nbs3, a0, a1 a[25:2]
215 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 23-18. early read wait state: ncs cont rolled write with no hold followed by a read with no ncs setup figure 23-19. early read wait state: nwe-controlled write with no hold followed by a read with one set-up cycle write cycle (write_mode = 0) early read wait state mck nrd ncs read cycle (read_mode = 0 or read_mode = 1) no setup no hold d[31:0] nbs0, nbs1, nbs2, nbs3, a0,a1 a[25:2] a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1 write cycle (write_mode = 1) early read wait state mck nrd internal write controlling signal external write controlling signal (nwe) d[31:0] read cycle (read_mode = 0 or read_mode = 1) no hold read setup = 1
216 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.9.3 reload user configuration wait state the user may change any of the configuration parameters by writing the smc user interface. when detecting that a new user configuration has been written in the user interface, the smc inserts a wait state before starting the next access. the so called ?reload user configuration wait state? is used by the smc to load the new set of parameters to apply to next accesses. the reload configuration wait state is not applied in addition to the chip select wait state. if accesses before and after re-programming the user interface are made to different devices (chip selects), then one single chip select wait state is applied. on the other hand, if accesses before and after writing the user interface are made to the same device, a reload configuration wait state is inserted, even if the change does not concern the current chip select. 23.9.3.1 user procedure to insert a reload configuration wait state, the smc detects a write access to any smc_mode register of the user interface. if the user only modifies timing registers (smc_setup, smc_pulse, smc_cycle registers) in the user interface, he must validate the modification by writing the smc_mode, even if no change was made on the mode parameters. the user must not change the configuration parameters of an smc chip select (setup, pulse, cycle, mode) if accesses are performed on this cs during the modification. any change of the chip select parameters, while fetching the code from a memory connected on this cs, may lead to unpredictable behavior. the instructions used to modify the parameters of an smc chip select can be executed from the internal ram or from a memory connected to another cs. 23.9.3.2 slow clock mode transition a reload configuration wait state is also inserted when the slow clock mode is entered or exited, after the end of the current transfer (see ?slow clock mode? on page 228 ). 23.9.4 read to write wait state due to an internal mechanism, a wait cycle is always inserted between consecutive read and write smc accesses. this wait cycle is referred to as a read to write wait stat e in this document. this wait cycle is applied in add ition to chip select and reload user configuration wait states when they are to be inserted. see figure 23-16 on page 213 .
217 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.10 data float wait states some memory devices are slow to release the exte rnal bus. for such devices, it is necessary to add wait states (data float wait states) after a read access: ? before starting a read access to a different external memory ? before starting a write access to the same device or to a different external one. the data float output time (t df ) for each external memory device is programmed in the tdf_cycles field of the smc_mode register for the corresponding chip select. the value of tdf_cycles indicates the number of data float wait cycles (between 0 and 15) before the external device releases the bus, and represents the time allowed for the data output to go to high impedance after the memory is disabled. data float wait states do not delay internal memory accesses. hence, a single access to an external memory with long t df will not slow down the executio n of a program from internal memory. the data float wait states management depends on the read_mode and the tdf_mode fields of the smc_mode register for the corresponding chip select. 23.10.1 read_mode setting the read_mode to 1 indicates to the smc that the nrd signal is responsible for turn- ing off the tri-state buffers of the external memory device. the data float period then begins after the rising edge of the nrd sign al and lasts tdf_cycles mck cycles. when the read operation is controlled by the ncs signal (read_mode = 0), the tdf field gives the number of mck cycles during which the data bus remains busy after the rising edge of ncs. figure 23-20 illustrates the data float period in nrd-controlled mode (read_mode =1), assuming a data float period of 2 cycles (tdf_cycles = 2). figure 23-21 shows the read oper- ation when controlled by ncs (read_mode = 0) and the tdf_cycles parameter equals 3.
218 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 23-20. tdf period in nrd controlled read access (tdf = 2) figure 23-21. tdf period in ncs controlled read operation (tdf = 3) nbs0, nbs1, nbs2, nbs3, a0, a1 ncs nrd controlled read operation tpacc mck nrd d[31:0] tdf = 2 clock cycles a[25:2] ncs tdf = 3 clock cycles tpacc mck d[31:0] ncs controlled read operation a[25:2] nbs0, nbs1, nbs2, nbs3, a0,a1 nrd
219 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.10.2 tdf optimization enabled (tdf_mode = 1) when the tdf_mode of the smc_mode register is set to 1 (tdf optimization is enabled), the smc takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert. figure 23-22 shows a read access controlled by nrd, followed by a write access controlled by nwe, on chip select 0. chip se lect 0 has been programmed with: nrd_hold = 4; read_mode = 1 (nrd controlled) nwe_setup = 3; write_mode = 1 (nwe controlled) tdf_cycles = 6; tdf_mode = 1 (optimization enabled). figure 23-22. tdf optimization: no tdf wait states are inserted if the tdf period is over when the next access begins 23.10.3 tdf optimization disabled (tdf_mode = 0) when optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that the data float period is ended when the second access begins. if the hold period of the read1 controlling signal overlaps the data float period, no additional tdf wait st ates will be inserted. figure 23-23 , figure 23-24 and figure 23-25 illustrate the cases: ? read access followed by a read access on another chip select, ? read access followed by a write access on another chip select, ? read access followed by a write access on the same chip select, with no tdf optimization. a [25:2] ncs0 mck nrd nwe d[31:0] read to write wait state tdf_cycles = 6 read access on ncs0 (nrd controlled) nrd_hold= 4 nwe_setup= 3 write access on ncs0 (nwe controlled)
220 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 23-23. tdf optimization disabled (tdf mode = 0). tdf wait states between 2 read accesses on different chip selects figure 23-24. tdf mode = 0: tdf wait states between a read and a write access on different chip selects tdf_cycles = 6 tdf_cycles = 6 tdf_mode = 0 (optimization disabled) a[ 25:2] read1 cycle chip select wait state mck read1 controlling signal (nrd) read2 controlling signal (nrd) d[31:0] read1 hold = 1 read 2 cycle read2 setup = 1 5 tdf wait states nbs0, nbs1, nbs2, nbs3, a0, a1 tdf_cycles = 4 tdf_cycles = 4 tdf_mode = 0 (optimization disabled) a [25:2] read1 cycle chip select wait state read to write wait state mck read1 controlling signal (nrd) write2 controlling signal (nwe) d[31:0] read1 hold = 1 write2 cycle write2 setup = 1 2 tdf wait states nbs0, nbs1, nbs2, nbs3, a0, a1
221 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 23-25. tdf mode = 0: tdf wait states between read and write accesses on the same chip select tdf_cycles = 5 tdf_cycles = 5 tdf_mode = 0 (optimization disabled) a [25:2] read1 cycle read to write wait state mck read1 controlling signal (nrd) write2 controlling signal (nwe) d[31:0] read1 hold = 1 write2 cycle write2 setup = 1 4 tdf wait states nbs0, nbs1, nbs2, nbs3, a0, a1
222 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.11 external wait any access can be extended by an external device using the nw ait input signal of the smc. the exnw_mode field of the smc_mode register on the corresponding chip select must be set to either to ?10? (frozen mode) or ?11? (ready mode). when the exnw_mode is set to ?00? (disabled), the nwait signal is simply ignored on the correspo nding chip select. the nwait signal delays the read or write operation in regards to the read or write controlling signal, depending on the read and write modes of the corresponding chip select. 23.11.1 restriction when one of the exnw_mode is enabled, it is mandatory to program at least one hold cycle for the read/write controlling signal. for that reason, the nwait signal cannot be used in page mode ( ?asynchronous page mode? on page 231 ), or in slow clock mode ( ?slow clock mode? on page 228 ). the nwait signal is assumed to be a response of the external device to the read/write request of the smc. then nwait is examined by the smc only in the pulse state of the read or write controlling signal. the assertion of the nwait signal outside th e expected period has no impact on smc behavior.
223 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.11.2 frozen mode when the external device asserts the nwait signal (active low), and after internal synchroniza- tion of this signal, the smc state is frozen, i.e., smc internal counters are frozen, and all control signals remain unchanged. when the resynchronized nwait signal is deasserted, the smc completes the access, resuming the access from the point where it was stopped. see figure 23- 26 . this mode must be selected when the external device uses the nwait signal to delay the access and to freeze the smc. the assertion of the nwait sign al outside the expected period is ignored as illustrated in figure 23-27 . figure 23-26. write access with nwait assertion in frozen mode (exnw_mode = 10) exnw_mode = 10 (frozen) write_mode = 1 (nwe_controlled) nwe_pulse = 5 ncs_wr_pulse = 7 a [25:2] mck nwe ncs 432 1 110 1 4 5 63222210 write cycle d[31:0] nwait frozen state nbs0, nbs1, nbs2, nbs3, a0,a1 internally synchronized nwait signal
224 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 23-27. read access with nwait assertion in frozen mode (exnw_mode = 10) exnw_mode = 10 (frozen) read_mode = 0 (ncs_controlled) nrd_pulse = 2, nrd_hold = 6 ncs_rd_pulse =5, ncs_rd_hold =3 a [25:2] mck ncs nrd 10 43 43 2 555 22 0 210 210 1 read cycle assertion is ignored nwait internally synchronized nwait signal frozen state nbs0, nbs1, nbs2, nbs3, a0,a1
225 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.11.3 ready mode in ready mode (exnw_mode = 11), the smc behaves differently. normally, the smc begins the access by down counting the setup and pulse counters of the read/write controlling signal. in the last cycle of the pulse phase, the resynchronized nwait signal is examined. if asserted, the smc suspends the access as shown in figure 23-28 and figure 23-29 . after deassertion, the access is completed: the hold step of the access is performed. this mode must be selected when the external de vice uses deassertion of the nwait signal to indicate its ability to complete the read or write operation. if the nwait signal is deasserted before the end of the pulse, or asserted after the end of the pulse of the controlling read/write signal, it has no impact on the access length as shown in fig- ure 23-29 . figure 23-28. nwait assertion in write access: ready mode (exnw_mode = 11) exnw_mode = 11 (ready mode) write_mode = 1 (nwe_controlled) nwe_pulse = 5 ncs_wr_pulse = 7 a [25:2] mck nwe ncs 432 1 00 0 4 5 6321110 write cycle d[31:0] nwait internally synchronized nwait signal wait state nbs0, nbs1, nbs2, nbs3, a0,a1
226 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 23-29. nwait assertion in read access: ready mode (exnw_mode = 11) exnw_mode = 11(ready mode) read_mode = 0 (ncs_controlled) nrd_pulse = 7 ncs_rd_pulse =7 a[25:2] mck ncs nrd 4 5 63200 0 1 4 5 6321 1 read cycle assertion is ignored nwait internally synchronized nwait signal wait state assertion is ignored nbs0, nbs1, nbs2, nbs3, a0,a1
227 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.11.4 nwait latency and read/write timings there may be a latency between the assertion of the read/w rite controlling signal and the asser- tion of the nwait signal by the device. t he programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. otherwise, the smc may enter the hold state of the access without detecting the nwait signal assertion. this is true in frozen mode as well as in ready mode. this is illustrated on fig- ure 23-30 . when exnw_mode is enabled (ready or frozen), th e user must program a pulse length of the read and write controllin g signal of at least: minimal pulse length = nwait latency + 2 resynchronization cycles + 1 cycle figure 23-30. nwait latency exnw_mode = 10 or 11 read_mode = 1 (nrd_controlled) nrd_pulse = 5 a [25:2] mck nrd 43 210 0 0 read cycle minimal pulse length nwait latency nwait intenally synchronized nwait signal wait state 2 cycle resynchronization nbs0, nbs1, nbs2, nbs3, a0,a1
228 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.12 slow clock mode the smc is able to automatically apply a set of ?slow clock mode? read/write waveforms when an internal signal driven by the power management controller is asserted because mck has been turned to a very slow clock rate (typically 32khz clock rate). in this mode, the user-pro- grammed waveforms are ignored and the slow clock mode waveforms are applied. this mode is provided so as to avoid reprogramming the user interface with appropriate waveforms at very slow clock rate. when activated, the sl ow mode is active on all chip selects. 23.12.1 slow clock mode waveforms figure 23-31 illustrates the read and write operations in slow clock mode. they are valid on all chip selects. table 23-6 indicates the value of read and write parameters in slow clock mode. figure 23-31. read/write cycles in slow clock mode a[ 25:2] ncs 1 mck nwe 1 1 nwe_cycle = 3 a [25:2] mck nrd nrd_cycle = 2 1 1 ncs slow clock mode write slow clock mode read nbs0, nbs1, nbs2, nbs3, a0,a1 nbs0, nbs1, nbs2, nbs3, a0,a1 table 23-6. read and write timing parameters in slow clock mode read parameters duration (cycles) write parameters duration (cycles) nrd_setup 1 nwe_setup 1 nrd_pulse 1 nwe_pulse 1 ncs_rd_setup 0 ncs_wr_setup 0 ncs_rd_pulse 2 ncs_wr_pulse 3 nrd_cycle 2 nwe_cycle 3
229 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.12.2 switching from (to) slow clock mode to (from) normal mode when switching from slow clock mode to the nor mal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters.see figure 23-32 on page 229 . the external device may not be fast enough to support such timings. figure 23-33 illustrates the recommended procedure to properly switch from one mode to the other. figure 23-32. clock rate transition occurs while the smc is performing a write operation a [25:2] ncs 1 mck nwe 1 1 nwe_cycle = 3 slow clock mode write slow clock mode internal signal from pmc 11 1 2 3 2 nwe_cycle = 7 normal mode write slow clock mode transition is detected: reload configuration wait state this write cycle finishes with the slow clock mode set of parameters after the clock rate transition slow clock mode write nbs0, nbs1, nbs2, nbs3, a0,a1
230 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 23-33. recommended procedure to switch from slow clock mo de to normal mode or from normal mode to slow clock mode a [25:2] ncs 1 mck nwe 1 1 slow clock mode write slow clock mode internal signal from pmc 2 3 2 normal mode write idle state reload configuration wait state nbs0, nbs1, nbs2, nbs3, a0,a1
231 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.13 asynchronous page mode the smc supports asynchronous burst reads in page mode, providing that the page mode is enabled in the smc_mode register (pmen fiel d). the page size must be configured in the smc_mode register (ps field) to 4, 8, 16 or 32 bytes. the page defines a set of consecutive bytes into memory. a 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. the msb of data address defines the address of the page in memory, the lsb of address define the address of the data in the page as detailed in table 23-7 . with page mode memory devices, the first access to one page (t pa ) takes longer than the subse- quent accesses to the page (t sa ) as shown in figure 23-34 . when in page mode, the smc enables the user to define different read timings for the first access within one page, and next accesses withi n the page. notes: 1. a denotes the address bus of the memory device 2. for 16-bit devices, the bit 0 of address is ignored. for 32-bit devices, bits [1:0] are ignored. 23.13.1 protocol and timings in page mode figure 23-34 shows the nrd and ncs timings in page mode access. figure 23-34. page mode read protocol (address msb and lsb are defined in table 23-7 ) the nrd and ncs signals are held low during all read transfers, whatever the programmed val- ues of the setup and hold timings in the us er interface may be. moreover, the nrd and ncs table 23-7. page address and data address within a page page size page address (1) data address in the page (2) 4 bytes a[25:2] a[1:0] 8 bytes a[25:3] a[2:0] 16 bytes a[25:4] a[3:0] 32 bytes a[25:5] a[4:0] a[msb] ncs mck nrd d[31:0] ncs_rd_pulse nrd_pulse nrd_pulse tsa tpa tsa a[lsb]
232 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary timings are identical. the pulse length of the first access to the page is defined with the ncs_rd_pulse field of the smc_pulse register. the pulse length of subsequent accesses within the page are defined using the nrd_pulse parameter. in page mode, the programming of the read timings is described in table 23-8 : the smc does not check the coherency of timings. it will always apply the ncs_rd_pulse timings as page access timing (t pa ) and the nrd_pulse for accesses to the page (t sa ), even if the programmed value for t pa is shorter than the programmed value for t sa . 23.13.2 byte access type in page mode the byte access type configuration remains active in page mode. for 16-bit or 32-bit page mode devices that require byte selection signals, configure the bat field of the smc_register to 0 (byt e select access type). 23.13.3 page mode restriction the page mode is not compatible with the use of the nwait signal. using the page mode and the nwait signal may lead to unpredictable behavior. 23.13.4 sequential and non-sequential accesses if the chip select and the msb of addresses as defined in table 23-7 are identical, then the cur- rent access lies in the same page as the previous one, and no page break occurs. using this information, all data within the same page, sequential or not sequential, are accessed with a minimum access time (t sa ). figure 23-35 illustrates access to an 8-bit memory device in page mode, with 8-byte pages. access to d1 c auses a page access with a long access time (t pa ). accesses to d3 and d7, though they are not sequential accesses, only require a short access time (t sa ). if the msb of addresses are different, the smc performs the access of a new page. in the same way, if the chip select is diffe rent from the previous access, a page break occurs. if two sequen- tial accesses are made to the page mode memory , but separated by an other internal or external peripheral access, a page break occurs on the second access because the chip select of the device was deasserted between both accesses. table 23-8. programming of read timings in page mode parameter value definition read_mode ?x? no impact ncs_rd_setup ?x? no impact ncs_rd_pulse t pa access time of first access to the page nrd_setup ?x? no impact nrd_pulse t sa access time of subsequent accesses in the page nrd_cycle ?x? no impact
233 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 23-35. access to non-sequential data within the same page a [25:3] a[2], a1, a0 ncs mck nrd page address a1 a3 a7 d[7:0] ncs_rd_pulse nrd_pulse nrd_pulse d1 d3 d7
234 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.14 static memory contro ller (smc) user interface the smc is programmed using the registers listed in table 23-9 . for each chip select, a set of 4 registers is used to pro- gram the parameters of the exter nal device connected on it. in table 23-9 , ?cs_number? denotes the chip select number. 16 bytes (0x10) are required per chip select. the user must complete writing the configuration by writing any one of the smc_mode registers. table 23-9. register mapping offset register name access reset 0x10 x cs_number + 0x00 smc setup register smc_setup read-write 0x00000000 0x10 x cs_number + 0x04 smc pulse register smc_pulse read-write 0x01010101 0x10 x cs_number + 0x08 smc cycle register smc_cycle read-write 0x00010001 0x10 x cs_number + 0x0c smc mode register smc_mode read-write 0x10001000 0xec-0xfc reserved - - -
235 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.14.1 smc setup register register name: smc_setup[0..7] addresses: 0xffffec00 [0], 0xffffec10 [1], 0xffffec20 [2], 0xffffec30 [3], 0xffffec40 [4], 0xffffec50 [5], 0xffffec60 [6], 0xffffec70 [7] access type: read-write ? nwe_setup: nwe setup length the nwe signal setup length is defined as: nwe setup length = (128* nwe_setup [5] + nwe_setup[4:0]) clock cycles ? ncs_wr_setup: ncs setup length in write access in write access, the ncs signal setup length is defined as: ncs setup length = (128* ncs_wr_setup [5] + ncs_wr_setup[4:0]) clock cycles ? nrd_setup: nrd setup length the nrd signal setup length is defined in clock cycles as: nrd setup length = (128* nrd_setup[5] + nrd_setup[4:0]) clock cycles ? ncs_rd_setup: ncs setup length in read access in read access, the ncs signal setup length is defined as: ncs setup length = (128* ncs_rd_setup [5] + ncs_rd_setup[4:0]) clock cycles 31 30 29 28 27 26 25 24 ? ? ncs_rd_setup 23 22 21 20 19 18 17 16 ? ? nrd_setup 15 14 13 12 11 10 9 8 ? ? ncs_wr_setup 76543210 ? ? nwe_setup
236 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.14.2 smc pulse register register name: smc_pulse[0..7] addresses: 0xffffec04 [0], 0xffffec14 [1], 0xffffec24 [2], 0xffffec34 [3], 0xffffec44 [4], 0xffffec54 [5], 0xffffec64 [6], 0xffffec74 [7] access type: read-write ? nwe_pulse: nwe pulse length the nwe signal pulse length is defined as: nwe pulse length = (256* nwe_pulse[6] + nwe_pulse[5:0]) clock cycles the nwe pulse length must be at least 1 clock cycle. ? ncs_wr_pulse: ncs pulse length in write access in write access, the ncs signal pulse length is defined as: ncs pulse length = (256* ncs_wr_pul se[6] + ncs_wr_pulse[5:0]) clock cycles the ncs pulse length must be at least 1 clock cycle. ? nrd_pulse: nrd pulse length in standard read access, the nrd signal pulse length is defined in clock cycles as: nrd pulse length = (256* nrd_pulse[ 6] + nrd_pulse[5:0]) clock cycles the nrd pulse length must be at least 1 clock cycle. in page mode read access, the nrd_pulse parameter defines the duration of the subsequent accesses in the page. ? ncs_rd_pulse: ncs pulse length in read access in standard read access, the ncs signal pulse length is defined as: ncs pulse length = (256* ncs_rd_pul se[6] + ncs_rd_pulse[5:0]) clock cycles the ncs pulse length must be at least 1 clock cycle. in page mode read access, the ncs_rd_pulse parameter defines the duration of the first access to one page. 31 30 29 28 27 26 25 24 ? ncs_rd_pulse 23 22 21 20 19 18 17 16 ? nrd_pulse 15 14 13 12 11 10 9 8 ? ncs_wr_pulse 76543210 ?nwe_pulse
237 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.14.3 smc cycle register register name: smc_cycle[0..7] addresses: 0xffffec08 [0], 0xffffec18 [1], 0xffffec28 [2], 0xffffec38 [3], 0xffffec48 [4], 0xffffec58 [5], 0xffffec68 [6], 0xffffec78 [7] access type: read-write ? nwe_cycle: total write cycle length the total write cycle length is the total du ration in clock cycles of the write cycle. it is equal to the sum of the setup, pul se and hold steps of the nwe and ncs signals. it is defined as: write cycle length = (nwe_cycle[8:7 ]*256 + nwe_cycle[6:0]) clock cycles ? nrd_cycle: total read cycle length the total read cycle length is the total duration in clock cycles of the read cycle. it is equal to the sum of the setup, pulse and hold steps of the nrd and ncs signals. it is defined as: read cycle length = (nrd_cycle[8:7] *256 + nrd_cycle[6:0]) clock cycles 31 30 29 28 27 26 25 24 ???????nrd_cycle 23 22 21 20 19 18 17 16 nrd_cycle 15 14 13 12 11 10 9 8 ???????nwe_cycle 76543210 nwe_cycle
238 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 23.14.4 smc mode register register name: smc_mode[0..7] addresses: 0xffffec0c [0], 0xffffec1c [1], 0xffffe c2c [2], 0xffffec3c [3], 0xffffec4c [4], 0xffffec5c [5], 0xffffec6c [6], 0xffffec7c [7] access type: read-write ? read_mode: 1: the read operation is controlled by the nrd signal. ? if tdf cycles are programmed, the external bus is marked busy after the rising edge of nrd. ? if tdf optimization is enabled (tdf_mode =1), tdf wait states are inserted after the setup of nrd. 0: the read operation is controlled by the ncs signal. ? if tdf cycles are programmed, the external bus is marked busy after the rising edge of ncs. ? if tdf optimization is enabled (tdf_mode =1), tdf wait states are inserted after the setup of ncs. ?write_mode 1: the write operation is controlled by the nwe signal. ? if tdf optimization is enabled (tdf_mode =1), tdf wa it states will be inserted after the setup of nwe. 0: the write operation is controlled by the ncs signal. ? if tdf optimization is enabled (tdf_mode =1), tdf wa it states will be inserted after the setup of ncs. ? exnw_mode: nwait mode the nwait signal is used to extend the current read or writ e signal. it is only taken into account during the pulse phase of the read and writ e controlling signal. when the use of nwait is enable d, at least one cycle hold duration mu st be pro- grammed for the read and write controlling signal. ? disabled mode: the nwait input signal is ignored on the corresponding chip select. ? frozen mode: if asserted, the nwait signal freezes the current read or write cycle. after deassertion, the read/write cycle is resumed from the point where it was stopped. 31 30 29 28 27 26 25 24 ?? ps ???pmen 23 22 21 20 19 18 17 16 ? ? ? tdf_mode tdf_cycles 15 14 13 12 11 10 9 8 ?? dbw ???bat 76543210 ? ? exnw_mode ? ? write_mode read_mode exnw_mode nwait mode 00disabled 01reserved 1 0 frozen mode 1 1 ready mode
239 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? ready mode: the nwait si gnal indicates the availa bility of the external device at t he end of the pulse of the controlling read or write signal, to complete the access. if high, the access normally completes. if low, the access is extended until nwait returns high. ? bat: byte access type this field is used only if dbw defines a 16- or 32-bit data bus. ? 1: byte write access type: ? write operation is controlled us ing ncs, nwr0, nwr1, nwr2, nwr3. ? read operation is controlled using ncs and nrd. ? 0: byte select access type: ? write operation is controlled using ncs, nwe, nbs0, nbs1, nbs2 and nbs3 ? read operation is controlled using ncs, nrd, nbs0, nbs1, nbs2 and nbs3 ? dbw: data bus width ? tdf_cycles: data float time this field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the read controlling signal. the smc always provide one full cycle of bus turnaround after the tdf_cycles period. the external bus cannot be used by another chip select during tdf_cycles + 1 cycles. from 0 up to 15 tdf_cycles can be set. ? tdf_mode: tdf optimization 1: tdf optimization is enabled. ? the number of tdf wait states is optimized using the setup period of the next read/write access. 0: tdf optimization is disabled. ? the number of tdf wait states is inserted before the next access begins. ? pmen: page mode enabled 1: asynchronous burst read in page mode is applied on the corresponding chip select. 0: standard read is applied. ? ps: page size if page mode is enabled, this field indicates the size of the page in bytes. dbw data bus width 008-bit bus 0116-bit bus 1032-bit bus 11reserved ps page size 0 0 4-byte page 0 1 8-byte page 1 0 16-byte page 1 1 32-byte page
240 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary
241 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 24. sdram controller (sdramc) 24.1 description the sdram controller (sdramc) extends the memory capabilities of a ch ip by providing the interface to an external 16-bit or 32-bit sdram device. the page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. it supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. the sdram controller supports a read or write burst length of one location. it keeps track of the active row in each bank, thus maximizing sdram performance, e.g., the application may be placed in one bank and data in the other banks. so as to optimize performance, it is advisable to avoid accessing different rows in the same bank. the sdram controller supports a cas latency of 1, 2 or 3 and optimizes the read access depending on the frequency. the different modes available - self-refresh, power-down and deep power-down modes - mini- mize power consumption on the sdram device. 24.2 i/o lines description table 24-1. i/o line description name description type active level sdck sdram clock output sdcke sdram clock enable output high sdcs sdram controller chip select output low ba[1:0] bank select signals output ras row signal output low cas column signal output low sdwe sdram write enable output low nbs[3:0] data mask enable signals output low sdramc_a[12:0] address bus output d[31:0] data bus i/o
242 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 24.3 application example 24.3.1 software interface the sdram address space is organized into banks, rows, and columns. the sdram controller allows mapping different memory types according to the values set in the sdramc configura- tion register. the sdram controller?s function is to make the sdram device access protocol transparent to the user. table 24-2 to table 24-7 illustrate the sdram device memory mapping seen by the user in correlation with the device structure. various co nfigurations are illustrated. 24.3.1.1 32-bit memory data bus width notes: 1. m[1:0] is the byte address inside a 32-bit word. 3. bk[1] = ba1, bk[0] = ba0. table 24-2. sdram configuration mapping: 2k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[10:0] column[7:0] m[1:0] bk[1:0] row[10:0] column[8:0] m[1:0] bk[1:0] row[10:0] column[9:0] m[1:0] bk[1:0] row[10:0] column[10:0] m[1:0] table 24-3. sdram configuration mapping: 4k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[11:0] column[7:0] m[1:0] bk[1:0] row[11:0] column[8:0] m[1:0] bk[1:0] row[11:0] column[9:0] m[1:0] bk[1:0] row[11:0] column[10:0] m[1:0] table 24-4. sdram configuration mapping: 8k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[12:0] column[7:0] m[1:0] bk[1:0] row[12:0] column[8:0] m[1:0] bk[1:0] row[12:0] column[9:0] m[1:0] bk[1:0] row[12:0] column[10:0] m[1:0]
243 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 24.3.1.2 16-bit memory data bus width notes: 1. m0 is the byte address inside a 16-bit half-word. 4. bk[1] = ba1, bk[0] = ba0. table 24-5. sdram configuration mapping: 2k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[10:0] column[7:0] m0 bk[1:0] row[10:0] column[8:0] m0 bk[1:0] row[10:0] column[9:0] m0 bk[1:0] row[10:0] column[10:0] m0 table 24-6. sdram configuration mapping: 4k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[11:0] column[7:0] m0 bk[1:0] row[11:0] column[8:0] m0 bk[1:0] row[11:0] column[9:0] m0 bk[1:0] row[11:0] column[10:0] m0 table 24-7. sdram configuration mapping: 8k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[12:0] column[7:0] m0 bk[1:0] row[12:0] column[8:0] m0 bk[1:0] row[12:0] column[9:0] m0 bk[1:0] row[12:0] column[10:0] m0
244 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 24.4 product dependencies 24.4.1 sdram device initialization the initialization sequence is generated by softw are. the sdram devices are initialized by the following sequence: 1. sdram features must be set in the configuration register: asynchronous timings (trc, tras, etc.), number of columns, rows, cas latency, and the data bus width. 2. for mobile sdram, temperature-compensated self refresh (tcsr), drive strength (ds) and partial array self refresh (pasr) must be set in the low power register. 3. the sdram memory type must be set in the memory device register. 4. a minimum pause of 200 s is provided to precede any signal toggle. 5. (1) a nop command is issued to the sdram devices. the application must set mode to 1 in the mode register and perform a write access to any sdram address. 6. an all banks precharge command is issued to the sdram devices. the application must set mode to 2 in the mode register and perform a write access to any sdram address. 7. eight auto-refresh (cbr) cycles are provided. the application must set the mode to 4 in the mode register and perform a write access to any sdram location eight times. 8. a mode register set (mrs) cycle is issued to program the parameters of the sdram devices, in particular cas latency and burst length. the application must set mode to 3 in the mode register and perform a write access to the sdram. the write address must be chosen so that ba[1:0] are set to 0. for example, with a 16-bit 128 mb sdram (12 rows, 9 columns, 4 banks) bank address, the sdram write access should be done at the address 0x20000000. 9. for mobile sdram initialization, an ex tended mode register set (emrs) cycle is issued to program the sdram parameters (tcsr, pasr, ds). the application must set mode to 5 in the mode register and perform a write access to the sdram. the write address must be chosen so that ba[1] or ba[0] are set to 1. for example, with a 16-bit 128 mb sdram, (12 rows, 9 columns, 4 banks) bank address the sdram write access should be done at the address 0x20800000 or 0x20400000. 10. the application must go into normal mode, setting mode to 0 in the mode register and performing a write access at any location in the sdram. 11. write the refresh rate into the count field in the sdramc refresh timer register. (refresh rate = delay between refresh cycles). the sdram device requires a refresh every 15.625 s or 7.81 s. with a 100 mhz frequency, the refresh timer counter register must be set with the value 1562(15.652 s x 100 mhz) or 781(7.81 s x 100 mhz). after initialization, the sdram devices are fully functional. note: 1. it is strongly recommended to respect the instructions stated in step 5 of the initialization pro- cess in order to be certain that the subseque nt commands issued by the sdramc will be taken into account.
245 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 24-1. sdram device initialization sequence 24.4.2 i/o lines the pins used for interfacing the sdram contro ller may be multiplexed with the pio lines. the programmer must first program the pio controller to assign the sdram controller pins to their peripheral function. if i/o lines of the sdram controller are not used by the application, they can be used for other purposes by the pio controller. 24.4.3 interrupt the sdram controller interrupt (refresh error notification) is connected to the memory control- ler. this interrupt may be ored with other syst em peripheral interrupt lines and is finally provided as the system interrupt source (source 1) to the aic (advanced interrupt controller). using the sdram controller interrupt requires the aic to be programmed first. sdck sdramc_a[9:0] a10 sdramc_a[12:11] sdcs ras cas sdwe nbs inputs stable for 200 sec precharge all banks 1st auto-refresh 8th auto-refresh mrs command valid command sdcke t rp t rc t mrd
246 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 24.5 functional description 24.5.1 sdram controller write cycle the sdram controller allows burst access or single access. in both cases, the sdram control- ler keeps track of the active row in each bank, th us maximizing performance. to initiate a burst access, the sdram controller uses the transfe r type signal provided by the master requesting the access. if the next access is a sequential write access, writing to the sdram device is car- ried out. if the next access is a write-sequential access, but the current a ccess is to a boundary page, or if the next access is in another ro w, then the sdram controller generates a precharge command, activates the new row and initiates a write command. to comply with sdram timing parameters, additional clock cycles ar e inserted between precharge/active (t rp ) commands and active/write (t rcd ) commands. for definition of these timing parameters, refer to the ?sdramc configuration register? on page 256 . this is described in figure 24-2 below. figure 24-2. write burst, 32-bit sdram access 24.5.2 sdram controller read cycle the sdram controller allows burst access, incremental burst of unspecified length or single access. in all cases, the sdram controller keeps track of the active row in each bank, thus maximizing performance of the sdram. if row and bank addresses do not match the previous row/bank address, then the sdram controller automatically generates a precharge command, activates the new row and starts the read command. to comply with the sdram timing param- eters, additional clock cycles on sdck are inserted between precharge and active commands (t rp ) and between active and read command (t rcd ). these two parameters are set in the config- uration register of the sdram controller. after a read command, additional wait states are generated to comply with the cas latency (1, 2 or 3 clock delays specified in the configuration register). sdck sdcs ras cas sdramc_a[12:0] d[31:0] t rcd = 3 dna sdwe dnb dnc dnd dne dnf dng dnh dni dnj dnk dnl row n col a col b col c col d col e col f col g col h col i col j col k col l
247 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary for a single access or an incremented burst of unspecified length, the sdram controller antici- pates the next access. while the last value of t he column is returned by the sdram controller on the bus, the sdram controller anticipates the read to the next column and thus anticipates the cas latency. this reduces the effect of the cas latency on the internal bus. for burst access of specified length (4, 8, 16 words), access is not anticipated. this case leads to the best performance. if the burst is broken (border, busy mode, etc.), the next access is han- dled as an incrementing burst of unspecified length. figure 24-3. read burst, 32-bit sdram access sdck sdcs ras cas sdramc_a[12:0] d[31:0] (input) t rcd = 3 dna sdwe dnb dnc dnd dne dnf row n col a col b col c col d col e col f cas = 2
248 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 24.5.3 border management when the memory row boundary has been reached, an automatic page break is inserted. in this case, the sdram controller generates a precharge command, activates the new row and initi- ates a read or write command. to comply with sd ram timing parameters, an additional clock cycle is inserted between the precharge/active (t rp ) command and the active/read (t rcd ) com- mand. this is described in figure 24-4 below. figure 24-4. read burst with boundary row access sdck sdcs ras cas sdramc_a[12:0] d[31:0] t rp = 3 sdwe row m col a col a col b col c col d col e dna dnb dnc dnd t rcd = 3 cas = 2 col b col c col d dma dmb dmc dmd row n dme
249 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 24.5.4 sdram controller refresh cycles an auto-refresh command is used to refresh the sdram device. refresh addresses are gener- ated internally by the sdram device and incremented after each auto-refresh automatically. the sdram controller generates these auto-refresh commands periodically. an internal timer is loaded with the value in the register sdramc _tr that indicates the number of clock cycles between refresh cycles. a refresh error interrupt is generated when the previous auto-refresh command did not perform. it is acknowledged by reading the interrupt status register (sdramc_isr). when the sdram controller initia tes a refresh of the sdram devi ce, internal memory accesses are not delayed. however, if the cpu tries to ac cess the sdram, the slave indicates that the device is busy and the master is held by a wait signal. see figure 24-5 . figure 24-5. refresh cycle followed by a read access 24.5.5 power management three low-power modes are available: ? self-refresh mode: the sdram executes its own auto-refresh cycle without control of the sdram controller. current drain ed by the sdram is very low. ? power-down mode: auto-refresh cycles are controlled by the sdram controller. between auto-refresh cycles, the sdram is in power-down. current drained in power-down mode is higher than in self-refresh mode. ? deep power-down mode: (only available with mobile sdram) the sdram contents are lost, but the sdram does not drain any current. the sdram controller activates one low-power mode as soon as the sdram device is not selected. it is possible to delay the entry in self-refresh and power-down mode after the last access by programming a timeout value in the low power register. sdck sdcs ras cas sdramc_a[12:0] d[31:0] (input) t rp = 3 sdwe dnb dnc dnd col c col d cas = 2 row m col a t rc = 8 t rcd = 3 dma row n
250 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 24.5.5.1 self-refresh mode this mode is selected by programming the lpcb field to 1 in the sdramc low power register. in self-refresh mode, the sdram device retains data without external clocking and provides its own internal clocking, thus performing its own auto-refresh cycles. all the inputs to the sdram device become ?don?t care? except sdcke, whic h remains low. as soon as the sdram device is selected, the sdram controller provides a sequence of commands and exits self-refresh mode. some low-power sdrams (e.g., mobile sdram) can refresh only one quarter or a half quarter or all banks of the sdram array. this feature reduces the self-refresh current. to configure this feature, temperature compensated self refresh (tcsr), partial array self refresh (pasr) and drive strength (ds) parameters must be set in the low power register and transmitted to the low-power sdram du ring initialization. the sdram device must remain in self-refresh mode for a minimum period of t ras and may remain in self-refresh mode for an indefinite period. this is described in figure 24-6 . figure 24-6. self-refresh mode behavior sdck sdcs ras cas sdramc_a[12:0] self refresh mode sdwe row t xsr = 3 sdcke write sdramc_srr srcb = 1 access request to the sdram controller
251 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 24.5.5.2 low-power mode this mode is selected by programming the lpcb field to 2 in the sdramc low power register. power consumption is greater than in self-refresh mode. all the input and output buffers of the sdram device are deactivated except sdcke, which remains low. in contrast to self-refresh mode, the sdram device cannot remain in low-power mode longer than the refresh period (64 ms for a whole device refresh operation). as no auto-refresh operations are performed by the sdram itself, the sdram controller carries out the refresh operation. the exit procedure is faster than in self-refresh mode. this is described in figure 24-7 . figure 24-7. low-power mode behavior sdck sdcs ras cas sdramc_a[12:0] d[31:0] (input) t rcd = 3 dna dnb dnc dnd dne dnf row n col a col b col c col d col e col f cas = 2 sdcke low power mode
252 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 24.5.5.3 deep power-down mode this mode is selected by programming the lpcb field to 3 in the sdramc low power register. when this mode is activated, all internal voltage generators inside the sdram are stopped and all data is lost. when this mode is enabled, the application must not access to the sdram until a new initializa- tion sequence is done (see ?sdram device initialization? on page 244 ). this is described in figure 24-8 . figure 24-8. deep power-down mode behavior sdck sdcs ras cas sdramc_a[12:0] d[31:0] (input) t rp = 3 sdwe dnb dnc dnd col c col d row n cke
253 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 24.6 sdram controller ( sdramc) user interface table 24-8. register mapping offset register name access reset 0x00 sdramc mode register sdramc_mr read-write 0x00000000 0x04 sdramc refresh timer register sdramc_tr read-write 0x00000000 0x08 sdramc configuration regist er sdramc_cr read-write 0x852372c0 0x10 sdramc low power register sdramc_lpr read-write 0x0 0x14 sdramc interrupt enable register sdramc_ier write-only ? 0x18 sdramc interrupt disable register sdramc_idr write-only ? 0x1c sdramc interrupt mask register sdramc_imr read-only 0x0 0x20 sdramc interrupt status register sdramc_isr read-only 0x0 0x24 sdramc memory device register sdramc_mdr read 0x0 0x28 - 0xfc reserved ? ? ?
254 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 24.6.1 sdramc mode register register name : sdramc_mr address: 0xffffea00 access type : read-write reset value : 0x00000000 ? mode: sdramc command mode this field defines the command issued by the sdram controller when the sdram device is accessed. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????? mode mode description 000 normal mode. any access to the sdram is decoded normally. to activate this mode, command must be followed by a write to the sdram. 001 the sdram controller issues a nop command when the sdram device is accessed regardless of the cycle. to activate this mo de, command must be followe d by a write to the sdram. 010 the sdram controller issues an ?all banks prec harge? command when the sdram device is accessed regardless of the cycle. to activate this mode, co mmand must be followed by a write to the sdram. 011 the sdram controller issues a ?load mode registe r? command when the sdram device is accessed regardless of the cycle. to activate this mode, co mmand must be followed by a write to the sdram. 100 the sdram controller issues an ?auto-refresh? command when the sdram device is accessed regardless of the cycle. previously, an ?all banks precharge? command must be issued. to activate this mode, command must be followed by a write to the sdram. 101 the sdram controller issues an ?extended load mo de register? command when the sdram device is accessed regardless of the cycle. to activate this mode, the ?extended load mode register? command must be followed by a write to the sdram. the writ e in the sdram must be done in the appropriate bank; most low-power sdram devices use the bank 1. 1 1 0 deep power-down mode. enters deep power-down mode.
255 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 24.6.2 sdramc refresh timer register register name : sdramc_tr address: 0xffffea04 access type : read-write reset value : 0x00000000 ? count: sdramc refresh timer count this 12-bit field is loaded into a timer that generates the refr esh pulse. each time the refresh pulse is generated, a refresh burst is initiated. the value to be loaded depends on the sdramc clock frequency (mck: master clock), the refresh rate of the sdram device and the refresh burst length where 15.6 s per row is a typical value for a burst of length one. to refresh the sdram device, this 12-bit field must be written. if this condition is not satisfied, no refresh command is issued and no refresh of the sdram device is carried out. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???? count 76543210 count
256 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 24.6.3 sdramc configuration register register name : sdramc_cr address: 0xffffea08 access type : read-write reset value : 0x852372c0 ? nc: number of column bits reset value is 8 column bits. ? nr: number of row bits reset value is 11 row bits. ? nb: number of banks reset value is two banks. 31 30 29 28 27 26 25 24 txsr tras 23 22 21 20 19 18 17 16 trcd trp 15 14 13 12 11 10 9 8 trc twr 76543210 dbw cas nb nr nc nc column bits 008 019 1010 1111 nr row bits 00 11 01 12 10 13 11 reserved nb number of banks 02 14
257 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? cas: cas latency reset value is two cycles. in the sdramc, only a cas latency of one, two and three cycles are managed. ? dbw: data bus width reset value is 16 bits 0: data bus width is 32 bits. 1: data bus width is 16 bits. ? twr: write recovery delay reset value is two cycles. this field defines the write recovery time in numb er of cycles. number of cycles is between 0 and 15. ? trc: row cycle delay reset value is seven cycles. this field defines the delay between a refresh and an activate command in numbe r of cycles. number of cycles is between 0 and 15. ? trp: row precharge delay reset value is three cycles. this field defines the delay between a precharge command and another command in number of cycles. number of cycles is between 0 and 15. ? trcd: row to column delay reset value is two cycles. this field defines the delay between an activate comman d and a read/write command in number of cycles. number of cycles is between 0 and 15. ? tras: active to precharge delay reset value is five cycles. this field defines the delay between an activate command and a precharge command in number of cycles. number of cycles is between 0 and 15. ? txsr: exit self refresh to active delay reset value is eight cycles. this field defines the delay between scke set high and an activate command in numb er of cycles. number of cycles is between 0 and 15. cas cas latency (cycles) 00 reserved 01 1 10 2 11 3
258 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 24.6.4 sdramc low power register register name : sdramc_lpr address: 0xffffea10 access type : read-write reset value :0x0 ? lpcb: low-power configuration bits ? pasr: partial array self-refresh (only for low-power sdram) pasr parameter is transmitted to the sdram during initialization to specify whether only one quar ter, one half or all banks of the sdram array are enabled. disabled banks are not refreshed in self-refresh mode. this parameter must be set according to the sdram device specification. ? tcsr: temperature compensated self -refresh (only fo r low-power sdram) tcsr parameter is transmitted to the sdram during initiali zation to set the refresh interval during self-refresh mode depending on the temperature of the low-power sdram. this parameter must be set according to the sdram device specification. ? ds: drive strength (only for low-power sdram) ds parameter is transmitted to the sdram during initialization to sele ct the sdram strength of data output. this parame- ter must be set according to the sdram device specification. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?? timeout ds tcsr 76543210 ? pasr ? ? lpcb 00 low power feature is inhibited: no power-down, self -refresh or deep power-down command is issued to the sdram device. 01 the sdram controller issues a self-refresh comm and to the sdram device, the sdclk clock is deactivated and the sdcke signal is set low. t he sdram device leaves the self refresh mode when accessed and enters it after the access. 10 the sdram controller issues a power-down command to the sdram device after each access, the sdcke signal is set to low. the sdram device leaves the power-down mode when accessed and enters it after the access. 11 the sdram controller issues a deep power-down command to the sdram device. this mode is unique to low-power sdram.
259 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? timeout: time to define when low-power mode is enabled 00 the sdram controller activates the sdram low-power mo de immediately after the end of the last transfer. 01 the sdram controller activates the sdram low-powe r mode 64 clock cycles afte r the end of the last transfer. 10 the sdram controller activates the sdram low-power mode 128 clock cycles after the end of the last transfer. 11 reserved.
260 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 24.6.5 sdramc interrupt enable register register name : sdramc_ier address: 0xffffea14 access type : write-only ? res: refresh error status 0: no effect. 1: enables the refresh error interrupt. 24.6.6 sdramc interrupt disable register register name : sdramc_idr address: 0xffffea18 access type : write-only ? res: refresh error status 0: no effect. 1: disables the refresh error interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????res 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????res
261 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 24.6.7 sdramc interrupt mask register register name : sdramc_imr address: 0xffffea1c access type : read-only ? res: refresh error status 0: the refresh error interrupt is disabled. 1: the refresh error interrupt is enabled. 24.6.8 sdramc interrupt status register register name : sdramc_isr address: 0xffffea20 access type : read-only ? res: refresh error status 0: no refresh error has been detected since the register was last read. 1: a refresh error has been detected since the register was last read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????res 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????res
262 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 24.6.9 sdramc memory device register register name : sdramc_mdr address: 0xffffea24 access type : read-write ? md: memory device type 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????? md 00 sdram 01 low-power sdram 10 reserved 11 reserved.
263 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25. error corrected co de controller (ecc) 25.1 description nand flash/smartmedia devices contain by default invalid blocks which have one or more invalid bits. over the nand flash/smartmedia lifetime, additional invalid blocks may occur which can be detected/corrected by ecc code. the ecc controller is a mechanism that encodes data in a manner that makes possible the identification and correction of certain errors in data. the ecc controller is capable of single bit error correction and 2-bit random detection. w hen nand flash/smartmedia have more than 2 bits of errors, the data cannot be corrected. the ecc user interface is compliant with the arm ? advanced peripheral bus (apb rev2). 25.2 block diagram figure 25-1. block diagram 25.3 functional description a page in nand flash and smartmedia memories contains an area for main data and an addi- tional area used for redundancy (ecc). the page is organized in 8-bit or 16-bit words. the page size corresponds to the number of words in the main area plus the number of words in the extra area used for redundancy. over time, some memory locations may fail to program or erase properly. in order to ensure that data is stored properly over the life of the nand flash device, nand flash providers recom- user interface ctrl/ecc algorithm static memory controller apb nand flash smartmedia logic ecc controller
264 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary mend to utilize either 1 ecc per 256 bytes of data, 1 ecc per 512 bytes of data or 1 ecc for all of the page. the only configurations required for ecc are the nand flash or the smartmedia page size (528/2112/4224) and the type of correction wanted (1 ecc for all the page/1 ecc per 256 bytes of data /1 ecc per 512 bytes of data). page size is configured setting the pagesize field in the ecc mode register (ecc_mr). type of corre ction is configured setting the typcorrect field in the ecc mode register (ecc_mr). ecc is automatically computed as soon as a read (00h)/write (80h) command to the nand flash or the smartmedia is detected. read and write access must start at a page boundary. ecc results are available as soon as the counte r reaches the end of the main area. values in the ecc parity registers (ecc_pr0 to ecc_pr15) are then valid and locked until a new start condition occurs (read/write command followed by address cycles). 25.3.1 write access once the flash memory page is written, the computed ecc codes are available in the ecc par- ity (ecc_pr0 to ecc_pr15) registers. the ecc code values must be written by the software application in the extra area used for redundancy. the number of write accesses in the extra area is a function of the value of the type of correction field. for example, for 1 ecc per 256 bytes of data for a page of 512 bytes, only the values of ecc_pr0 and ecc_pr1 must be writ- ten by the software application. other registers are meaningless. 25.3.2 read access after reading the whole data in the main area, the application must perform read accesses to the extra area where ecc code has been previously stored. error detection is automatically per- formed by the ecc controller. please note that it is mandatory to read consecutively the entire main area and the locations where parity and nparity values have been previously stored to let the ecc controller perform error detection. the application can check the ecc status registers (ecc_sr1/ecc_sr2) for any detected errors. it is up to the application to correct any detected error. ecc computation can detect four different circumstances: ? no error: xor between the ecc computation and the ecc code stored at the end of the nand flash or smartmedia page is equal to 0. no error flags in the ecc status registers (ecc_sr1/ecc_sr2). ? recoverable error: only the recerr flags in the ecc status registers (ecc_sr1/ecc_sr2) are set. the corrupted word offset in the read page is defined by the wordaddr field in the ecc parity registers (ecc_pr0 to ecc_pr15). the corrupted bit position in the concerned word is defined in the bitaddr field in the ecc parity registers (ecc_pr0 to ecc_pr15). ? ecc error: the eccerr flag in the ecc status registers (ecc_sr1/ecc_sr2) are set. an error has been detected in the ecc code stored in the flash memory. the position of the corrupted bit can be found by the application performing an xor between the parity and the nparity contained in the ecc code stored in the flash memory. ? non correctable error: the mulerr flag in the ecc status registers (ecc_sr1/ecc_sr2) are set. several unrecoverable errors have been detected in the flash memory page.
265 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ecc status registers, ecc parity registers are cleared when a read/write command is detected or a software reset is performed. for single-bit error correction and double-bit er ror detection (sec-ded) hsiao code is used. 24-bit ecc is generated in order to perform one bit correction per 256 or 512 bytes for pages of 512/2048/4096 8-bit words. 32-bit ecc is generated in order to perform one bit correction per 512/1024/2048/4096 8- or 16-bit words.they are generated according to the schemes shown in figure 25-2 and figure 25-3 . figure 25-2. parity generation for 512/1024/2048/4096 8-bit words to calculate p8? to px? and p8 to px, apply the algorithm that follows. page size = 2 n for i =0 to n begin for (j = 0 to page_size_byte) begin if(j[i] ==1) p[2 i+3 ]=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)p[2 i+3 ] else p[2 i+3 ]?=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)p[2 i+3 ]' end end bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 p8' bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 p8 p8' p16 p16' bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 p8 p8' bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 p8 p8' p16 p16' p32 p32 1st byte p32 2nd byte 3rd byte 4 th byte page size th byte (page size -1 )th byte px px' page size = 512 px = 2048 page size = 1024 px = 4096 page size = 2048 px = 8192 page size = 4096 px = 16384 (page size -2 )th byte (page size -3 )th byte p1 p1' p1' p1 p1 p1' p1' p1 p2 p2' p2 p2' p4 p4' p1=bit7(+)bit5(+)bit3(+)bit1(+)p1 p2=bit7(+)bit6(+)bit3(+)bit2(+)p2 p4=bit7(+)bit6(+)bit5(+)bit4(+)p4 p1'=bit6(+)bit4(+)bit2(+)bit0(+)p1' p2' bit5( )bit4( )bit1( )bit0( )p2'
266 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 25-3. parity generation for 512/1024/2048/4096 16-bit words 1st word 2nd word 3rd word 4th word (page size -3 )th word (page size -2 )th word (page size -1 )th word page size th word (+) (+)
267 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary to calculate p8? to px? and p8 to px, apply the algorithm that follows. page size = 2 n for i =0 to n begin for (j = 0 to page_size_word) begin if(j[i] ==1) p[2 i+3 ]= bit15(+)bit14(+)bit13(+)bit12(+) bit11(+)bit10(+)bit9(+)bit8(+) bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)p[2 n+3 ] else p[2 i+3 ]?=bit15(+)bit14(+)bit13(+)bit12(+) bit11(+)bit10(+)bit9(+)bit8(+) bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)p[2 i+3 ]' end end
268 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.4 error corrected code cont roller (ecc) user interface table 25-1. register mapping offset register name access reset 0x00 ecc control register ecc_ctrl write-only 0x0 0x04 ecc mode register ecc_md read-write 0x0 0x08 ecc status1 register ecc_sr1 read-only 0x0 0x0c ecc parity register 0 ecc_pr0 read-only 0x0 0x10 ecc parity register 1 ecc_pr1 read-only 0x0 0x14 ecc status2 register ecc_sr2 read-only 0x0 0x18 ecc parity 2 ecc_pr2 read-only 0x0 0x1c ecc parity 3 ecc_pr3 read-only 0x0 0x20 ecc parity 4 ecc_pr4 read-only 0x0 0x24 ecc parity 5 ecc_pr5 read-only 0x0 0x28 ecc parity 6 ecc_pr6 read-only 0x0 0x2c ecc parity 7 ecc_pr7 read-only 0x0 0x30 ecc parity 8 ecc_pr8 read-only 0x0 0x34 ecc parity 9 ecc_pr9 read-only 0x0 0x38 ecc parity 10 ecc_pr10 read-only 0x0 0x3c ecc parity 11 ecc_pr11 read-only 0x0 0x40 ecc parity 12 ecc_pr12 read-only 0x0 0x44 ecc parity 13 ecc_pr13 read-only 0x0 0x48 ecc parity 14 ecc_pr14 read-only 0x0 0x4c ecc parity 15 ecc_pr15 read-only 0x0 0x14 - 0xfc reserved ? ? ?
269 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.4.1 ecc control register name: ecc_cr access type: write-only ? rst: reset parity provides reset to current ecc by software. 1: reset ecc parity registers 0: no effect ? srst: soft reset provides soft reset to ecc block 1: resets all registers. 0: no effect. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????srstrst
270 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.4.2 ecc mode register register name : ecc_mr access type : read-write ? pagesize: page size this field defines the page size of the nand flash device. a word has a value of 8 bits or 16 bits, depending on the nand flash or smartmedia memory organization. ? typecorrec: type of correction 00: 1 bit correction for a page size of 512/1024/2048/4096 bytes. 01: 1 bit correction for 256 bytes of data for a page size of 512/2048/4096 bytes. 10: 1 bit correction for 512 bytes of data for a page size of 512/2048/4096 bytes. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? typcorrec ? ? pagesize page size description 00 528 words 01 1056 words 10 2112 words 11 4224 words
271 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.4.3 ecc status register 1 register name : ecc_sr1 address: 0xffffe808 access type : read-only ? recerr0: recoverable error 0 = no errors detected. 1 = errors detected. if mul_error is 0, a single correctable error was detected. otherwise multiple uncorrected errors were detected. ? eccerr0: ecc error 0 = no errors detected. 1 = a single bit error occurred in the ecc bytes. if typecorrect = 0, read both ecc parity 0 and ecc parity 1 registers, the error occurred at the location which con- tains a 1 in the least significant 16 bits; else read ecc parity 0 register, the error occurred at the location which contains a 1 in the least significant 24 bits. ? mulerr0: multiple error 0 = no multiple errors detected. 1 = multiple errors detected. ? recerr1: recoverable error in the page between the 256th and the 511th bytes or the 512th and the 1023rd bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = errors detected. if mul_error is 0, a single correctable error was detected. otherwise multiple uncorrected errors were detected. ? eccerr1: ecc error in the page between the 256th and the 511th bytes or the 512th and the 1023rd bytes fixed to 0 if typecorrec = 0 0 = no errors detected. 1 = a single bit error occurred in the ecc bytes. read ecc parity 1 register, the error occurred at the lo cation which contains a 1 in the least significant 24 bits. ? mulerr1: multiple error in the page between the 256th and the 511th bytes or the 512th and the 1023rd bytes fixed to 0 if typecorrec = 0. 0 = no multiple errors detected. 1 = multiple errors detected. 31 30 29 28 27 26 25 24 ? mulerr7 eccerr7 recerr7 ? mulerr6 eccerr6 recerr6 23 22 21 20 19 18 17 16 ? mulerr5 eccerr5 recerr5 ? mulerr4 eccerr4 recerr4 15 14 13 12 11 10 9 8 ? mulerr3 eccerr3 recerr3 ? mulerr2 eccerr2 recerr2 76543210 ? mulerr1 eccerr1 recerr1 ? mulerr0 eccerr0 recerr0
272 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? recerr2: recoverable error in the page between the 512th and the 767th bytes or the 1024th and the 1535th bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = errors detected. if mul_error is 0, a single correct able error was detected. otherwise, multiple uncorrected errors were detected. ? eccerr2: ecc error in the page between the 512th and the 767th bytes or the 1024th and the 1535th bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = a single bit error occurred in the ecc bytes. read ecc parity 2 register, the error occurred at the lo cation which contains a 1 in the least significant 24 bits. ? mulerr2: multiple error in the page between the 512th and the 767th bytes or the 1024th and the 1535th bytes fixed to 0 if typecorrec = 0. 0 = no multiple errors detected. 1 = multiple errors detected. ? recerr3: recoverable error in the page between the 768th and the 1023rd bytes or the 1536th and the 2047th bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = errors detected. if mul_error is 0, a single correctable error was detected. otherwise multiple uncorrected errors were detected. ? eccerr3: ecc error in the page between the 768th and the 1023rd bytes or the 1536th and the 2047th bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = a single bit error occurred in the ecc bytes. read ecc parity 3 register, the error occurred at the lo cation which contains a 1 in the least significant 24 bits. ? mulerr3: multiple error in the page between the 768th and the 1023rd bytes or the 1536th and the 2047th bytes fixed to 0 if typecorrec = 0. 0 = no multiple errors detected. 1 = multiple errors detected. ? recerr4: recoverable error in the page between the 1024th and the 1279th bytes or the 2048th and the 2559th bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = errors detected. if mul_error is 0, a single correctable error was detected. otherwise multiple uncorrected errors were detected. ? eccerr4: ecc error in the page between the 1024th and the 1279th bytes or the 2048th and the 2559th bytes fixed to 0 if typecorrec = 0.
273 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 0 = no errors detected. 1 = a single bit error occurred in the ecc bytes. read ecc parity 4 register, the error occurred at the lo cation which contains a 1 in the least significant 24 bits. ? mulerr4: multiple error in the page between the 1024th and the 1279th bytes or the 2048th and the 2559th bytes fixed to 0 if typecorrec = 0. 0 = no multiple errors detected. 1 = multiple errors detected. ? recerr5: recoverable error in the page between the 1280th and the 1535th bytes or the 2560th and the 3071st bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = errors detected. if mul_error is 0, a single correctable error was detected. otherwise multiple uncorrected errors were detected ? eccerr5: ecc error in the page between the 1280th and the 1535th bytes or the 2560th and the 3071st bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = a single bit error occurred in the ecc bytes. read ecc parity 5 register, the error occurred at the lo cation which contains a 1 in the least significant 24 bits. ? mulerr5: multiple error in the page between the 1280th and the 1535th bytes or the 2560th and the 3071st bytes fixed to 0 if typecorrec = 0. 0 = no multiple errors detected. 1 = multiple errors detected. ? recerr6: recoverable error in the page between the 1536th and the 1791st bytes or the 3072nd and the 3583rd bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = errors detected. if mul_error is 0, a single correctable error was detected. otherwise multiple uncorrected errors were detected. ? eccerr6: ecc error in the page between the 1536th and the 1791st bytes or the 3072nd and the 3583rd bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = a single bit error occurred in the ecc bytes. read ecc parity 6 register, the error occurred at the lo cation which contains a 1 in the least significant 24 bits.
274 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? mulerr6: multiple error in the page between the 1536th and the 1791st bytes or the 3072nd and the 3583rd bytes fixed to 0 if typecorrec = 0. 0 = no multiple errors detected. 1 = multiple errors detected. ? recerr7: recoverable error in the page between the 1792nd and the 2047th bytes or the 3584th and the 4095th bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = errors detected. if mul_error is 0, a single correct able error was detected. otherwise, multiple uncorrected errors were detected. ? eccerr7: ecc error in the page between the 1792nd and the 2047th bytes or the 3584th and the 4095th bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = a single bit error occurred in the ecc bytes. read ecc parity 7 register, the error occurred at the lo cation which contains a 1 in the least significant 24 bits. ? mulerr7: multiple error in the page between the 1792nd and the 2047th bytes or the 3584th and the 4095th bytes fixed to 0 if typecorrec = 0. 0 = no multiple errors detected. 1 = multiple errors detected.
275 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.4.4 ecc status register 2 register name : ecc_sr2 address: 0xffffe814 access type : read-only ? recerr8: recoverable error in the page between the 2048th and the 2303rd bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = errors detected. if mul_error is 0, a single correctable error was detected. otherwise multiple uncorrected errors were detected ? eccerr8: ecc error in the page between the 2048th and the 2303rd bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = a single bit error occurred in the ecc bytes. read ecc parity 8 register, the error occurred at the lo cation which contains a 1 in the least significant 24 bits. ? mulerr8: multiple error in the page between the 2048th and the 2303rd bytes fixed to 0 if typecorrec = 0. 0 = no multiple errors detected. 1 = multiple errors detected. ? recerr9: recoverable error in the page between the 2304th and the 2559th bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = errors detected. if mul_error is 0, a single correctable error was detected. otherwise multiple uncorrected errors were detected. ? eccerr9: ecc error in the page between the 2304th and the 2559th bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = a single bit error occurred in the ecc bytes. read ecc parity 9 register, the error occurred at the lo cation which contains a 1 in the least significant 24 bits. 31 30 29 28 27 26 25 24 ? mulerr15 eccerr15 recerr15 ? mulerr14 eccerr14 recerr14 23 22 21 20 19 18 17 16 ? mulerr13 eccerr13 recerr13 ? mulerr12 eccerr12 recerr12 15 14 13 12 11 10 9 8 ? mulerr11 eccerr11 recerr11 ? mulerr10 eccerr10 recerr10 76543210 ? mulerr9 eccerr9 recerr9 ? mulerr8 eccerr8 recerr8
276 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? mulerr9: multiple error in the page between the 2304th and the 2559th bytes fixed to 0 if typecorrec = 0. 0 = no multiple errors detected. 1 = multiple errors detected. ? recerr10: recoverable error in the page between the 2560th and the 2815th bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = errors detected. if mul_error is 0, a single correct able error was detected. otherwise, multiple uncorrected errors were detected. ? eccerr10: ecc error in the page between the 2560th and the 2815th bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = a single bit error occurred in the ecc bytes. read ecc parity 10 register, the error occurred at the location which contains a 1 in the least significant 24 bits. ? mulerr10: multiple error in the page between the 2560th and the 2815th bytes fixed to 0 if typecorrec = 0. 0 = no multiple errors detected. 1 = multiple errors detected. ? recerr11: recoverable error in the page between the 2816th and the 3071st bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = errors detected.. if mul_error is 0, a single correctable error was detected. otherwise, multiple uncorrected errors were detected. ? eccerr11: ecc error in the page between the 2816th and the 3071st bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = a single bit error occurred in the ecc bytes. read ecc parity 11 register, the error occurred at the location which contains a 1 in the least significant 24 bits. ? mulerr11: multiple error in the page between the 2816th and the 3071st bytes fixed to 0 if typecorrec = 0. 0 = no multiple errors detected. 1 = multiple errors detected. ? recerr12: recoverable error in the page between the 3072nd and the 3327th bytes fixed to 0 if typecorrec = 0. 0 = no errors detected.
277 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 1 = errors detected. if mul_error is 0, a single correctable error was detected. otherwise multiple uncorrected errors were detected. ? eccerr12: ecc error in the page between the 3072nd and the 3327th bytes fixed to 0 if typecorrec = 0 0 = no errors detected 1 = a single bit error occurred in the ecc bytes. read ecc parity 12 register, the error occurred at the location which contains a 1 in the least significant 24 bits. ? mulerr12: multiple error in the page between the 3072nd and the 3327th bytes fixed to 0 if typecorrec = 0. 0 = no multiple errors detected. 1 = multiple errors detected. ? recerr13: recoverable error in the page between the 3328th and the 3583rd bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = errors detected. if mul_error is 0, a single correctable error was detected. otherwise multiple uncorrected errors were detected. ? eccerr13: ecc error in the page between the 3328th and the 3583rd bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = a single bit error occurred in the ecc bytes. read ecc parity 13 register, the error occurred at the location which contains a 1 in the least significant 24 bits. ? mulerr13: multiple error in the page between the 3328th and the 3583rd bytes fixed to 0 if typecorrec = 0. 0 = no multiple errors detected. 1 = multiple errors detected. ? recerr14: recoverable error in the page between the 3584th and the 3839th bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = errors detected. if mul_error is 0, a single correct able error was detected. otherwise, multiple uncorrected errors were detected. ? eccerr14: ecc error in the page between the 3584th and the 3839th bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = a single bit error occurred in the ecc bytes. read ecc parity 14 register, the error occurred at the location which contains a 1 in the least significant 24 bits.
278 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? mulerr14: multiple error in the page between the 3584th and the 3839th bytes fixed to 0 if typecorrec = 0. 0 = no multiple errors detected. 1 = multiple errors detected. ? recerr15: recoverable error in the page between the 3840th and the 4095th bytes fixed to 0 if typecorrec = 0. 0 = no errors detected. 1 = errors detected. if mul_error is 0, a single correct able error was detected. otherwise, multiple uncorrected errors were detected ? eccerr15: ecc error in the page between the 3840th and the 4095th bytes fixed to 0 if typecorrec = 0 0 = no errors detected. 1 = a single bit error occurred in the ecc bytes. read ecc parity 15 register, the error occurred at the location which contains a 1 in the least significant 24 bits. ? mulerr15: multiple error in the page between the 3840th and the 4095th bytes fixed to 0 if typecorrec = 0. 0 = no multiple errors detected. 1 = multiple errors detected.
279 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.5 registers for 1 ecc for a page of 512/1024/2048/4096 bytes 25.5.1 ecc parity register 0 register name : ecc_pr0 address: 0xffffe80c access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. ? bitaddr: bit address during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr: word address during a page read, this value contains the word address (8-bit or 16-bit word depending on the memory plane organiza- tion) where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 wordaddr 76543210 wordaddr bitaddr
280 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.5.2 ecc parity register 1 register name : ecc_pr1 address: 0xffffe810 access type : read-only ? nparity: parity n 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 nparity 76543210 nparity
281 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.6 registers for 1 ecc per 512 bytes for a page of 512/2048/4 096 bytes, 8-bit word 25.6.1 ecc parity register 0 register name : ecc_pr0 address: 0xffffe80c access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. ? bitaddr0: corrupted bit address in the page between the first byte and the 511th bytes during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr0: corrupted word address in the page between the first byte and the 511th bytes during a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. if multiple errors were de tected, this value is meaningless. ? nparity0: parity n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 nparity0 15 14 13 12 11 10 9 8 nparity0 wordadd0 7 6 543210 wordaddr0 bitaddr0
282 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.6.2 ecc parity register 1 register name : ecc_pr1 address: 0xffffe810 access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. ? bitaddr1: corrupted bit address in the page between the 512th an d the 1023rd bytes during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr1: corrupted word address in the pa ge between the 512th and the 1023rd bytes during a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. if multiple errors were de tected, this value is meaningless. ? nparity1: parity n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 nparity1 15 14 13 12 11 10 9 8 nparity1 wordadd1 7 6 543210 wordaddr1 bitaddr1
283 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.6.3 ecc parity register 2 register name : ecc_pr2 address: 0xffffe818 access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. ? bitaddr2: corrupted bit address in the page between the 1023rd and the 1535th bytes during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr2: corrupted word address in the page in the page between the 1023 rd and the 1535th bytes during a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. if multiple errors were de tected, this value is meaningless. ? nparity2: parity n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 nparity2 15 14 13 12 11 10 9 8 nparity2 wordadd2 7 6 543210 wordaddr2 bitaddr2
284 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.6.4 ecc parity register 3 register name : ecc_pr3 address: 0xffffe81c access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. ? bitaddr3: corrupted bit address in the pa ge between th e1536th and th e 2047th bytes during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr3 corrupted word address in the pa ge between the 1536th and the 20 47th bytes during a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. if multiple errors were de tected, this value is meaningless. ? nparity3 parity n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 nparity3 15 14 13 12 11 10 9 8 nparity3 wordadd3 7 6 543210 wordaddr3 bitaddr3
285 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.6.5 ecc parity register 4 register name : ecc_pr4 address: 0xffffe820 access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. ? bitaddr4: corrupted bit address in the page between the 2048th and the 2559th bytes during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr4: corrupted word address in the page between the 2048th and the 2559th bytes during a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. if multiple errors were de tected, this value is meaningless. ? nparity4: parity n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 nparity4 15 14 13 12 11 10 9 8 nparity4 wordadd4 7 6 543210 wordaddr4 bitaddr4
286 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.6.6 ecc parity register 5 register name : ecc_pr5 address: 0xffffe824 access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. ? bitaddr5: corrupted bit address in the page between the 2560th and the 3071st bytes during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr5: corrupted word address in the page between the 2560th and the 3071st bytes during a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. if multiple errors were de tected, this value is meaningless. ? nparity5: parity n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 nparity5 15 14 13 12 11 10 9 8 nparity5 wordadd5 7 6 543210 wordaddr5 bitaddr5
287 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.6.7 ecc parity register 6 register name : ecc_pr6 address: 0xffffe828 access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. ? bitaddr6: corrupted bit address in the page between the 3072nd an d the 3583rd bytes during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr6: corrupted word address in the pa ge between the 3072nd and the 3583rd bytes during a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. if multiple errors were de tected, this value is meaningless. ? nparity6: parity n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 nparity6 15 14 13 12 11 10 9 8 nparity6 wordadd6 7 6 543210 wordaddr6 bitaddr6
288 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.6.8 ecc parity register 7 register name : ecc_pr7 address: 0xffffe82c access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. ? bitaddr7: corrupted bit address in the page between the 3584h an d the 4095th bytes during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr7: corrupted word address in the page between the 3584th and the 4095th bytes during a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. if multiple errors were de tected, this value is meaningless. ? nparity7: parity n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 nparity7 15 14 13 12 11 10 9 8 nparity7 wordadd7 7 6 543210 wordaddr7 bitaddr7
289 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.7 registers for 1 ecc per 256 bytes for a page of 512/2048/4 096 bytes, 8-bit word 25.7.1 ecc parity register 0 register name : ecc_pr0 address: 0xffffe80c access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. ? bitaddr0: corrupted bit address in the page between the first byte and the 255th bytes during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr0: corrupted word address in the page between the first by te and the 255th bytes during a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. if multiple errors were de tected, this value is meaningless. ? nparity0: parity n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0nparity0 15 14 13 12 11 10 9 8 nparity0 0 wordadd0 7 6 543210 wordaddr0 bitaddr0
290 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.7.2 ecc parity register 1 register name : ecc_pr1 address: 0xffffe810 access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area ? bitaddr1: corrupted bit address in the pa ge between the 256th and the 511th bytes during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr1: corrupted word address in the pa ge between the 256th and the 511th bytes during a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. if multiple errors were de tected, this value is meaningless. ? nparity1: parity n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0nparity1 15 14 13 12 11 10 9 8 nparity1 0 wordadd1 7 6 543210 wordaddr1 bitaddr1
291 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.7.3 ecc parity register 2 register name : ecc_pr2 address: 0xffffe818 access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. ? bitaddr2: corrupted bit address in the pa ge between the 512th and the 767th bytes during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr2: corrupted word address in the pa ge between the 512th and the 767th bytes during a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. if multiple errors were de tected, this value is meaningless. ? nparity2: parity n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0nparity2 15 14 13 12 11 10 9 8 nparity2 0 wordadd2 7 6 543210 wordaddr2 bitaddr2
292 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.7.4 ecc parity register 3 register name : ecc_pr3 address: 0xffffe81c access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. ? bitaddr3: corrupted bit address in the page between the 768th and the 1023rd bytes during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr3: corrupted word address in the pa ge between the 768th and the 1023rd bytes during a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. if multiple errors were de tected, this value is meaningless ? nparity3: parity n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0nparity3 15 14 13 12 11 10 9 8 nparity3 0 wordadd3 7 6 543210 wordaddr3 bitaddr3
293 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.7.5 ecc parity register 4 register name : ecc_pr4 address: 0xffffe820 access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area ? bitaddr4: corrupted bit addre ss in the page between the 1024th and th e 1279th bytes during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr4: corrupted word address in the pa ge between the 1024th and the 1279th bytes during a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. if multiple errors were de tected, this value is meaningless. ? nparity4 parity n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0nparity4 15 14 13 12 11 10 9 8 nparity4 0 wordadd4 7 6 543210 wordaddr4 bitaddr4
294 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.7.6 ecc parity register 5 register name : ecc_pr5 address: 0xffffe824 access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. ? bitaddr5: corrupted bit address in the page between the 1280th and the 1535th bytes during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr5: corrupted word address in the page between the 1280th and the 1535th bytes during a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. if multiple errors were de tected, this value is meaningless. ? nparity5: parity n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0nparity5 15 14 13 12 11 10 9 8 nparity5 0 wordadd5 7 6 543210 wordaddr5 bitaddr5
295 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.7.7 ecc parity register 6 register name : ecc_pr6 address: 0xffffe828 access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. ? bitaddr6: corrupted bit addre ss in the page between the 1536th and the1791st bytes during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr6: corrupted word address in the pa ge between the 1536th and the1791st bytes during a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. if multiple errors were de tected, this value is meaningless. ? nparity6: parity n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0nparity6 15 14 13 12 11 10 9 8 nparity6 0 wordaddr6 7 6 543210 wordaddr6 bitaddr6
296 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.7.8 ecc parity register 7 register name : ecc_pr7 address: 0xffffe82c access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. ? bitaddr7: corrupted bit address in the page between the 1792nd an d the 2047th bytes during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr7: corrupted word address in the pa ge between the 1792nd and the 2047th bytes during a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. if multiple errors were de tected, this value is meaningless. ? nparity7: parity n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0nparity7 15 14 13 12 11 10 9 8 nparity7 0 wordaddr7 7 6 543210 wordaddr7 bitaddr7
297 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.7.9 ecc parity register 8 register name : ecc_pr8 address: 0xffffe830 access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. ? bitaddr8: corrupted bit address in the pa ge between the 2048th and the2303rd bytes during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr8: corrupted word address in the page between the 2048th and the 2303rd bytes during a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. if multiple errors were de tected, this value is meaningless. ? nparity8: parity n. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0nparity8 15 14 13 12 11 10 9 8 nparity8 0 wordaddr8 7 6 543210 wordaddr8 bitaddr8
298 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.7.10 ecc parity register 9 register name : ecc_pr9 address: 0xffffe834 access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area ? bitaddr9: corrupted bit addre ss in the page between the 2304th and th e 2559th bytes during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr9: corrupted word address in the pa ge between the 2304th and the 2559th bytes during a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. if multiple errors were de tected, this value is meaningless ? nparity9 parity n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0nparity9 15 14 13 12 11 10 9 8 nparity9 0 wordaddr9 7 6 543210 wordaddr9 bitaddr9
299 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.7.11 ecc parity register 10 register name : ecc_pr10 address: 0xffffe838 access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. ? bitaddr10: corrupted bit address in the page between the 2560th and the2815th bytes during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr10: corrupted word address in the page between the 2560th and the 2815th bytes during a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. if multiple errors were de tected, this value is meaningless. ? nparity10: parity n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0nparity10 15 14 13 12 11 10 9 8 nparity10 0 wordaddr10 7 6 543210 wordaddr10 bitaddr10
300 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.7.12 ecc parity register 11 register name : ecc_pr11 address: 0xffffe83c access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. ? bitaddr11: corrupted bit address in the page between the 2816th and the 3071st bytes during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr11: corrupted word address in the page between the 2816th and the 3071st bytes during a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. if multiple errors were de tected, this value is meaningless. ? nparity11: parity n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0nparity11 15 14 13 12 11 10 9 8 nparity11 0 wordaddr11 7 6 543210 wordaddr11 bitaddr11
301 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.7.13 ecc parity register 12 register name : ecc_pr12 address: 0xffffe840 access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. ? bitaddr12; corrupted bit address in the page between the 3072nd and the 3327th bytes during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr12: corrupted word address in the page between the 3072nd and the 3327th bytes during a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. if multiple errors were de tected, this value is meaningless. ? nparity12: parity n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0nparity12 15 14 13 12 11 10 9 8 nparity12 0 wordaddr12 7 6 543210 wordaddr12 bitaddr12
302 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.7.14 ecc parity register 13 register name : ecc_pr13 address: 0xffffe844 access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. ? bitaddr13: corrupted bit address in the page between the 3328th and the 3583rd bytes during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr13: corrupted word address in the page between the 3328th and the 3583rd bytes during a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. if multiple errors were de tected, this value is meaningless. ? nparity13: parity n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0nparity13 15 14 13 12 11 10 9 8 nparity13 0 wordaddr13 7 6 543210 wordaddr13 bitaddr13
303 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.7.15 ecc parity register 14 register name : ecc_pr14 address: 0xffffe848 access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. ? bitaddr14: corrupted bit address in the page between the 3584th and the 3839th bytes during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr14: corrupted word address in the page between the 3584th and the 3839th bytes during a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. if multiple errors were de tected, this value is meaningless. ? nparity14: parity n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0nparity14 15 14 13 12 11 10 9 8 nparity14 0 wordaddr14 7 6 543210 wordaddr14 bitaddr14
304 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 25.7.16 ecc parity register 15 register name : ecc_pr15 address: 0xffffe84c access type : read-only once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area ? bitaddr15: corrupted bit address in the page between the 3840th and the 4095th bytes during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr15: corrupted word address in the page between the 3840th and the 4095th bytes during a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. if multiple errors were de tected, this value is meaningless. ? nparity15 parity n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0nparity15 15 14 13 12 11 10 9 8 nparity15 0 wordaddr15 7 6 543210 wordaddr15 bitaddr15
305 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 26. peripheral dma controller (pdc) 26.1 description the peripheral dma controller (pdc) transfers data between on-chip serial peripherals and the on- and/or off-chip memories. the link betw een the pdc and a serial peripheral is operated by the ahb to abp bridge. the pdc contains 22 channels. the full-duplex peripherals feature 21 mono directional chan- nels used in pairs (transmit only or receive only). the half-duplex peripherals feature 1 bi- directional channels. the user interface of each pdc channel is integrat ed into the user interface of the peripheral it serves. the user interface of mono directional channels (receive only or transmit only), contains two 32-bit memory pointers and two 16-bit counters, one set (pointer, counter) for current trans- fer and one set (pointer, counter) for next transfer. the bi-directional channel user interface contains four 32-bit memory pointers and four 16-bit counters. each set (pointer, counter) is used by current transmit, next transmi t, current receive and next receive. using the pdc removes processor overhead by reducing its intervention during the transfer. this significantly reduces the number of clock cycles required for a data transfer, which improves microcontroller performance. to launch a transfer, the peripheral triggers its associated pdc channels by using transmit and receive signals. when the programmed data is transferred, an end of transfer interrupt is gener- ated by the peripheral itself.
306 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 26.2 block diagram figure 26-1. block diagram 26.3 functional description 26.3.1 configuration the pdc channel user interface enables the user to configure and control data transfers for each channel. the user interface of each pdc channel is integrated into the associated periph- eral user interface. the user interface of a serial peripheral, whether it is full or half duplex, contains four 32-bit pointers (rpr, rnpr, tpr, tn pr) and four 16-bit counter registers (rcr, rncr, tcr, tncr). however, the transmit and receive parts of each type are programmed differently: the pdc full duplex peripheral thr rhr pdc channel a pdc channel b control status & control control pdc channel c half duplex peripheral thr status & control receive or transmit peripheral rhr or thr control control rhr pdc channel d status & control
307 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary transmit and receive parts of a full duplex peripheral can be programmed at the same time, whereas only one part (transmit or receive) of a half duplex peripheral can be programmed at a time. 32-bit pointers define the access location in memory for current and next transfer, whether it is for read (transmit) or write (receive). 16-bit counters define the size of current and next transfers. it is possible, at any moment, to read the number of transfers left for each channel. the pdc has dedicated status registers which indica te if the transfer is enabled or disabled for each channel. the status for each channel is located in the associated peripheral status register. transfers can be enabled and/or disabled by setting txten/txtdis and rxten/rxtdis in the peripheral?s transfer control register. at the end of a transfer, the pdc channel sends status flags to its associated peripheral. these flags are visible in the peripheral status register (endrx, endtx, rxbuff, and txbufe). refer to section 26.3.3 and to the associated peripheral user interface. 26.3.2 memory pointers each full duplex peripheral is connected to the pdc by a receive channel and a transmit chan- nel. both channels have 32-bit memory pointers that point respectively to a receive area and to a transmit area in on- and/or off-chip memory. each half duplex peripheral is connected to the pdc by a bidirectional channel. this channel has two 32-bit memory pointers, one for current transfer and the other for next transfer. these pointers point to transmit or receive data depending on the operating mode of the peripheral. depending on the type of transfer (byte, half-word or word), the memory pointer is incremented respectively by 1, 2 or 4 bytes. if a memory pointer address changes in the middle of a transfer, the pdc channel continues operating using the new address. 26.3.3 transfer counters each channel has two 16-bit counters, one for current transfer and the other one for next trans- fer. these counters define the size of data to be transferred by the channel. the current transfer counter is decremented first as the data addresse d by current memory pointer starts to be trans- ferred. when the cu rrent transfer counter re aches zero, the channel checks its next transfer counter. if the value of next counter is zero, the channel stops transferring data and sets the appropriate flag. but if the next counter value is greater then zero, the values of the next pointer/next counter are copied into the current pointer/current counter and the channel resumes the transfer whereas next pointer/next counter get zero/zero as values. at the end of this trans- fer the pdc channel sets the appropriate flags in the peripheral status register. the following list gives an overview of how status register flags behave depending on the counters? values: ? endrx flag is set when the periph_rcr register reaches zero. ? rxbuff flag is set when both per iph_rcr and periph_rncr reach zero. ? endtx flag is set when the periph_tcr register reaches zero. ? txbufe flag is set when both periph_tcr and periph_tncr reach zero. these status flags are described in the peripheral status register.
308 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 26.3.4 data transfers the serial peripheral triggers its associated pdc channels? transfers using transmit enable (txen) and receive enable (rxen) flags in the transfer control register integrated in the periph- eral?s user interface. when the peripheral receives an external data, it sends a receive ready signal to its pdc receive channel which then requests access to the matrix. when access is granted, the pdc receive channel starts reading the peripheral receive holding register (rhr). the read data are stored in an internal buffer and then written to memory. when the peripheral is about to send data, it sends a transmit ready to its pdc transmit chan- nel which then requests access to the matrix. when access is granted, the pdc transmit channel reads data from memory and puts them to transmit holding regist er (thr) of its asso- ciated peripheral. the same peripheral sends data according to its mechanism. 26.3.5 pdc flags and peripheral status register each peripheral connected to the pdc sends out receive ready and transmit ready flags and the pdc sends back flags to the peripheral. all these flags are only visible in the peripheral status register. depending on the type of peripheral, half or full duplex, the flags belong to either one single channel or two different channels. 26.3.5.1 receive transfer end this flag is set when periph_rcr register reaches zero and the last data has been transferred to memory. it is reset by writing a non zero value in periph_rcr or periph_rncr. 26.3.5.2 transmit transfer end this flag is set when periph_tcr register reaches zero and the last data has been written into peripheral thr. it is reset by writing a non zero value in periph_tcr or periph_tncr. 26.3.5.3 receive buffer full this flag is set when periph_rcr register reac hes zero with periph_rncr also set to zero and the last data has been transferred to memory. it is reset by writing a non zero value in periph_tcr or periph_tncr. 26.3.5.4 transmit buffer empty this flag is set when periph_tcr register reac hes zero with periph_tncr also set to zero and the last data has been written into peripheral thr. it is reset by writing a non zero value in periph_tcr or periph_tncr.
309 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 26.4 peripheral dma controll er (pdc) user interface note: 1. periph: ten registers are mapped in the peripheral memory space at the same offset. these can be defined by the user according to the function and the peripheral desired (dbgu, usart, ssc, spi, mci, etc.) table 26-1. register mapping offset register name access reset 0x100 receive pointer register periph (1) _rpr read-write 0 0x104 receive counter register periph_rcr read-write 0 0x108 transmit pointer register periph_tpr read-write 0 0x10c transmit counter register periph_tcr read-write 0 0x110 receive next pointer register periph_rnpr read-write 0 0x114 receive next counter register periph_rncr read-write 0 0x118 transmit next pointer register periph_tnpr read-write 0 0x11c transmit next counter register periph_tncr read-write 0 0x120 transfer control register periph_ptcr write-only 0 0x124 transfer status register periph_ptsr read-only 0
310 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 26.4.1 receive pointer register register name: periph_rpr access type: read-write ? rxptr: receive pointer register rxptr must be set to receive buffer address. when a half duplex peripheral is connected to the pdc, rxptr = txptr. 31 30 29 28 27 26 25 24 rxptr 23 22 21 20 19 18 17 16 rxptr 15 14 13 12 11 10 9 8 rxptr 76543210 rxptr
311 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 26.4.2 receive counter register register name: periph_rcr access type: read-write ? rxctr: receive counter register rxctr must be set to receive buffer size. when a half duplex peripheral is connected to the pdc, rxctr = txctr. 0 = stops peripheral data transfer to the receiver 1 - 65535 = starts peripheral data transfer if corresponding channel is active 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rxctr 76543210 rxctr
312 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 26.4.3 transmit pointer register register name: periph_tpr access type: read-write ? txptr: transmit counter register txptr must be set to transmit buffer address. when a half duplex peripheral is connected to the pdc, rxptr = txptr. 26.4.4 transmit counter register register name: periph_tcr access type: read-write ? txctr: transmit counter register txctr must be set to transmit buffer size. when a half duplex peripheral is connected to the pdc, rxctr = txctr. 0 = stops peripheral data transfer to the transmitter 1- 65535 = starts peripheral data transfer if corresponding channel is active 31 30 29 28 27 26 25 24 txptr 23 22 21 20 19 18 17 16 txptr 15 14 13 12 11 10 9 8 txptr 76543210 txptr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 txctr 76543210 txctr
313 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 26.4.5 receive next pointer register register name: periph_rnpr access type: read-write ? rxnptr: receive next pointer rxnptr contains next receive buffer address. when a half duplex peripheral is connected to the pdc, rxnptr = txnptr. 26.4.6 receive next counter register register name: periph_rncr access type: read-write ? rxnctr: receive next counter rxnctr contains next receive buffer size. when a half duplex peripheral is connected to the pdc, rxnctr = txnctr. 31 30 29 28 27 26 25 24 rxnptr 23 22 21 20 19 18 17 16 rxnptr 15 14 13 12 11 10 9 8 rxnptr 76543210 rxnptr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rxnctr 76543210 rxnctr
314 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 26.4.7 transmit next pointer register register name: periph_tnpr access type: read-write ? txnptr: transmit next pointer txnptr contains next transmit buffer address. when a half duplex peripheral is connected to the pdc, rxnptr = txnptr. 26.4.8 transmit next counter register register name: periph_tncr access type: read-write ? txnctr: transmit counter next txnctr contains next transmit buffer size. when a half duplex peripheral is connected to the pdc, rxnctr = txnctr. 31 30 29 28 27 26 25 24 txnptr 23 22 21 20 19 18 17 16 txnptr 15 14 13 12 11 10 9 8 txnptr 76543210 txnptr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 txnctr 76543210 txnctr
315 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 26.4.9 transfer control register register name: periph_ptcr access type: write-only ? rxten: receiver transfer enable 0 = no effect. 1 = enables pdc receiver channel requests if rxtdis is not set. when a half duplex peripheral is connected to the pdc, en abling the receiver channel requests automatically disables the transmitter channel requests. it is forbidden to set both txten and rxten for a half duplex peripheral. ? rxtdis: receiver transfer disable 0 = no effect. 1 = disables the pdc receiver channel requests. when a half duplex peripheral is connecte d to the pdc, disabling the receiver chann el requests also disables the transmit- ter channel requests. ? txten: transmitter transfer enable 0 = no effect. 1 = enables the pdc transmitter channel requests. when a half duplex peripheral is connected to the pdc, it en ables the transmitter channel requests only if rxten is not set. it is forbidden to set both txten and rxten for a half duplex peripheral. ? txtdis: transmitter transfer disable 0 = no effect. 1 = disables the pdc transmitter channel requests. when a half duplex peripheral is connected to the pdc, dis abling the transmitter channel requests disables the receiver channel requests. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????txtdistxten 76543210 ??????rxtdisrxten
316 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 26.4.10 transfer status register register name: periph_ptsr access type: read-only ? rxten: receiver transfer enable 0 = pdc receiver channel requests are disabled. 1 = pdc receiver channel requests are enabled. ? txten: transmitter transfer enable 0 = pdc transmitter channel requests are disabled. 1 = pdc transmitter channel requests are enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????txten 76543210 ???????rxten
317 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 27. clock generator 27.1 description the clock generator is made up of 2 pll, a main oscillator, as well as an rc oscillator and a 32,768 hz low-power oscillator. it provides the following clocks: ? slck, the slow clock, which is the only permanent clock within the system ? mainck is the output of the main oscillator the clock generator user interface is embedded within the power management controller one and is described in section 28.9 . however, the clock generator registers are named ckgr_. ? pllack is the output of the divider and pll a block ? pllbck is the output of the divider and pll b block 27.2 clock generator block diagram figure 27-1. clock generator block diagram 27.3 slow clock crystal oscillator the clock generator int egrates a 32,768 hz low-power osc illator. the xin32 and xout32 pins must be connected to a 32,768 hz crystal. two external capacitors must be wired as shown in figure 27-2 . on chip rc osc power management controller xin xout pllrca slow clock slck main clock mainck plla clock pllack control status pll and divider b pllb clock pllbck xin32 xout32 slow clock oscillator main oscillator pll and divider a clock generator osc_sel
318 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 27-2. typical slow clock crystal oscillator connection 27.4 slow clock rc oscillator the user has to take into accoun t the possible drifts of the rc oscillator. more details are given in the section ?dc characteristics? of the product datasheet. 27.5 slow clock selection the at91sam9xe128/256/512 slow clock can be generated either by an external 32,768 hz crystal or the on-c hip rc oscillator. the startup counter delay for the slow clock oscillator depends on the oscsel signal. the 32,768 hz startup delay is 1200 ms whereas it is 200 s for th e internal rc oscillator. the pin oscsel must be tied either to gndbu or vddbu for correct operation of the device. refer to the slow clock selection table in the electrical characteristics section of the product datasheet for the states of the oscsel signal. 27.6 main oscillator figure 27-3 shows the main oscillator block diagram. figure 27-3. main oscillator block diagram 27.6.1 main oscillator connections the clock generator integr ates a main oscillator that is designed for a 3 to 20 mhz fundamental crystal. the typical crystal connection is illustrated in figure 27-4 . the 1 k resistor is only xin32 xout32 gndbu 32,768 hz crystal xin xout moscen main oscillator counter oscount moscs mainck main clock main clock frequency counter mainf mainrdy slck slow clock main oscillator
319 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary required for crystals with frequencies lower than 8 mhz. for further details on the electrical char- acteristics of the main oscillato r, see the sectio n ?dc characteristics? of the product datasheet. figure 27-4. typical crystal connection 27.6.2 main oscillator startup time the startup time of the main oscillator is giv en in the dc characteristics section of the product datasheet. the startup time depends on the crystal frequency and decreases when the fre- quency rises. 27.6.3 main oscillator control to minimize the power required to start up the sy stem, the main oscillator is disabled after reset and slow clock is selected. the software enable s or disables the main oscillator so as to reduce po wer consumption by clearing the moscen bit in the ma in oscillator regi ster (ckgr_mor). when disabling the main oscillator by clearin g the moscen bit in ckgr_mor, the moscs bit in pmc_sr is automatica lly cleared, indicating the main clock is off. when enabling the main oscillator, the user must initiate the ma in oscillator coun ter with a value corresponding to the startup time of the oscillat or. this startup time depends on the crystal fre- quency connected to the main oscillator. when the moscen bit and the oscount are written in ckgr_mor to enable the main oscil- lator, the moscs bit in pmc_sr (status register) is cleared and the counter starts counting down on the slow clock divided by 8 from the oscount value. since the oscount value is coded with 8 bits, the maximum startup time is about 62 ms. when the counter reaches 0, the moscs bit is set, indicating that the main clock is valid. set- ting the moscs bit in pmc_imr can trigger an interrupt to the processor. 27.6.4 main clock frequency counter the main oscillator feat ures a main clock frequen cy counter that provides the quartz frequency connected to the main oscillator. generally, this value is know n by the system designer; how- ever, it is useful for the boot program to c onfigure the device with the correct clock speed, independently of the application. the main clock frequency counter starts incrementing at the main clock speed after the next ris- ing edge of the slow clock as soon as the main oscillator is stab le, i.e., as soon as the moscs bit is set. then, at th e 16th falling edge of slow clock, the mainrdy bit in ckgr_mcfr (main 1k xin xout gnd at91 microcontroller
320 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary clock frequency register) is set and the counter stops counting. its value can be read in the mainf field of ckgr_mcfr and gives the number of main clock cycles during 16 periods of slow clock, so that the frequency of the crystal connected on the main oscillator can be determined. 27.6.5 main oscillator bypass the user can input a clock on the device instead of connecting a crystal. in this case, the user has to provide the external clock signal on the xi n pin. the input characteristics of the xin pin under these conditions are given in the product el ectrical characteristics section. the program- mer has to be sure to set the oscbypass bit to 1 and the moscen bit to 0 in the main osc register (ckgr_mor) for the external clock to operate properly. 27.7 divider and pll block the pll embeds an input divider to increase the accuracy of the resulting clock signals. how- ever, the user must respect the pll minimum input frequency when programming the divider. figure 27-5 shows the block diagram of the divider and pll blocks. figure 27-5. divider and pll block diagram 27.7.1 pll filter the pll requires connection to an external second-order filter through the pllrca and/or pll- rcb pin. figure 27-6 shows a schematic of these filters. divider b divb pll b mulb pllrca diva pll a counter pllbcount lockb pll a counter pllacount locka mula outb outa slck pllack pllbck divider a pll b mainck
321 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 27-6. pll capacitors and resistors values of r, c1 and c2 to be connected to the pllrc pin must be calculated as a function of the pll input frequency, the pll output frequency and the phase margin. a trade-off has to be found between output signal overshoot and startup time. 27.7.2 divider and phase lock loop programming the divider can be set between 1 and 255 in steps of 1. when a divider field (div) is set to 0, the output of the corresponding divider and the pll out put is a continuous signal at level 0. on reset, each div field is set to 0, thus the corresponding pll input clock is set to 0. the pll allows multiplication of the divider?s out puts. the pll clock signal has a frequency that depends on the respective source signal frequency and on the parameters div and mul. the factor applied to the source signal frequency is (mul + 1)/div. when mul is written to 0, the corresponding pll is disabled and its power consumption is saved. re-enabling the pll can be performed by writing a value higher than 0 in the mul field. whenever the pll is re-enabled or one of its parameters is changed, the lock bit (locka or lockb) in pmc_sr is automatically cleared. the values written in the pllcount field (plla- count or pllbcount) in ckgr_pllr (ckgr_ pllar or ckgr_pllbr), are loaded in the pll counter. the pll counter then decrements at the speed of the slow clock until it reaches 0. at this time, the lock bit is set in pmc_sr and can trigger an interrupt to the processor. the user has to load the number of slow clock cycles required to cover the pll transient time into the pllcount field. the transient time depends on the pll filter. the initial state of the pll and its target frequency can be calculated using a specific tool provided by atmel. during the plla or pllb initialization, the pmc_pllicpr register must be programmed correctly. gnd c1 c2 pll pllrc r
322 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 28. power management controller (pmc) 28.1 description the power management controller (pmc) optimizes power consumption by controlling all sys- tem and user peripheral clocks. the pmc enables/disables the clock inputs to many of the peripherals and the arm processor. the power management controller provides the following clocks: ? mck, the master clock, programmable from a few hundred hz to the maximum operating frequency of the device. it is available to the modules running permanently, such as the aic and the memory controller. ? processor clock (pck), must be switched off when entering processor in idle mode. ? peripheral clocks, typically mck, provided to the embedded peripherals (usart, ssc, spi, twi, tc, mci, etc.) and independently controllable. in order to reduce the number of clock names in a product, the peripheral clocks are named mck in the product datasheet. ? uhp clock (uhpck), required by usb host port operations. ? programmable clock outputs can be selected from the clocks provided by the clock generator and driven on the pckx pins. ? five flexible operating modes: ? normal mode, processor and peripherals running at a programmable frequency ? idle mode, processor stopped waiting for an interrupt ? slow clock mode, processor and peripherals running at low frequency ? standby mode, mix of idle and backup mode, peripheral running at low frequency, processor stopped waiting for an interrupt ? backup mode, main power supplies off, vddbu powered by a battery figure 28-1. at91sam9xe128/256/512 power management controller block diagram mck periph_clk[..] int slck mainck pllack prescaler /1,/2,/4,...,/64 pck processor clock controller idle mode master clock controller peripherals clock controller on/off pllbck divider /1,/2,/4 usb clock controller slck mainck pllack prescaler /1,/2,/4,...,/64 programmable clock controller pllbck divider /1,/2,/4 pck[..] pllbck udpck on/off on/off uhpck
323 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 28.2 master clock controller the master clock controller provides selection and division of the master clock (mck). mck is the clock provided to all the peripherals and the memory controller. the master clock is selected from one of the clocks provided by the clock generator. selecting the slow clock provides a slow clock signal to the whole device. selecting the main clock saves power consumption of the plls. the master clock controller is made up of a cloc k selector and a prescaler. it also contains a master clock divider which allows the processor clock to be faster than the master clock. the master clock selection is made by writi ng the css field (clock source selection) in pmc_mckr (master clock register). the prescaler supports the division by a power of 2 of the selected clock between 1 and 64. the pres field in pmc_mckr programs the prescaler. the master clock divider can be programmed through the mdiv field in pmc_mckr. each time pmc_mckr is written to define a ne w master clock, the mckr dy bit is cleared in pmc_sr. it reads 0 until the master clock is es tablished. then, the mckrdy bit is set and can trigger an interrupt to the processor. this feature is useful when switching from a high-speed clock to a lower one to inform the software when the change is actually done. figure 28-2. master clock controller 28.3 processor clock controller the pmc features a processor clock controller (pck) that implements the processor idle mode. the processor clock can be disabled by writing the system clock disable register (pmc_scdr). the status of this clock (at least for debug purposes) can be read in the system clock status register (pmc_scsr). the processor clock pck is enabled after a reset and is automatically re-enabled by any enabled interrupt. the processor idle mode is ac hieved by disabling the processor clock and entering wait for interrupt mode. the processor clock is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product. note: the arm wait for interrupt mode is entered with cp15 coprocessor operation. refer to the atmel application note, optimizing power consumption fo at91sam9261-based systems , lit. number 6217. when the processor clock is disabled, the curr ent instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus. slck master clock prescaler mck pres css master clock divider mainck pllack pllbck mdiv to the processor clock controller (pck) pmc_mckr pmc_mckr pmc_mckr
324 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 28.4 usb clock controller the usb source clock is always generated from the pll b output. if using the usb, the user must program the pll to generate a 48 mhz, a 96 mhz or a 192 mhz signal with an accuracy of 0.25% depending on the usbdiv bit in ckgr_pllbr (see figure 28-3 ). when the pll b output is stable, i.e., the lockb is set: ? the usb host clock can be enabled by setting the uhp bit in pmc_scer. to save power on this peripheral when it is not used, the user can set the uhp bit in pmc_scdr. the uhp bit in pmc_scsr gives the activity of this clock. the usb host port require both the 12/48 mhz signal and the master clock. the master clock may be controlled via the master clock controller. figure 28-3. usb clock controller 28.5 peripheral clock controller the power management controller controls the clocks of each embedded peripheral by the way of the peripheral clock controller. the user can individually enable and disable the master clock on the peripherals by writing into the peripheral clock enable (pmc_pcer) and periph- eral clock disable (pmc_pcdr) registers. the status of the peripheral clock activity can be read in the peripheral clock status register (pmc_pcsr). when a peripheral clock is disabled, the clock is immediately stopped. the peripheral clocks are automatically disabled after a reset. in order to stop a peri pheral, it is recommended that the syst em software wait until the peripheral has executed its last programmed operation before disabling the clock. this is to avoid data cor- ruption or erroneous behavior of the system. the bit number within the peripheral clock control registers (pmc_pcer, pmc_pcdr, and pmc_pcsr) is the peripheral identifier defined at the product level. generally, the bit number corresponds to the interrupt source number assigned to the peripheral. 28.6 programmable clock output controller the pmc controls 2 signals to be output on external pi ns pckx. each signal can be indepen- dently programmed via the pmc_pckx registers. pckx can be independently selected between the slow clock, the pll a output, the pll b out- put and the main clock by writing the css field in pmc_pckx. each output signal can also be divided by a power of 2 between 1 and 64 by wr iting the pres (prescaler) field in pmc_pckx. each output signal can be enabled and disabled by writing 1 in the corresponding bit, pckx of pmc_scer and pmc_scdr, respectively. status of the active programmable output clocks are given in the pckx bits of pmc_scsr (system clock status register). usb source clock udp clock (udpck) udp usbdiv divider /1,/2,/4 uhp clock (uhpck) uhp
325 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary moreover, like the pck, a status bitin pmc_sr indicates that the programmable clock is actu- ally what has been programmed in the programmable clock registers. as the programmable clock controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disable the programmable clock before any configuration change and to re-enable it after the change is actually performed. 28.7 programming sequence 1. enabling the main oscillator: the main oscillator is enabled by setting the moscen field in the ckgr_mor register. in some cases it may be advantageous to define a st art-up time. this can be achieved by writ- ing a value in the oscount field in the ckgr_mor register. once this register has been correctly configured, the user must wait for moscs field in the pmc_sr register to be se t. this can be done either by pollin g the status regist er or by wait- ing the interrupt line to be raised if the associated interrupt to moscs has been enabled in the pmc_ier register. code example: write_register(ckgr_mor,0x00000701) start up time = 8 * oscount / slck = 56 slow clock cycles. so, the main oscillator will be enabled (moscs bit set) after 56 slow clock cycles. 2. checking the main oscilla tor frequency (optional): in some situations the user may need an accu rate measure of the ma in oscillator frequency. this measure can be accomplished via the ckgr_mcfr register. once the mainrdy field is set in ckgr_mcfr register, the user may read the mainf field in ckgr_mcfr register. this provides the num ber of main clock cycles within sixteen slow clock cycles. 3. setting pll a and divider a: all parameters necessary to configure pll a and divider a are located in the ckgr_pllar register. icpplla in pmc_pllicpr register must be set to 1 before configuring the ckgr_pllar register. it is important to note that bit 29 must always be set to 1 when programming the ckgr_pllar register. the diva field is used to control the divider a itself. the user can program a value between 0 and 255. divider a output is divider a input divided by diva. by default, diva parameter is set to 0 which means that divider a is turned off. the outa field is used to select the pll a output frequency range. the mula field is the pll a multiplier factor. this parameter can be programmed between 0 and 2047. if mula is set to 0, pll a will be turned off. ot herwise pll a output frequency is pll a input frequency multiplied by (mula + 1). the pllacount field specifies the number of slow clock cycles before locka bit is set in the pmc_sr register after ckgr_pllar register has been written. once ckgr_pllar register has been written, the user is obliged to wait for the locka bit to be set in the pmc_sr register. this can be done either by polling the status register or by
326 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary waiting the interrupt line to be raised if the associated interrupt to locka has been enabled in the pmc_ier register. all parameters in ckgr_pllar can be programmed in a single write operation. if at some stage one of the following par ameters, srca, mula, diva is modified, locka bit will go low to indicate that pll a is not ready yet. when pll a is locked, locka will be set again. user has to wait for locka bit to be set before using the pll a output clock. code example: write_register(ckgr_pllar,0x20030605) pll a and divider a are enabled. pll a input clock is main clock divided by 5. pll an out- put clock is pll a input clock multiplied by 4. once ckgr_pllar has been written, locka bit will be set after six slow clock cycles. 4. setting pll b and divider b: all parameters needed to configure pll b and divider b are located in the ckgr_pllbr register. icppllb in pmc_pllicpr register must be set to 1 before configuring the ckgr_pllbr register. the divb field is used to control divider b itself. a value between 0 and 255 can be pro- grammed. divider b output is divider b input divided by divb parameter. by default divb parameter is set to 0 which means that divider b is turned off. the outb field is used to select the pll b output frequency range. the mulb field is the pll b multiplier factor. this parameter can be programmed between 0 and 2047. if mulb is set to 0, pll b will be turned off, otherwis e the pll b output fre- quency is pll b input frequency multiplied by (mulb + 1). the pllbcount field specifies the number of slow clock cycles before lockb bit is set in the pmc_sr register after ckgr_pllbr register has been written. once the pmc_pllb register has been written, the user must wait for the lockb bit to be set in the pmc_sr register. this can be done eith er by polling the status register or by wait- ing the interrupt line to be raised if the associated interrupt to lockb has been enabled in the pmc_ier register. all parameters in ckgr_pllbr can be programmed in a single write operation. if at some stage one of the following parameters, mulb, divb is modified, lockb bit will go low to indicate that pll b is not ready yet. when pl l b is locked, lockb will be set again. the user is constrained to wait for lockb bit to be set before using the pll a output clock. the usbdiv field is used to control the additional divider by 1, 2 or 4, which generates the usb clock(s). code example: write_register(ckgr_pllbr,0x00040805) if pll b and divider b are enabled, the pll b in put clock is the main clock. pll b output clock is pll b input clock multiplied by 5. once ckgr_pllbr has been written, lockb bit will be set after eight slow clock cycles. 5. selection of master clock and processor clock the master clock and the processor clock are configurable via the pmc_mckr register.
327 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary the css field is used to select the master clock divider source. by default, the selected clock source is slow clock. the pres field is used to control the master clock prescaler. the user can choose between different values (1, 2, 4, 8, 16, 32, 64). master clock output is prescaler input divided by pres parameter. by default, pres parameter is set to 0 which means that master clock is equal to slow clock. the mdiv field is used to control the master clock divider. it is possible to choose between different values (0, 1, 2). the master clock outp ut is processor clock divided by 1, 2 or 4, depending on the value programmed in mdiv. by default, mdiv is set to 0, which indicates that the processor clock is equal to the master clock. once the pmc_mckr register has been written, the user must wait for the mckrdy bit to be set in the pmc_sr register. this can be done either by polling the status register or by waiting for the interrupt line to be raised if the associated interrupt to mckrdy has been enabled in the pmc_ier register. the pmc_mckr register must not be programmed in a single write operation. the pre- ferred programming sequence for the pmc_mckr register is as follows: ? if a new value for css field corresponds to pll clock, ? program the pres field in the pmc_mckr register. ? wait for the mckrdy bit to be set in the pmc_sr register. ? program the css field in the pmc_mckr register. ? wait for the mckrdy bit to be set in the pmc_sr register. ? if a new value for css field corresponds to main clock or slow clock, ? program the css field in the pmc_mckr register. ? wait for the mckrdy bit to be set in the pmc_sr register. ? program the pres field in the pmc_mckr register. ? wait for the mckrdy bit to be set in the pmc_sr register. if at some stage one of the following parameters, css or pres, is modified, the mckrdy bit will go low to indicate that the master clock and the processor clock are not ready yet. the user must wait for mckrdy bit to be set again before using the master and processor clocks. note: if pllx clock was selected as the master clock and the user decides to modify it by writing in ckgr_pllr (ckgr_pllar or ckgr_pllbr), the mckrdy flag will go low while pll is unlocked. once pll is locked again, lock (locka or lockb) goes high and mckrdy is set. while plla is unlocked, the master clock selection is automatically changed to slow clock. while pllb is unlocked, the master clock selection is automatically changed to main clock. for further information, see section 28.8.2 . ?clock switching waveforms? on page 331 . code example: write_register(pmc_mckr,0x00000001) wait (mckrdy=1) write_register(pmc_mckr,0x00000011) wait (mckrdy=1)
328 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary the master clock is main clock divided by 16. the processor clock is the master clock. 6. selection of programmable clocks programmable clocks are controlled via registers; pmc_scer, pmc_scdr and pmc_scsr. programmable clocks can be enabled and/or disabled via the pmc_scer and pmc_scdr registers. depending on the system used, 2 programmable clocks can be enabled or dis- abled. the pmc_scsr provides a clear indi cation as to which programmable clock is enabled. by default all programmable clocks are disabled. pmc_pckx registers are used to configure programmable clocks. the css field is used to select the program mable clock divider sour ce. four clock options are available: main clock, slow clock, pl lack, pllbck. by default, the clock source selected is slow clock. the pres field is used to control the programmable clock prescaler. it is possible to choose between different values (1, 2, 4, 8, 16, 32, 64). programmable clock output is prescaler input divided by pres parameter. by default, the pres parameter is set to 0 which means that master clock is equal to slow clock. once the pmc_pckx register has been programmed, the corresponding programmable clock must be enabled and the user is constrai ned to wait for the pckrdyx bit to be set in the pmc_sr register. this can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to pckrdyx has been enabled in the pmc_ier register. all parameters in pmc_ pckx can be programmed in a single write operation. if the css and pres parameters are to be modified, the corresponding programmable clock must be disabled first. the parameters can then be modified. once this has been done, the user must re-enable the programmable clock and wait for the pckrdyx bit to be set. code example: write_register(pmc_pck0,0x00000015) programmable clock 0 is main clock divided by 32. 7. enabling peripheral clocks once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via registers pmc_pcer and pmc_pcdr. depending on the system used, 17 peripheral clocks can be enabled or disabled. the pmc_pcsr provides a clear view as to which peripheral clock is enabled. note: each enabled peripheral clock corresponds to master clock. code examples:
329 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary write_register(pmc_pcer,0x00000110) peripheral clocks 4 and 8 are enabled. write_register(pmc_pcdr,0x00000010) peripheral clock 4 is disabled.
330 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 28.8 clock switching details 28.8.1 master clock switching timings table 28-1 and table 28-2 give the worst case timings requ ired for the master clock to switch from one selected clock to another one. this is in the event that the prescaler is de-activated. when the prescaler is activated, an additional ti me of 64 clock cycles of the new selected clock has to be added. notes: 1. pll designates either the pll a or the pll b clock. 2. pllcount designates either pllacount or pllbcount. table 28-1. clock switching timings (worst case) from main clock slck pll clock to main clock ? 4 x slck + 2.5 x main clock 3 x pll clock + 4 x slck + 1 x main clock slck 0.5 x main clock + 4.5 x slck ? 3 x pll clock + 5 x slck pll clock 0.5 x main clock + 4 x slck + pllcount x slck + 2.5 x pllx clock 2.5 x pll clock + 5 x slck + pllcount x slck 2.5 x pll clock + 4 x slck + pllcount x slck table 28-2. clock switching timings between two plls (worst case) from plla clock pllb clock to plla clock 2.5 x plla clock + 4 x slck + pllacount x slck 3 x plla clock + 4 x slck + 1.5 x plla clock pllb clock 3 x pllb clock + 4 x slck + 1.5 x pllb clock 2.5 x pllb clock + 4 x slck + pllbcount x slck
331 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 28.8.2 clock switching waveforms figure 28-4. switch master clock from slow clock to pll clock figure 28-5. switch master clock from main clock to slow clock slow clock lock mckrdy master clock write pmc_mckr pll clock slow clock main clock mckrdy master clock write pmc_mckr
332 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 28-6. change plla programming figure 28-7. change pllb programming slow clock slow clock plla clock lock mckrdy master clock write ckgr_pllar main clock main clock pllb clock lock mckrdy master clock write ckgr_pllbr
333 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 28-8. programmable clock output programming pll clock pckrdy pckx output write pmc_pckx write pmc_scer write pmc_scdr pckx is disabled pckx is enabled pll clock is selected
334 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 28.9 power management contro ller (pmc) user interface table 28-3. register mapping offset register name access reset 0x0000 system clock enable register pmc_scer write-only ? 0x0004 system clock disable register pmc_scdr write-only ? 0x0008 system clock status register pmc _scsr read-only 0x03 0x000c reserved ? ? ? 0x0010 peripheral clock enable register pmc _pcer write-only ? 0x0014 peripheral clock disable register pmc_pcdr write-only ? 0x0018 peripheral clock status register pmc_pcsr read-only 0x0 0x001c reserved ? ? ? 0x0020 main oscillator register ckgr_mor read-write 0x0 0x0024 main clock frequency register ckgr_mcfr read-only 0x0 0x0028 pll a register ckgr_pllar readwrite 0x3f00 0x002c pll b register ckgr_pllbr readwrite 0x3f00 0x0030 master clock register pmc_mckr read-write 0x0 0x0038 reserved ? ? ? 0x003c reserved ? ? ? 0x0040 programmable clock 0 register pmc_pck0 read-write 0x0 0x0044 programmable clock 1 register pmc_pck1 read-write 0x0 ... ... ... ... ... 0x0060 interrupt enable register pmc_ier write-only -- 0x0064 interrupt disable register pmc_idr write-only -- 0x0068 status register pmc_sr read-only 0x08 0x006c interrupt mask register pmc_imr read-only 0x0 0x0070 - 0x007c reserved ? ? ? 0x0080 charge pump current regi ster pmc_pllicpr write-only -- 0x0084 - 0x00fc reserved ? ? ?
335 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 28.9.1 pmc system clock enable register register name: pmc_scer address: 0xfffffc00 access type: write-only ? uhp: usb host port clock enable 0 = no effect. 1 = enables the 12 and 48 mhz clock of the usb host port. ? udp: usb device port clock enable 0 = no effect. 1 = enables the 48 mhz clock of the usb device port. ? pckx: programmable clock x output enable 0 = no effect. 1 = enables the corresponding programmable clock output. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????pck1pck0 76543210 udpuhp??????
336 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 28.9.2 pmc system clock disable register register name: pmc_scdr address: 0xfffffc04 access type: write-only ? pck: processor clock disable 0 = no effect. 1 = disables the processor clock. this is used to enter the processor in idle mode. ? uhp: usb host port clock disable 0 = no effect. 1 = disables the 12 and 48 mhz clock of the usb host port. ? udp: usb device port clock disable 0 = no effect. 1 = disables the 48 mhz clock of the usb device port. ? pckx: programmable clock x output disable 0 = no effect. 1 = disables the corresponding programmable clock output. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????pck1pck0 76543210 udpuhp?????pck
337 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 28.9.3 pmc system clock status register register name: pmc_scsr address: 0xfffffc08 access type: read-only ? pck: processor clock status 0 = the processor clock is disabled. 1 = the processor clock is enabled. ? uhp: usb host port clock status 0 = the 12 and 48 mhz clock (uhpck) of the usb host port is disabled. 1 = the 12 and 48 mhz clock (uhpck) of the usb host port is enabled. ? udp: usb device port clock status 0 = the 48 mhz clock (udpck) of th e usb device port is disabled. 1 = the 48 mhz clock (udpck) of the usb device port is enabled. ? pckx: programmable clock x output status 0 = the corresponding programmable clock output is disabled. 1 = the corresponding programmable clock output is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????pck1pck0 76543210 udpuhp?????pck
338 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 28.9.4 pmc peripheral clock enable register register name: pmc_pcer address: 0xfffffc10 access type: write-only ? pidx: peripheral clock x enable 0 = no effect. 1 = enables the corresponding peripheral clock. note: pid2 to pid31 refer to identifiers as defined in the section ?peripheral identifiers ? in the product datasheet. note: programming the control bits of the peripheral id that ar e not implemented has no effect on the behavior of the pmc. 28.9.5 pmc peripheral clock disable register register name: pmc_pcdr address: 0xfffffc14 access type: write-only ? pidx: peripheral clock x disable 0 = no effect. 1 = disables the corresponding peripheral clock. note: pid2 to pid31 refer to identifiers as defined in the section ?peripheral identifiers ? in the product datasheet. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 - - 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 - -
339 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 28.9.6 pmc peripheral clock status register register name: pmc_pcsr address: 0xfffffc18 access type: read-only ? pidx: peripheral clock x status 0 = the corresponding peripheral clock is disabled. 1 = the corresponding peripheral clock is enabled. note: pid2 to pid31 refer to identifiers as defined in the section ?peripheral identifiers ? in the product datasheet. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 ? ?
340 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 28.9.7 pmc clock generator main oscillator register register name: ckgr_mor address: 0xfffffc20 access type: read-write ? moscen: main oscillator enable a crystal must be connected between xin and xout. 0 = the main oscillator is disabled. 1 = the main oscillator is enabl ed. oscbypass must be set to 0. when moscen is set, the moscs flag is set once the main oscillator startup time is achieved. ? oscbypass: oscillator bypass 0 = no effect. 1 = the main oscillator is bypassed. moscen must be set to 0. an exter nal clock must be connected on xin. when oscbypass is set, th e moscs flag in pmc_sr is automatically set. clearing moscen and oscbypass bits allows resetting the moscs flag. ? oscount: main oscillator start-up time specifies the number of slow clock cycles multip lied by 8 for the main o scillator start-up time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 oscount 76543210 ??????oscbypassmoscen
341 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 28.9.8 pmc clock generator main clock frequency register register name: ckgr_mcfr address: 0xfffffc24 access type: read-only ? mainf: main clock frequency gives the number of main clock cycles within 16 slow clock periods. ? mainrdy: main clock ready 0 = mainf value is not valid or the main oscillator is disabled. 1 = the main oscillator has been enabled pr eviously and mainf value is available. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????mainrdy 15 14 13 12 11 10 9 8 mainf 76543210 mainf
342 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 28.9.9 pmc clock generator pll a register register name: ckgr_pllar address: 0xfffffc28 access type: read-write possible limitations on pll a input frequencies and multiplier factors should be checked before using the pmc. warning: bit 29 must always be set to 1 when programming the ckgr_pllar register. ? diva: divider a ? pllacount: pll a counter specifies the number of slow clock cycles before the lo cka bit is set in pmc_sr af ter ckgr_pllar is written. ? outa: pll a clock frequency range to optimize clock performance, this field must be programmed as specified in ?pll characteristics? in the electrical char- acteristics section of the product datasheet. ? mula: pll a multiplier 0 = the pll a is deactivated. 1 up to 2047 = the pll a clock frequency is the pll a input frequency multiplied by mula + 1. 31 30 29 28 27 26 25 24 ??1?? mula 23 22 21 20 19 18 17 16 mula 15 14 13 12 11 10 9 8 outa pllacount 76543210 diva diva divider selected 0 divider output is 0 1 divider is bypassed 2 - 255 divider output is the main clock divided by diva.
343 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 28.9.10 pmc clock generator pll b register register name: ckgr_pllbr address: 0xfffffc2c access type: read-write possible limitations on pll b input frequencies and multiplier factors should be checked before using the pmc. ? divb: divider b ? pllbcount: pll b counter specifies the number of slow clock cycles before the lo ckb bit is set in pmc_sr after ckgr_pllbr is written. ? outb: pllb clock frequency range to optimize clock performance, this field must be programmed as specified in ?pll characteristics? in the electrical char- acteristics section of the product datasheet. ? mulb: pll multiplier 0 = the pll b is deactivated. 1 up to 2047 = the pll b clock frequency is the pll b input frequency multiplied by mulb + 1. ? usbdiv: divider for usb clock 31 30 29 28 27 26 25 24 ? ? usbdiv ? mulb 23 22 21 20 19 18 17 16 mulb 15 14 13 12 11 10 9 8 outb pllbcount 76543210 divb divb divider selected 0 divider output is 0 1 divider is bypassed 2 - 255 divider output is the selected clock divided by divb. usbdiv divider for usb clock(s) 0 0 divider output is pll b clock output. 0 1 divider output is pll b clock output divided by 2. 1 0 divider output is pll b clock output divided by 4. 1 1 reserved.
344 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 28.9.11 pmc master clock register register name: pmc_mckr address: 0xfffffc30 access type: read-write ? css: master clock selection ? pres: processor clock prescaler ? mdiv: master clock division 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? mdiv 76543210 ? ? ? pres css css clock source selection 0 0 slow clock is selected 0 1 main clock is selected 1 0 pll a clock is selected 1 1 pll b clock is selected pres processor clock 0 0 0 selected clock 0 0 1 selected clock divided by 2 0 1 0 selected clock divided by 4 0 1 1 selected clock divided by 8 1 0 0 selected clock divided by 16 1 0 1 selected clock divided by 32 1 1 0 selected clock divided by 64 111reserved mdiv master clock division 0 0 master clock is processor clock. 0 1 master clock is processor clock divided by 2. 1 0 master clock is processor clock divided by 4. 1 1 reserved.
345 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 28.9.12 pmc programmable clock register register name: pmc_pckx address: 0xfffffc40 access type: read-write ? css: master clock selection ? pres: programmable clock prescaler 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? pres css css clock source selection 0 0 slow clock is selected 0 1 main clock is selected 1 0 pll a clock is selected 1 1 pll b clock is selected pres programmable clock 0 0 0 selected clock 0 0 1 selected clock divided by 2 0 1 0 selected clock divided by 4 0 1 1 selected clock divided by 8 1 0 0 selected clock divided by 16 1 0 1 selected clock divided by 32 1 1 0 selected clock divided by 64 111reserved
346 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 28.9.13 pmc interrupt enable register register name: pmc_ier address: 0xfffffc60 access type: write-only ? moscs: main oscillator status interrupt enable ? locka: pll a lock interrupt enable ? lockb: pll b lock interrupt enable ? mckrdy: master clock ready interrupt enable ? pckrdyx: programmable clock ready x interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????pckrdy1pckrdy0 76543210 ????mckrdylockblockamoscs
347 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 28.9.14 pmc interrupt disable register register name: pmc_idr address: 0xfffffc64 access type: write-only ? moscs: main oscillator status interrupt disable ? locka: pll a lock interrupt disable ? lockb: pll b lock interrupt disable ? mckrdy: master clock ready interrupt disable ? pckrdyx: programmable clock ready x interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????pckrdy1pckrdy0 76543210 ? ???mckrdy lockb locka moscs
348 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 28.9.15 pmc status register register name: pmc_sr address: 0xfffffc68 access type: read-only ? moscs: moscs flag status 0 = main oscillator is not stabilized. 1 = main oscillator is stabilized. ? locka: pll a lock status 0 = pll a is not locked 1 = pll a is locked. ? lockb: pll b lock status 0 = pll b is not locked. 1 = pll b is locked. ? mckrdy: master clock status 0 = master clock is not ready. 1 = master clock is ready. ? osc_sel: slow clock oscillator selection 0 = internal slow clock rc oscillator. 1 = external slow clock 32 khz oscillator. ? pckrdyx: programmable clock ready status 0 = programmable clock x is not ready. 1 = programmable clock x is ready. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????pckrdy1pckrdy0 76543210 osc_sel ? ? ? mckrdy lockb locka moscs
349 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 28.9.16 pmc interrupt mask register register name: pmc_imr address: 0xfffffc6c access type: read-only ? moscs: main oscillator status interrupt mask ? locka: pll a lock interrupt mask ? lockb: pll b lock interrupt mask ? mckrdy: master clock ready interrupt mask ? pckrdyx: programmable clock ready x interrupt mask 0 = the corresponding interrupt is enabled. 1 = the corresponding interrupt is disabled 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????pckrdy1pckrdy0 76543210 ? ???mckrdy lockb locka moscs
350 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 28.9.17 .pll charge pump current register register name: pmc_pllicpr address: 0xfffffc80 access type: write-only ? icpplla: charge pump current must be set to 1. ? icppllb: charge pump current must be set to 1. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????icppllb 15 14 13 12 11 10 9 8 ???????? 76543210 ???????icpplla
351 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 29. advanced interrupt controller (aic) 29.1 description the advanced interrupt controller (aic) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. it is designed to sub- stantially reduce the software and real-time overhead in handling internal and external interrupts. the aic drives the nfiq (fast interrupt request) and the nirq (standard interrupt request) inputs of an arm processor. inputs of the aic are either internal peripheral interrupts or external inter- rupts coming from the product's pins. the 8-level priority controller allows the user to define the priority for each interrupt source, thus permitting higher priority interrupts to be serviced even if a lower priority interrupt is being treated. internal interrupt sources can be programmed to be level sensitive or edge triggered. external interrupt sources can be programmed to be positive-edge or negative-edge triggered or high- level or low-level sensitive. the fast forcing feature redirects any internal or external interrupt source to provide a fast inter- rupt rather than a normal interrupt.
352 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 29.2 block diagram figure 29-1. block diagram 29.3 application block diagram figure 29-2. description of the application block 29.4 aic detailed block diagram figure 29-3. aic detailed block diagram aic apb arm processor fiq irq0-irqn embedded peripheralee peripheral embedded peripheral embedded up to thirty-two sources nfiq nirq advanced interrupt controller embedded peripherals external peripherals (external interrupts) standalone applications rtos drivers hard real time tasks os-based applications os drivers general os interrupt handler fiq pio controller advanced interrupt controller irq0-irqn pioirq embedded peripherals external source input stage internal source input stage fast forcing interrupt priority controller fast interrupt controller arm processor nfiq nirq power management controller wake up user interface apb processor clock
353 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 29.5 i/o line description 29.6 product dependencies 29.6.1 i/o lines the interrupt signals fiq and irq0 to irqn are normally multiplexed through the pio control- lers. depending on the features of the pio controller used in the product, the pins must be programmed in accordance with their assigned interrupt function. this is not applicable when the pio controller used in the product is transparent on the input path. 29.6.2 power management the advanced interrupt controller is continuously clocked. the power management controller has no effect on the advanced interrupt controller behavior. the assertion of the advanced interrupt controller outputs, either nirq or nfiq, wakes up the arm processor while it is in idle mode. the general interrupt mask feature enables the aic to wake up the processor without asserting the interr upt line of the processor, thus providing syn- chronization of the processor on an event. 29.6.3 interrupt sources the interrupt source 0 is always located at fiq. if the product does not feature an fiq pin, the interrupt source 0 cannot be used. the interrupt source 1 is always located at system interrupt. this is the result of the or-wiring of the system peripheral interrupt lines. when a system interrupt occurs, the service routine must first distinguish the cause of the interrupt . this is performed by reading successively the status registers of the above mentioned system peripherals. the interrupt sources 2 to 31 can either be connected to the interrupt outputs of an embedded user peripheral or to external interrupt lines . the external interrupt lines can be connected directly, or through the pio controller. the pio controllers are considered as user peripherals in the scope of interrupt handling. accordingly, the pio controller interrupt lines are connected to the interrupt sources 2 to 31. the peripheral identification defined at the product level corresponds to the interrupt source number (as well as the bit number controlling the clock of the peri pheral). conseq uently, to sim- plify the description of the functional operations and the user interface, the interrupt sources are named fiq, sys, and pid2 to pid31. table 29-1. i/o line description pin name pin description type fiq fast interrupt input irq0 - irqn interrupt 0 - interrupt n input
354 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 29.7 functional description 29.7.1 interrupt source control 29.7.1.1 interrupt source mode the advanced interrupt controller independently programs each interrupt source. the src- type field of the corresponding aic_smr (source mode register) selects the interrupt condition of each source. the internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode. the active level of the internal interrupts is not important for the user. the external interrupt sources can be programmed either in high level-sensitive or low level-sen- sitive modes, or in positive edge-triggered or negative edge-triggered modes. 29.7.1.2 interrupt source enabling each interrupt source, including the fiq in source 0, can be enabled or disabled by using the command registers; aic_iecr (interrupt enable command register) and aic_idcr (interrupt disable command register). this set of registers conducts enabling or disabling in one instruc- tion. the interrupt mask can be read in the aic_imr register. a disabled interrupt does not affect servicing of other interrupts. 29.7.1.3 interrupt clearing and setting all interrupt sources programmed to be edge-triggered (including the fiq in source 0) can be individually set or cleared by writing respectively the aic_iscr and aic_iccr registers. clear- ing or setting interrupt sources programmed in level-sensitive mode has no effect. the clear operation is perfunctory, as the softwa re must perform an acti on to reinitialize the ?memorization? circuitry activated when the source is programmed in edge-triggered mode. however, the set operation is available for auto-test or software debug purposes. it can also be used to execute an aic-implementation of a software interrupt. the aic features an automatic clear of the current interrupt when the aic_ivr (interrupt vector register) is read. only the interrupt source being detected by the aic as the current interrupt is affected by this operation. ( see ?priority controller? on page 357. ) the automatic clear reduces the operations required by the interrupt service routine entry code to reading the aic_ivr. note that the automatic interrupt clear is disabled if the interrupt source has the fast forcing feature enabled as it is considered uniquely as a fiq source. (for further details, see ?fast forcing? on page 361. ) the automatic clear of the interrupt source 0 is performed when aic_fvr is read. 29.7.1.4 interrupt status for each interrupt, the aic operation originates in aic_ipr (interrupt pending register) and its mask in aic_imr (interrupt mask register). aic_ipr enables the actual activity of the sources, whether masked or not. the aic_isr register reads the number of the current interrupt (see ?priority controller? on page 357 ) and the register aic_cisr gives an image of the signals nirq and nfiq driven on the processor. each status referred to above can be used to optimize the interrupt handling of the systems.
355 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 29.7.1.5 internal interrupt source input stage figure 29-4. internal interrupt source input stage 29.7.1.6 external interrupt source input stage figure 29-5. external interrupt source input stage edge detector clear set source i aic_ipr aic_imr aic_iecr aic_idcr aic_iscr aic_iccr fast interrupt controller or priority controller ff level/ edge aic_smri (srctype) edge detector clear set pos./neg. aic_iscr aic_iccr source i ff level/ edge high/low aic_smri srctype aic_ipr aic_imr aic_iecr aic_idcr fast interrupt controller or priority controller
356 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 29.7.2 interrupt latencies global interrupt latencies depend on several parameters, including: ? the time the software masks the interrupts. ? occurrence, either at the processor level or at the aic level. ? the execution time of the instruction in progress when the interrupt occurs. ? the treatment of higher priority interrupts and the resynchronization of the hardware signals. this section addresses only the hardware resync hronizations. it gives details of the latency times between the event on an external interrupt leading in a valid interrupt (edge or level) or the assertion of an internal interrupt source and the assertion of the nirq or nfiq line on the pro- cessor. the resynchronization time depends on the programming of the interrupt source and on its type (internal or external). for the standard interrupt, resynchronization times are given assuming there is no higher priority in progress. the pio controller multiplexing has no effect on the interrupt latencies of the external interrupt sources. 29.7.2.1 external interrupt edge triggered source figure 29-6. external interrupt edge triggered source 29.7.2.2 external interrupt level sensitive source figure 29-7. external interrupt level sensitive source maximum fiq latency = 4 cycles maximum irq latency = 4 cycles nfiq nirq mck irq or fiq (positive edge) irq or fiq (negative edge) maximum irq latency = 3 cycles maximum fiq latency = 3 cycles mck irq or fiq (high level) irq or fiq (low level) nirq nfiq
357 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 29.7.2.3 internal interrupt edge triggered source figure 29-8. internal interrupt edge triggered source 29.7.2.4 internal interrupt level sensitive source figure 29-9. internal interrupt level sensitive source 29.7.3 normal interrupt 29.7.3.1 priority controller an 8-level priority controller drives the nirq line of the processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 31 (except for those programmed in fast forcing). each interrupt source has a programmable priority le vel of 7 to 0, which is user-definable by writ- ing the prior field of the corresponding aic_smr (source mode register). level 7 is the highest priority and level 0 the lowest. as soon as an interrupt condition occurs, as defined by the srctype field of the aic_smr (source mode register), the nirq line is asserted. as a new interrupt condition might have hap- pened on other interrupt sources since the nirq has been asserted, the priority controller determines the current interrupt at the time the aic_ivr (interrupt vector register) is read. the read of aic_ivr is the entry point of the interrupt handling which allows the aic to consider that the interrupt has been taken into account by the software. the current priority level is defined as the priority level of the current interrupt. if several interrupt sources of equal priority are pending and enabled when the aic_ivr is read, the interrupt with the lowest interrupt source number is serviced first. mck nirq peripheral interrupt becomes active maximum irq latency = 4.5 cycles mck nirq maximum irq latency = 3.5 cycles peripheral interrupt becomes active
358 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary the nirq line can be asserted only if an interrupt cond ition occurs on an in terrupt source with a higher priority. if an interrupt condition happens (or is pending) during the interrupt treatment in progress, it is delayed until the software indicates to the aic the end of the current service by writing the aic_eoicr (end of interrupt command register). the write of aic_eoicr is the exit point of the interrupt handling . 29.7.3.2 interrupt nesting the priority controller utilizes interr upt nesting in order for the high priority interrup t to be handled during the service of lower priori ty interrupts. this requires the interrupt service routines of the lower interrupts to re-enable the interrupt at the processor level. when an interrupt of a higher priority happens during an already occurring interrupt service rou- tine, the nirq line is re-asserted. if the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt service routine should read the aic_ivr. at this time, the current interrupt number and its priority level are pushed into an embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing is finished and the aic_eoicr is written. the aic is equipped with an 8-leve l wide hardware stack in order to support up to eight interrupt nestings pursuant to having eight priority levels. 29.7.3.3 interrupt vectoring the interrupt handler addresses corresponding to each interrupt source can be stored in the reg- isters aic_svr1 to aic_svr31 (source vector register 1 to 31). when the processor reads aic_ivr (interrupt vector register), the value written into aic_svr corresponding to the cur- rent interrupt is returned. this feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as aic_ivr is mapped at the absolute address 0xffff f100 and thus acces- sible from the arm interrupt vector at address 0x0000 0018 through the following instruction: ldr pc,[pc,# -&f20] when the processor executes this instruction, it loads the read value in aic_ivr in its program counter, thus branching the execution on the correct interrupt handler. this feature is often not used when the application is based on an operating system (either real time or not). operating systems often have a single entry point for all the interrupts and the first task performed is to discern the source of the interrupt. however, it is strongly recommended to port the operating system on at91 products by support- ing the interrupt vectoring. this can be performed by defining all the aic_svr of the interrupt source to be handled by the operating system at the address of its interrupt handler. when doing so, the interrupt vectoring permits a critical inte rrupt to transfer the execution on a specific very fast handler and not onto the operating system?s general interrupt handler. this facilitates the support of hard real-time tasks (input/outputs of voice/audio buffers and software peripheral han- dling) to be handled efficiently and independently of the application running under an operating system. 29.7.3.4 interrupt handlers this section gives an overview of the fast interrupt handling sequence when using the aic. it is assumed that the programmer understands the architecture of the arm processor, and espe- cially the processor interrupt mode s and the associated status bits.
359 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary it is assumed that: 1. the advanced interrupt controller has been programmed, aic_svr registers are loaded with corresponding interrupt service routine addresses and interrupts are enabled. 2. the instruction at the arm interrupt exception vector address is required to work with the vectoring ldr pc, [pc, # -&f20] when nirq is asserted, if the bit ?i? of cpsr is 0, the sequence is as follows: 1. the cpsr is stored in spsr_i rq, the current value of the program coun ter is loaded in the interrupt link register (r14_irq) and the program counter (r15) is loaded with 0x18. in the following cycle during fetch at address 0x1c, the arm core adjusts r14_irq, dec- rementing it by four. 2. the arm core enters interrupt mode, if it has not already done so. 3. when the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in aic_ivr. reading the aic_ivr has the following effects: ? sets the current interrupt to be the pending and enabled interrupt with the highest priority. the current level is the priority level of the current interrupt. ? de-asserts the nirq line on the processor. even if vectoring is not used, aic_ivr must be read in order to de-assert nirq. ? automatically clears the interrupt, if it has been programmed to be edge-triggered. ? pushes the current level and the current interrupt number on to the stack. ? returns the value written in the aic_svr corresponding to the current interrupt. 4. the previous step has the effect of branc hing to the corresponding interrupt service routine. this should start by saving the link register (r14_irq) and spsr_irq. the link register must be decremented by four when it is saved if it is to be restored directly into the program counter at the end of the interrupt. for example, the instruction sub pc, lr, #4 may be used. 5. further interrupts can then be unmasked by clearing the ?i? bit in cpsr, allowing re- assertion of the nirq to be taken into account by the core. this can happen if an inter- rupt with a higher priority than the current interrupt occurs. 6. the interrupt handler can th en proceed as required, savi ng the registers that will be used and restoring them at the end. during this phase, an interrupt of higher priority than the current leve l will restart the sequence from step 1. note: if the interrupt is programmed to be level sensitiv e, the source of the interrupt must be cleared dur- ing this phase. 7. the ?i? bit in cpsr must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner. 8. the end of interrupt command register (aic_eoicr) must be written in order to indi- cate to the aic that the current interrupt is finished. this causes the current level to be popped from the stack, restoring the previous current level if one exists on the stack. if another interrupt is pending, with lower or equal priority than the old current level but with higher priority than the new current level, the nirq line is re-asserted, but the inter- rupt sequence does not immediately start because the ?i? bit is set in the core. spsr_irq is restored. fina lly, the saved value of the link regi ster is restored directly into the pc. this has the effect of returning from the interrupt to whatever was being exe- cuted before, and of loading the cpsr with the stored spsr, masking or unmasking the interrupts depending on the state saved in spsr_irq.
360 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary note: the ?i? bit in spsr is significant. if it is set, it indicates that the arm core was on the verge of masking an interrupt when the mask instruction was in terrupted. hence, when spsr is restored, the mask instruction is comple ted (interrupt is masked). 29.7.4 fast interrupt 29.7.4.1 fast interrupt source the interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. the interrupt so urce 0 is generally connected to a fiq pin of the product, either directly or through a pio controller. 29.7.4.2 fast interrupt control the fast interrupt logic of the aic has no priority controller. the mode of interrupt source 0 is programmed with the aic_smr0 and the field prior of this register is not used even if it reads what has been written. the fi eld srctype of aic_smr0 enable s programming the fast inter- rupt source to be positive-edge triggered or negative-edge triggered or high-level sensitive or low-level sensitive writing 0x1 in the aic_iecr (interrupt enable command register) and aic_idcr (interrupt disable command register) respectively enables and disables the fast interrupt. the bit 0 of aic_imr (interrupt mask register) indicates whet her the fast interrupt is enabled or disabled. 29.7.4.3 fast interrupt vectoring the fast interrupt handler address can be stor ed in aic_svr0 (source vector register 0). the value written into this register is returned when the processor reads aic_fvr (fast vector reg- ister). this offers a way to branch in one single instruction to the interrupt handler, as aic_fvr is mapped at the absolute address 0xffff f104 and thus accessible from the arm fast inter- rupt vector at address 0x0000 001c through the following instruction: ldr pc,[pc,# -&f20] when the processor executes this instruction it loads the value read in aic_fvr in its program counter, thus branching the execution on the fast interrupt handler. it also automatically per- forms the clear of the fast interrupt source if it is programmed in edge-triggered mode. 29.7.4.4 fast interrupt handlers this section gives an overview of the fast interrupt handling sequence when using the aic. it is assumed that the programmer understands the architecture of the arm processor, and espe- cially the processor interrupt modes and associated status bits. assuming that: 1. the advanced interrupt controller has been programmed, aic_svr0 is loaded with the fast interrupt service routine address, and the interrupt source 0 is enabled. 2. the instruction at address 0x1c (fiq exception vector address) is required to vector the fast interrupt: ldr pc, [pc, # -&f20] 3. the user does not need nested fast interrupts. when nfiq is asserted, if the bit ?f? of cpsr is 0, the sequence is: 1. the cpsr is stored in spsr_fiq, the current value of the program counter is loaded in the fiq link register (r14_fiq) and the program counter (r15) is loaded with 0x1c. in
361 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary the following cycle, during fetch at address 0x20, the arm core ad justs r14_fiq, decre- menting it by four. 2. the arm core enters fiq mode. 3. when the instruction loaded at address 0x1c is executed, the program counter is loaded with the value read in aic_fvr. re ading the aic_fvr has effect of automati- cally clearing the fast interrupt, if it has been programmed to be edge triggered. in this case only, it de-asserts the nfiq line on the processor. 4. the previous step enables branching to the corresponding interrupt service routine. it is not necessary to save the link register r14_fiq and spsr_fiq if nested fast interrupts are not needed. 5. the interrupt handler can then proceed as required. it is not necessary to save regis- ters r8 to r13 because fiq mode has its own dedicated registers and the user r8 to r13 are banked. the other registers, r0 to r7, must be saved before being used, and restored at the end (before the next step). note that if the fast interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the interrupt source 0. 6. finally, the link register r14_fiq is restored into the pc after decrementing it by four (with instruction sub pc, lr, #4 for example). this has the effect of returning from the interrupt to whatever was being exec uted before, loading the cpsr with the spsr and masking or unmasking the fast interrupt depending on the state saved in the spsr. note: the ?f? bit in spsr is significan t. if it is set, it indicates that the arm core was just about to mask fiq interrupts when the mask instru ction was interrupted. hence wh en the spsr is restored, the interrupted instruction is completed (fiq is masked). another way to handle the fast interrupt is to map the interrupt service routine at the address of the arm vector 0x1c. this method does not use the vectoring, so that reading aic_fvr must be performed at the very beginning of the handler operation. however, this method saves the execution of a branch instruction. 29.7.4.5 fast forcing the fast forcing feature of the advanced interrupt controller provides redirection of any normal interrupt source on the fast interrupt controller. fast forcing is enabled or disabl ed by writing to the fast forcing enable register (aic_ffer) and the fast forcing disable register (aic_ff dr). writing to these registers results in an update of the fast forcing status register (aic _ffsr) that controls the feature for each inter- nal or external interrupt source. when fast forcing is disabled, the interrupt sources are handled as described in the previous pages. when fast forcing is enabled, the edge/level programming and, in certain cases, edge detec- tion of the interrupt s ource is still active but the source c annot trigger a normal interrupt to the processor and is not seen by the priority handler. if the interrupt source is programmed in level- sensitive mode and an active level is sampled, fast forcing results in the assertion of the nfiq line to the core. if the interrupt source is programmed in edge-triggered mode and an active edge is detected, fast forcing results in the assertion of the nfiq line to the core. the fast forcing feature does not affect the source 0 pending bit in the interrupt pending reg- ister (aic_ipr).
362 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary the fiq vector register (aic_fvr) reads the contents of the source vector register 0 (aic_svr0), whatever the source of the fast interrupt may be. the read of the fvr does not clear the source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the interrupt cl ear command register (aic_iccr). all enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in edge-triggered mode must be cleared by writing to the interrupt clear command register. in doing so, they are cleared independently and thus lost interrupts are prevented. the read of aic_ivr does not clear the source that has the fast forcing feature enabled. the source 0, reserved to the fast interrupt, continues operating normally and becomes one of the fast interrupt sources. figure 29-10. fast forcing 29.7.5 protect mode the protect mode permits reading the interrupt vector register without performing the associ- ated automatic operations. this is necessary when working with a debug system. when a debugger, working either with a debug monitor or the arm processor's ic e, stops the applica- tions and updates the opened windows, it might read the aic user interface and thus the ivr. this has undesirable consequences: ? if an enabled interrupt with a higher priority than the current one is pending, it is stacked. ? if there is no enabled pending interrupt, the spurious vector is returned. in either case, an end of interrupt command is necessary to acknowledge and to restore the context of the aic. this operation is generally not performed by the debug system as the debug system would become strongly intrusive and caus e the application to enter an undesired state. this is avoided by using the protect mode. wr iting prot in aic_dcr (debug control register) at 0x1 enables the protect mode. when the protect mode is enabled, the aic performs interrupt stacking only when a write access is performed on the aic_ivr. therefore, the interrupt service routines must write (arbitrary data) to the aic_ivr just after reading it. the new context of the aic, including the value of the source 0 _ fiq input stage automatic clear input stage automatic clear source n aic_ipr aic_imr aic_ffsr aic_ipr aic_imr priority manager nfiq nirq read ivr if source n is the current interrupt and if fast forcing is disabled on source n. read fvr if fast forcing is disabled on sources 1 to 31.
363 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary interrupt status register (aic_isr), is updated with the current interrupt only when aic_ivr is written. an aic_ivr read on its own (e.g., by a debugger), modifies neither the aic context nor the aic_isr. extra aic_ivr reads perform the same operations. however, it is recommended to not stop the processor between the read and the write of aic_ivr of the interrupt service routine to make sure the debugger does not modify the aic context. to summarize, in normal operating mode, the read of aic_ivr performs the following opera- tions within the aic: 1. calculates active interrupt (higher than current or spurious). 2. determines and returns the vector of the active interrupt. 3. memorizes the interrupt. 4. pushes the current priority level onto the internal stack. 5. acknowledges the interrupt. however, while the protect mode is activated, only operations 1 to 3 are performed when aic_ivr is read. operations 4 and 5 are only performed by the aic when aic_ivr is written. software that has been written and debugged using the protect mode runs correctly in normal mode without modification. however, in normal mode the aic_ivr write has no effect and can be removed to optimize the code. 29.7.6 spurious interrupt the advanced interrupt controller features protection against spurious interrupts. a spurious interrupt is defined as being the assertion of an interrupt source long enough for the aic to assert the nirq, but no longer present when aic_ivr is read. this is most prone to occur when: ? an external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time. ? an internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time. (as in the case for the watchdog.) ? an interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the interrupt source. the aic detects a spurious interrupt at the time the aic_ivr is read while no enabled interrupt source is pending. when this happens, the aic returns the value stored by the programmer in aic_spu (spurious vector register). the pr ogrammer must store the address of a spurious interrupt handler in aic_spu as part of the application, to enable an as fast as possible return to the normal execution flow. this handler writes in aic_eoicr and performs a return from interrupt. 29.7.7 general interrupt mask the aic features a general interrupt mask bit to prevent interrupts from reaching the processor. both the nirq and the nfiq lines are driven to thei r inactive state if the bit gmsk in aic_dcr (debug control register) is set. however, this mask does not prevent waking up the processor if it has entered idle mode. this function facilit ates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt. it is strongly recommended to use this mask with caution.
364 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 29.8 advanced interrupt controll er (aic) user interface 29.8.1 base address the aic is mapped at the address 0xffff f000 . it has a total 4-kbyte addressing space. this permits the vectoring fea- ture, as the pc-relative load/store instructions of the arm processor support only a 4-kbyte offset. notes: 1. the reset value of this register depends on the level of the external interrupt source. all other sources are cleared a t reset, thus not pending. 2. pid2...pid31 bit fields refer to the identifiers as defined in the peripheral identifiers section of the product datasheet. table 29-2. register mapping offset register name access reset 0x00 source mode register 0 aic_smr0 read-write 0x0 0x04 source mode register 1 aic_smr1 read-write 0x0 --- --- --- --- --- 0x7c source mode register 31 aic_smr31 read-write 0x0 0x80 source vector register 0 aic_svr0 read-write 0x0 0x84 source vector register 1 aic_svr1 read-write 0x0 --- --- --- --- --- 0xfc source vector register 31 aic_svr31 read-write 0x0 0x100 interrupt vector register aic_ivr read-only 0x0 0x104 fiq interrupt vector register aic_fvr read-only 0x0 0x108 interrupt status register aic_isr read-only 0x0 0x10c interrupt pending register (2) aic_ipr read-only 0x0 (1) 0x110 interrupt mask register (2) aic_imr read-only 0x0 0x114 core interrupt status register aic_cisr read-only 0x0 0x118 - 0x11c reserved --- --- --- 0x120 interrupt enable command register (2) aic_iecr write-only --- 0x124 interrupt disable command register (2) aic_idcr write-only --- 0x128 interrupt clear command register (2) aic_iccr write-only --- 0x12c interrupt set command register (2) aic_iscr write-only --- 0x130 end of interrupt command register aic_eoicr write-only --- 0x134 spurious interrupt vector register aic_spu read-write 0x0 0x138 debug control register aic_dcr read-write 0x0 0x13c reserved --- --- --- 0x140 fast forcing enable register (2) aic_ffer write-only --- 0x144 fast forcing disable register (2) aic_ffdr write-only --- 0x148 fast forcing status register (2) aic_ffsr read-only 0x0 0x14c - 0x1e0 reserved --- --- --- 0x1ec - 0x1fc reserved
365 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 29.8.2 aic source mode register register name: aic_smr0..aic_smr31 address: 0xfffff000 access type: read-write reset value: 0x0 ? prior: priority level programs the priority level for all sources except fiq source (source 0). the priority level can be between 0 (lowest) and 7 (highest). the priority level is not used for the fi q in the related smr register aic_smrx. ? srctype: interrupt source type the active level or edge is not programmable for the internal interrupt sources. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? srctype ? ? prior srctype internal interrupt sources external interrupt sources 0 0 high level sensitive low level sensitive 0 1 positive edge triggered negative edge triggered 1 0 high level sensitive high level sensitive 1 1 positive edge triggered positive edge triggered
366 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 29.8.3 aic source vector register register name: aic_svr0..aic_svr31 address: 0xfffff080 access type: read-write reset value: 0x0 ? vector: source vector the user may store in these registers the addresses of the corresponding handler for each interrupt source. 29.8.4 aic interrupt vector register register name: aic_ivr address: 0xfffff100 access type: read-only reset value: 0x0 ? irqv: interrupt vector register the interrupt vector register contains the vector programmed by the user in the source vector register corresponding to the current interrupt. the source vector register is indexed using the current interrupt number when the interrupt vector register is read. when there is no current interrupt, the interrupt vector register reads the value stored in aic_spu. 31 30 29 28 27 26 25 24 vector 23 22 21 20 19 18 17 16 vector 15 14 13 12 11 10 9 8 vector 76543210 vector 31 30 29 28 27 26 25 24 irqv 23 22 21 20 19 18 17 16 irqv 15 14 13 12 11 10 9 8 irqv 76543210 irqv
367 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 29.8.5 aic fiq vector register register name: aic_fvr address: 0xfffff104 access type: read-only reset value: 0x0 ? fiqv: fiq vector register the fiq vector register contains the vector programmed by the user in the source vector register 0. when there is no fast interrupt, the fiq vector register reads the value stored in aic_spu. 29.8.6 aic interrupt status register register name: aic_isr address: 0xfffff108 access type: read-only reset value: 0x0 ? irqid: current interrupt identifier the interrupt status register returns the current interrupt source number. 31 30 29 28 27 26 25 24 fiqv 23 22 21 20 19 18 17 16 fiqv 15 14 13 12 11 10 9 8 fiqv 76543210 fiqv 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??? irqid
368 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 29.8.7 aic interrupt pending register register name: aic_ipr address: 0xfffff10c access type: read-only reset value: 0x0 ? fiq, sys, pid2-pid31: interrupt pending 0 = corresponding interrupt is not pending. 1 = corresponding interrupt is pending. 29.8.8 aic interrupt mask register register name: aic_imr address: 0xfffff110 access type: read-only reset value: 0x0 ? fiq, sys, pid2-pid31: interrupt mask 0 = corresponding interrupt is disabled. 1 = corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
369 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 29.8.9 aic core interrupt status register register name: aic_cisr address: 0xfffff114 access type: read-only reset value: 0x0 ? nfiq: nfiq status 0 = nfiq line is deactivated. 1 = nfiq line is active. ? nirq: nirq status 0 = nirq line is deactivated. 1 = nirq line is active. 29.8.10 aic interrupt enable command register register name: aic_iecr address: 0xfffff120 access type: write-only ? fiq, sys, pid2-pid31: interrupt enable 0 = no effect. 1 = enables corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????nirqnfiq 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
370 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 29.8.11 aic interrupt disable command register register name: aic_idcr address: 0xfffff124 access type: write-only ? fiq, sys, pid2-pid31: interrupt disable 0 = no effect. 1 = disables corresponding interrupt. 29.8.12 aic interrupt clear command register register name: aic_iccr address: 0xfffff128 access type: write-only ? fiq, sys, pid2-pid31: interrupt clear 0 = no effect. 1 = clears corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
371 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 29.8.13 aic interrupt set command register register name: aic_iscr address: 0xfffff12c access type: write-only ? fiq, sys, pid2-pid31: interrupt set 0 = no effect. 1 = sets corresponding interrupt. 29.8.14 aic end of interrupt command register register name: aic_eoicr address: 0xfffff130 access type: write-only the end of interrupt command register is used by the interrupt routine to indicate that the interrupt treatment is complete. any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????????
372 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 29.8.15 aic spurious interrupt vector register register name: aic_spu address: 0xfffff134 access type: read-write reset value: 0x0 ? sivr: spurious interrupt vector register the user may store the address of a spurious interrupt handler in this register. the written value is returned in aic_ivr in case of a spurious interrupt and in aic_fvr in case of a spurious fast interrupt. 29.8.16 aic debug control register register name: aic_dcr address: 0xfffff138 access type: read-write reset value: 0x0 ? prot: protection mode 0 = the protection mode is disabled. 1 = the protection mode is enabled. ? gmsk: general mask 0 = the nirq and nfiq lines are normally controlled by the aic. 1 = the nirq and nfiq lines are tied to their inactive state. 31 30 29 28 27 26 25 24 sivr 23 22 21 20 19 18 17 16 sivr 15 14 13 12 11 10 9 8 sivr 76543210 sivr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????gmskprot
373 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 29.8.17 aic fast forcing enable register register name: aic_ffer address: 0xfffff140 access type: write-only ? sys, pid2-pid31: fast forcing enable 0 = no effect. 1 = enables the fast forcing feature on the corresponding interrupt. 29.8.18 aic fast forcing disable register register name: aic_ffdr address: 0xfffff144 access type: write-only ? sys, pid2-pid31: fast forcing disable 0 = no effect. 1 = disables the fast forcing feature on the corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys ? 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys ?
374 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 29.8.19 aic fast forcing status register register name: aic_ffsr address: 0xfffff148 access type: read-only ? sys, pid2-pid31: fast forcing status 0 = the fast forcing feature is disabled on the corresponding interrupt. 1 = the fast forcing feature is enabled on the corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys ?
375 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 30. debug unit (dbgu) 30.1 description the debug unit provides a single entry point from the processor for access to all the debug capabilities of atmel?s arm-based systems. the debug unit features a two-pin uart that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communica- tions. the debug unit two-pin uart can be used stand-alone for general purpose serial communication. moreover, the association with two peripheral data controller channels permits packet handling for these tasks with processor time reduced to a minimum. the debug unit also makes the debug communication channel (dcc) signals provided by the in-circuit emulator of the arm processor visible to the software. these signals indicate the sta- tus of the dcc read and write registers and gener ate an interrup t to the arm processor, making possible the handling of the dcc under interrupt control. chip identifier registers permit recognition of t he device and its revision. these registers inform as to the sizes and types of the on-chip memori es, as well as the set of embedded peripherals. finally, the debug unit features a force ntrst capability that enables the software to decide whether to prevent access to the system via th e in-circuit emulator. th is permits protection of the code, stored in rom.
376 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 30.2 block diagram figure 30-1. debug unit functional block diagram figure 30-2. debug unit application example peripheral dma controller baud rate generator dcc handler ice access handler transmit receive chip id interrupt control peripheral bridge parallel input/ output dtxd drxd power management controller arm processor force_ntrst commrx commtx mck ntrst power-on reset dbgu_irq apb debug unit r table 30-1. debug unit pin description pin name description type drxd debug receive data input dtxd debug transmit data output debug unit rs232 drivers programming tool trace console debug console boot program debug monitor trace manager
377 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 30.3 product dependencies 30.3.1 i/o lines depending on product integration, the debug unit pins may be multiplexed with pio lines. in this case, the programmer must first configure the corresponding pio controller to enable i/o lines operations of the debug unit. 30.3.2 power management depending on product integration, the debug unit clock may be controllable through the power management controller. in this case, the programmer must first configure the pmc to enable the debug unit clock. usually, the peripheral identifier used for this purpose is 1. 30.3.3 interrupt source depending on product integration, the debug unit interrupt line is connected to one of the inter- rupt sources of the advanced interrupt controller. interrupt handling requires programming of the aic before configuring the de bug unit. usually, the debug unit interrupt line connects to the interrupt source 1 of the aic, which may be shared with the real-time clock, the system timer interrupt lines and other system peripheral interrupts, as shown in figure 30-1 . this sharing requires the programmer to determine the source of the interrupt when the source 1 is triggered. 30.4 uart operations the debug unit operates as a uart, (asynchro nous mode only) and supports only 8-bit charac- ter handling (with parity). it has no clock pin. the debug unit's uart is made up of a receiver and a transmitter that operate independently, and a common baud rate generator. receiver timeout and transmitter time guard are not imple- mented. however, all the implemented features are compatible with those of a standard usart. 30.4.1 baud rate generator the baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter. the baud rate clock is the master clock divided by 16 times the value (cd) written in dbgu_brgr (baud rate generator register). if dbgu_brgr is set to 0, the baud rate clock is disabled and the debug unit's uart remains inactive. the maximum allowable baud rate is master clock divided by 16. the minimum allow able baud rate is master clock divided by (16 x 65536). baud rate mck 16 cd ---------------------- =
378 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 30-3. baud rate generator 30.4.2 receiver 30.4.2.1 receiver rese t, enable and disable after device reset, the debug unit receiver is disabled and must be enabled before being used. the receiver can be enabled by writing the control register dbgu_cr with the bit rxen at 1. at this command, the receiver starts looking for a start bit. the programmer can disable the receiver by writ ing dbgu_cr with the bit rxdis at 1. if the receiver is waiting for a start bit, it is immedi ately stopped. however, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. the programmer can also put the receiver in it s reset state by writing dbgu_cr with the bit rstrx at 1. in doing so, the receiver immediat ely stops its current operations and is disabled, whatever its current state. if rstrx is applied wh en data is being processed, this data is lost. 30.4.2.2 start detection and data sampling the debug unit only supports asynchronous operations, and this affects only its receiver. the debug unit receiver detects the start of a rece ived character by sampling the drxd signal until it detects a valid start bit. a low level (space) on drxd is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. a space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. when a valid start bit has been detected, the receiver samples the drxd at the theoretical mid- point of each bit. it is assumed that each bit last s 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. the first sampling point is therefore 24 cycles (1.5 -bit periods) after t he falling edge of the st art bit was detected. each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. mck 16-bit counter 0 baud rate clock cd cd out divide by 16 0 1 >1 receiver sampling clock
379 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 30-4. start bit detection figure 30-5. character reception 30.4.2.3 receiver ready when a complete character is received, it is transferred to the dbgu_rhr and the rxrdy sta- tus bit in dbgu_sr (status register) is set. the bit rxrdy is automatically cleared when the receive holding register dbgu_rhr is read. figure 30-6. receiver ready 30.4.2.4 receiver overrun if dbgu_rhr has not been read by the software (o r the peripheral data controller) since the last transfer, the rxrdy bit is still set and a ne w character is received, the ovre status bit in dbgu_sr is set. ovre is cleared when the soft ware writes the contro l register dbgu_cr with the bit rststa (reset status) at 1. figure 30-7. receiver overrun 30.4.2.5 parity error each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field par in dbgu_mr. it then compares the result with the received parity sampling clock drxd true start detection d0 baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 drxd true start detection sampling parity bit stop bit example: 8-bit, parity enabled 1 stop 1 bit period 0.5 bit period d0 d1 d2 d3 d4 d5 d6 d7 p s s d0 d1 d2 d3 d4 d5 d6 d7 p drxd read dbgu_rhr rxrdy d0 d1 d2 d3 d4 d5 d6 d7 p s s d0 d1 d2 d3 d4 d5 d6 d7 p drxd rststa rxrdy ovre stop stop
380 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary bit. if different, the parity error bit pare in dbgu_sr is set at the same time the rxrdy is set. the parity bit is cleared when the control register dbgu_cr is written with the bit rststa (reset status) at 1. if a new character is received before the reset status command is written, the pare bit remains at 1. figure 30-8. parity error 30.4.2.6 receiver framing error when a start bit is detected, it generates a character reception when all the data bits have been sampled. the stop bit is also sampled and when it is detected at 0, the frame (framing error) bit in dbgu_sr is set at the same time the rxrdy bit is set. the bit frame remains high until the control register dbgu_cr is written with the bit rststa at 1. figure 30-9. receiver framing error 30.4.3 transmitter 30.4.3.1 transmitter reset, enable and disable after device reset, the debug unit transmitter is disabled and it must be enabled before being used. the transmitter is enabled by writing the control register dbgu_cr with the bit txen at 1. from this command, the transmitter waits for a ch aracter to be written in the transmit holding register dbgu_thr before actually starting the transmission. the programmer can disable the transmitter by writing dbgu_cr with the bit txdis at 1. if the transmitter is not operating, it is immediately stopped. however, if a character is being pro- cessed into the shift register and/or a character has been written in the transmit holding register, the characters are completed before the transmitter is actually stopped. the programmer can also put the transmitter in its reset state by writing the dbgu_cr with the bit rsttx at 1. this immediately stops the transmitter, whether or not it is processing characters. 30.4.3.2 transmit format the debug unit transmitter drives the pin dtxd at the baud rate clock speed. the line is driven depending on the format defined in the mode register and the data stored in the shift register. one start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifte d out as shown on the following figure. the field stop d0 d1 d2 d3 d4 d5 d6 d7 p s drxd rststa rxrdy pare wrong parity bit d0 d1 d2 d3 d4 d5 d6 d7 p s drxd rststa rxrdy frame stop bit detected at 0 stop
381 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary pare in the mode register dbgu_mr defines whether or not a parity bit is shifted out. when a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. figure 30-10. character transmission 30.4.3.3 transmitter control when the transmitter is enabled, the bit txrdy (transmitter ready) is set in the status register dbgu_sr. the transmission starts when the prog rammer writes in the transmit holding regis- ter dbgu_thr, and after the written character is transferred from dbgu_thr to the shift register. the bit txrdy remains high until a second character is written in dbgu_thr. as soon as the first character is completed, the last character written in dbgu_thr is transferred into the shift register and txrdy rises again, showing that the holding register is empty. when both the shift register and the dbgu_thr are empty, i.e., all the characters written in dbgu_thr have been processed, the bit txempty rises after the last stop bit has been completed. figure 30-11. transmitter control 30.4.4 peripheral data controller both the receiver and the transmitter of the debug unit's uart are generally connected to a peripheral data controller (pdc) channel. the peripheral data controller channels are programmed via registers that are mapped within the debug unit user interface from the offset 0x100. the status bits are reported in the debug unit status register dbgu_sr and can generate an interrupt. d0 d1 d2 d3 d4 d5 d6 d7 dtxd start bit parity bit stop bit example: parity enabled baud rate clock dbgu_thr shift register dtxd txrdy txempty data 0 data 1 data 0 data 0 data 1 data 1 s s p p write data 0 in dbgu_thr write data 1 in dbgu_thr stop stop
382 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary the rxrdy bit triggers the pdc channel data transfer of the receiver. this results in a read of the data in dbgu_rhr. the txrdy bit triggers t he pdc channel data tran sfer of the transmit- ter. this results in a writ e of a data in dbgu_thr. 30.4.5 test modes the debug unit supports three tests modes. these modes of operation are programmed by using the field chmode (channel mode) in the mode register dbgu_mr. the automatic echo mode allows bit-by-bit retr ansmission. when a bit is received on the drxd line, it is sent to the dtxd line. the transm itter operates normally, but has no effect on the dtxd line. the local loopback mode allows the transmitted characters to be received. dtxd and drxd pins are not used and the output of the transmitter is internally connected to the input of the receiver. the drxd pin level has no effect and th e dtxd line is held high , as in idle state. the remote loopback mode directly connects the drxd pin to the dtxd line. the transmitter and the receiver are disabled and have no effec t. this mode allows a bit-by-bit retransmission. figure 30-12. test modes 30.4.6 debug communication channel support the debug unit handles the signals commrx and commtx that come from the debug com- munication channel of the arm processor and are driven by the in-circuit emulator. receiver transmitter disabled rxd txd receiver transmitter disabled rxd txd v dd disabled receiver transmitter disabled rxd txd disabled automatic echo local loopback remote loopback v dd
383 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary the debug communication channel contains two registers that are accessible through the ice breaker on the jtag side and through the coprocessor 0 on the arm processor side. as a reminder, the following instructions ar e used to read and write the debug communication channel: mrc p14, 0, rd, c1, c0, 0 returns the debug communication data read register into rd mcr p14, 0, rd, c1, c0, 0 writes the value in rd to the debug communication data write register. the bits commrx and commtx, which indicate, respectively, that the read register has been written by the debugger but not yet read by the processor, and that the write register has been written by the processor and not yet read by the debugger, are wired on the two highest bits of the status register dbgu_sr. these bits can generate an interrupt. this feature permits han- dling under interrupt a debug link between a debug monitor running on the target system and a debugger. 30.4.7 chip identifier the debug unit features two chip identifier registers, dbgu_cidr (chip id register) and dbgu_exid (extension id). both registers contain a hard-wired value that is read-only. the first register contains the following fields: ? ext - shows the use of the extension identifier register ? nvptyp and nvpsiz - identifies the type of embedded non-volatile memory and its size ? arch - identifies the set of embedded peripherals ? sramsiz - indicates the size of the embedded sram ? eproc - indicates the embedded arm processor ? version - gives the revision of the silicon the second register is device-dependent and reads 0 if the bit ext is 0. 30.4.8 ice access prevention the debug unit allows blockage of access to the system through the arm processor's ice interface. this feature is implemented via th e register force ntrst (dbgu_fnr), that allows assertion of the ntrst signal of the ice interface. writing the bit fntrst (force ntrst) to 1 in this register prevents any activity on the tap controller. on standard devices, the bit fntrst resets to 0 and thus does not prevent ice access. this feature is especially useful on custom rom devices for customers who do not want their on-chip code to be visible.
384 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 30.5 debug unit (dbgu) user interface table 30-2. register mapping offset register name access reset 0x0000 control register dbgu_cr write-only ? 0x0004 mode register dbgu_mr read-write 0x0 0x0008 interrupt enable register dbgu_ier write-only ? 0x000c interrupt disable register dbgu_idr write-only ? 0x0010 interrupt mask register dbgu_imr read-only 0x0 0x0014 status register dbgu_sr read-only ? 0x0018 receive holding register dbgu_rhr read-only 0x0 0x001c transmit holding register dbgu_thr write-only ? 0x0020 baud rate generator register dbgu_brgr read-write 0x0 0x0024 - 0x003c reserved ? ? ? 0x0040 chip id register dbgu_cidr read-only ? 0x0044 chip id extension register dbgu_exid read-only ? 0x0048 force ntrst register dbgu_fnr read-write 0x0 0x004c - 0x00fc reserved ? ? ? 0x0100 - 0x0124 pdc area ? ? ?
385 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 30.5.1 debug unit control register name: dbgu_cr address: 0xfffff200 access type: write-only ? rstrx: reset receiver 0 = no effect. 1 = the receiver logic is reset and disabled. if a ch aracter is being received, the reception is aborted. ? rsttx: reset transmitter 0 = no effect. 1 = the transmitter logic is reset and disabled. if a character is being transmitted, the transmission is aborted. ? rxen: receiver enable 0 = no effect. 1 = the receiver is enabled if rxdis is 0. ? rxdis: receiver disable 0 = no effect. 1 = the receiver is disabled. if a character is being processe d and rstrx is not set, the character is completed before the receiver is stopped. ? txen: transmitter enable 0 = no effect. 1 = the transmitter is ena bled if txdis is 0. ? txdis: transmitter disable 0 = no effect. 1 = the transmitter is disabled. if a character is bei ng processed and a character has been written the dbgu_thr and rsttx is not set, both characters are completed before the transmitter is stopped. ? rststa: reset status bits 0 = no effect. 1 = resets the status bits pare, frame and ovre in the dbgu_sr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????? rststa 76543210 txdis txen rxdis rxen rsttx rstrx ??
386 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 30.5.2 debug unit mode register name: dbgu_mr address: 0xfffff204 access type: read-write ? par: parity type ? chmode: channel mode 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 chmode ?? pa r ? 76543210 ???????? par parity type 0 0 0 even parity 001odd parity 0 1 0 space: parity forced to 0 0 1 1 mark: parity forced to 1 1 x x no parity chmode mode description 00normal mode 0 1 automatic echo 1 0 local loopback 1 1 remote loopback
387 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 30.5.3 debug unit interrupt enable register name: dbgu_ier address: 0xfffff208 access type: write-only ? rxrdy: enable rxrdy interrupt ? txrdy: enable txrdy interrupt ? endrx: enable end of receive transfer interrupt ? endtx: enable end of transmit interrupt ? ovre: enable overrun error interrupt ? frame: enable framing error interrupt ? pare: enable parity error interrupt ? txempty: enable txempty interrupt ? txbufe: enable buffer empty interrupt ? rxbuff: enable buffer full interrupt ? commtx: enable commtx (from arm) interrupt ? commrx: enable commrx (from arm) interrupt 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 commrx commtx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy
388 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 30.5.4 debug unit interrupt disable register name: dbgu_idr address: 0xfffff20c access type: write-only ? rxrdy: disable rxrdy interrupt ? txrdy: disable txrdy interrupt ? endrx: disable end of receive transfer interrupt ? endtx: disable end of transmit interrupt ? ovre: disable overrun error interrupt ? frame: disable framing error interrupt ? pare: disable parity error interrupt ? txempty: disable txempty interrupt ? txbufe: disable buffer empty interrupt ? rxbuff: disable buffer full interrupt ? commtx: disable commtx (from arm) interrupt ? commrx: disable commrx (from arm) interrupt 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 commrx commtx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy
389 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 30.5.5 debug unit interrupt mask register name: dbgu_imr address: 0xfffff210 access type: read-only ? rxrdy: mask rxrdy interrupt ? txrdy: disable txrdy interrupt ? endrx: mask end of receive transfer interrupt ? endtx: mask end of transmit interrupt ? ovre: mask overrun error interrupt ? frame: mask framing error interrupt ? pare: mask parity error interrupt ? txempty: mask txempty interrupt ? txbufe: mask txbufe interrupt ? rxbuff: mask rxbuff interrupt ? commtx: mask commtx interrupt ? commrx: mask commrx interrupt 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 commrx commtx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy
390 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 30.5.6 debug unit status register name: dbgu_sr address: 0xfffff214 access type: read-only ? rxrdy: receiver ready 0 = no character has been received since the last re ad of the dbgu_rhr or the receiver is disabled. 1 = at least one complete character has been received, transferred to dbgu_rhr and not yet read. ? txrdy: transmitter ready 0 = a character has been written to dbgu_thr and not yet transferred to the shift register, or the transmitter is disabled. 1 = there is no character written to dbgu_thr not yet transferred to the shift register. ? endrx: end of receiver transfer 0 = the end of transfer signal from the receiver peripheral data controller channel is inactive. 1 = the end of transfer signal from the receiver peripheral data controller channel is active. ? endtx: end of transmitter transfer 0 = the end of transfer signal from the transmitter peripheral data controller channel is inactive. 1 = the end of transfer signal from the transmitter peripheral data controller channel is active. ? ovre: overrun error 0 = no overrun error has occurred since the last rststa. 1 = at least one overrun error has occurred since the last rststa. ? frame: framing error 0 = no framing error has occurred since the last rststa. 1 = at least one framing error has occurred since the last rststa. ? pare: parity error 0 = no parity error has occurred since the last rststa. 1 = at least one parity error has occurred since the last rststa. ? txempty: transmitter empty 0 = there are characters in dbgu_thr, or characters being processed by the transmitter, or the transmitter is disabled. 1 = there are no characters in dbgu_thr and there ar e no characters being processed by the transmitter. 31 30 29 28 27 26 25 24 commrx commtx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy
391 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? txbufe: transmission buffer empty 0 = the buffer empty signal from the transmitter pdc channel is inactive. 1 = the buffer empty signal from the transmitter pdc channel is active. ? rxbuff: receive buffer full 0 = the buffer full signal from the receiver pdc channel is inactive. 1 = the buffer full signal from the receiver pdc channel is active. ? commtx: debug communication channel write status 0 = commtx from the arm processor is inactive. 1 = commtx from the arm processor is active. ? commrx: debug communication channel read status 0 = commrx from the arm processor is inactive. 1 = commrx from the arm processor is active.
392 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 30.5.7 debug unit receiver holding register name: dbgu_rhr address: 0xfffff218 access type: read-only ? rxchr: received character last received character if rxrdy is set. 30.5.8 debug unit transmit holding register name: dbgu_thr address: 0xfffff21c access type: write-only ? txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rxchr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 txchr
393 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 30.5.9 debug unit baud ra te generator register name: dbgu_brgr address: 0xfffff220 access type: read-write ? cd: clock divisor 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cd 76543210 cd cd baud rate clock 0 disabled 1mck 2 to 65535 mck / (cd x 16)
394 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 30.5.10 debug unit chip id register name: dbgu_cidr address: 0xfffff240 access type: read-only ? version: version of the device current version of the device. ? eproc: embedded processor ? nvpsiz: nonvolatile program memory size 31 30 29 28 27 26 25 24 ext nvptyp arch 23 22 21 20 19 18 17 16 arch sramsiz 15 14 13 12 11 10 9 8 nvpsiz2 nvpsiz 76543210 eproc version eproc processor 0 0 1 arm946es 0 1 0 arm7tdmi 100arm920t 1 0 1 arm926ejs nvpsiz size 0000none 00018k bytes 001016k bytes 001132k bytes 0100reserved 010164k bytes 0110reserved 0111128k bytes 1000reserved 1001256k bytes 1010512k bytes 1011reserved 11001024k bytes 1101reserved 11102048k bytes 1111reserved
395 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? nvpsiz2 second nonvolatile program memory size ? sramsiz: internal sram size nvpsiz2 size 0000none 00018k bytes 001016k bytes 001132k bytes 0100reserved 010164k bytes 0110reserved 0111128k bytes 1000reserved 1001256k bytes 1010512k bytes 1011reserved 11001024k bytes 1101reserved 11102048k bytes 1111reserved sramsiz size 0000reserved 00011k bytes 00102k bytes 00116k bytes 0100112k bytes 01014k bytes 011080k bytes 0111160k bytes 10008k bytes 100116k bytes 101032k bytes 101164k bytes 1100128k bytes 1101256k bytes 111096k bytes 1111512k bytes
396 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? arch: architecture identifier ? nvptyp: nonvolatile program memory type ? ext: extension flag 0 = chip id has a single register definition without extension 1 = an extended chip id exists. arch architecture hex bin 0x19 0001 1001 at91sam9xx series 0x29 0010 1001 at91sam9xexx series 0x34 0011 0100 at91x34 series 0x37 0011 0111 cap7 series 0x39 0011 1001 cap9 series 0x3b 0011 1011 cap11 series 0x40 0100 0000 at91x40 series 0x42 0100 0010 at91x42 series 0x55 0101 0101 at91x55 series 0x60 0110 0000 at91sam7axx series 0x61 0110 0001 at91sam7aqxx series 0x63 0110 0011 at91x63 series 0x70 0111 0000 at91sam7sxx series 0x71 0111 0001 at91sam7xcxx series 0x72 0111 0010 at91sam7sexx series 0x73 0111 0011 at91sam7lxx series 0x75 0111 0101 at91sam7xxx series 0x92 1001 0010 at91x92 series 0xf0 1111 0000 at75cxx series nvptyp memory 000rom 0 0 1 romless or on-chip flash 1 0 0 sram emulating rom 0 1 0 embedded flash memory 011 rom and embedded flash memory nvpsiz is rom size nvpsiz2 is flash size
397 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 30.5.11 debug unit chip id extension register name: dbgu_exid address: 0xfffff244 access type: read-only ? exid: chip id extension reads 0 if the bit ext in dbgu_cidr is 0. 31 30 29 28 27 26 25 24 exid 23 22 21 20 19 18 17 16 exid 15 14 13 12 11 10 9 8 exid 76543210 exid
398 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 30.5.12 debug unit force ntrst register name: dbgu_fnr address: 0xfffff248 access type: read-write ? fntrst: force ntrst 0 = ntrst of the arm processor?s tap controller is driven by the power_on_reset signal. 1 = ntrst of the arm processor?s tap controller is held low.b 31 30 29 28 27 26 25 24 ??????? ? 23 22 21 20 19 18 17 16 ??????? ? 15 14 13 12 11 10 9 8 ??????? ? 7654321 0 ??????? fntrst
399 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 31. parallel input/outp ut controller (pio) 31.1 description the parallel input/output controller (pio) manages up to 32 fully programmable input/output lines. each i/o line may be dedicated as a general-purpose i/o or be assigned to a function of an embedded peripheral. this assures effective optimization of the pins of a product. each i/o line is associated with a bit number in all of the 32-bit registers of the 32-bit wide user interface. each i/o line of the pio controller features: ? an input change interrupt enabling level change detection on any i/o line. ? a glitch filter providing rejection of pulses lower than one-half of clock cycle. ? multi-drive capability similar to an open drain i/o line. ? control of the the pull-up of the i/o line. ? input visibility and output control. the pio controller also features a synchronous output providing up to 32 bits of data output in a single write operation.
400 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 31.2 block diagram figure 31-1. block diagram figure 31-2. application block diagram embedded peripheral embedded peripheral pio interrupt pio controller up to 32 pins pmc up to 32 peripheral ios up to 32 peripheral ios pio clock apb aic data, enable pin 31 pin 1 pin 0 data, enable on-chip peripherals pio controller on-chip peripheral drivers control & command driver keyboard driver keyboard driver general purpose i/os external devices
401 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 31.3 product dependencies 31.3.1 pin multiplexing each pin is configurable, according to product definition as either a general-purpose i/o line only, or as an i/o line multiplexed with one or two peripheral i/os. as the multiplexing is hard- ware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the pio controllers required by their application. when an i/o line is general-purpose only, i.e. not multiplexed with any peripheral i/o, programming of the pio controller regarding the assignment to a peripheral has no effect and only the pio con- troller can control how the pin is driven by the product. 31.3.2 external interrupt lines the interrupt signals fiq and irq0 to irqn are most generally multiplexed through the pio controllers. however, it is not necessary to assign the i/o line to the interrupt function as the pio controller has no effect on inputs and the interrupt lines (fiq or irqs) are used only as inputs. 31.3.3 power management the power management controller controls the pio controller clock in order to save power. writing any of the registers of the user interface does not require the pio controller clock to be enabled. this means that the configuration of the i/o lines does not require the pio controller clock to be enabled. however, when the clock is disabled, not all of t he features of the pio controller are available. note that the input change interrupt and the read of the pin level require the clock to be validated. after a hardware reset, the pio clock is disabled by default. the user must configure the power management controller before any access to the input line information. 31.3.4 interrupt generation for interrupt handling, the pio controllers are considered as user peripherals. this means that the pio controller interrupt lines are connected among the interrupt sources 2 to 31. refer to the pio controller peripheral identifier in the produc t description to identify the interrupt sources dedicated to the pio controllers. the pio controller interrupt can be generated only if the pio controller clock is enabled.
402 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 31.4 functional description the pio controller features up to 32 fully-programmable i/o lines. most of the control logic asso- ciated to each i/o is represented in figure 31-3 . in this description each signal shown represents but one of up to 32 possible indexes. figure 31-3. i/o line control logic 1 0 1 0 1 0 glitch filter peripheral b input peripheral a input 1 0 pio_ifdr[0] pio_ifsr[0] pio_ifer[0] edge detector pio_pdsr[0] pio_isr[0] pio_idr[0] pio_imr[0] pio_ier[0] pio interrupt (up to 32 possible inputs) pio_isr[31] pio_idr[31] pio_imr[31] pio_ier[31] pad 1 0 pio_pudr[0] pio_pusr[0] pio_puer[0] pio_mddr[0] pio_mdsr[0] pio_mder[0] pio_codr[0] pio_odsr[0] pio_sodr[0] pio_pdr[0] pio_psr[0] pio_per[0] 1 0 1 0 pio_bsr[0] pio_absr[0] pio_asr[0] peripheral b output enable peripheral a output enable peripheral b output peripheral a output pio_odr[0] pio_osr[0] pio_oer[0]
403 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 31.4.1 pull-up resistor control each i/o line is designed with an embedded pull-up resistor. the pull-up resistor can be enabled or disabled by writing respectively pio_puer (pull-up enable register) and pio_pudr (pull- up disable resistor). writing in these registers re sults in setting or clearing the corresponding bit in pio_pusr (pull-up status register). readi ng a 1 in pio_pusr means the pull-up is dis- abled and reading a 0 means the pull-up is enabled. control of the pull-up resistor is possible regardless of the configuration of the i/o line. after reset, all of the pull-ups are enabled, i.e. pio_pusr resets at the value 0x0. 31.4.2 i/o line or peripheral function selection when a pin is multiplexed with one or two periph eral functions, the selection is controlled with the registers pio_per (pio enable register) and pio_pdr (pio disable register). the regis- ter pio_psr (pio status register) is the resu lt of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the pio controller. a value of 0 indicates that the pin is controlled by the co rresponding on-chip peripheral selected in the pio_absr (ab select status regist er). a value of 1 indicates the pin is controlled by the pio controller. if a pin is used as a general purpose i/o line (not multiplexed with an on-chip peripheral), pio_per and pio_pdr have no effect and pio_psr returns 1 for the corresponding bit. after reset, most generally, the i/o lines are controlled by the pio controller, i.e. pio_psr resets at 1. however, in some events, it is important that pio lines are controlled by the periph- eral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). thus, the reset value of pio_psr is defined at the product level, depending on the multiplexing of the device. 31.4.3 peripheral a or b selection the pio controller provides multiplexing of up to two peripheral functions on a single pin. the selection is performed by writing pio_asr (a select register) and pio_bsr (select b regis- ter). pio_absr (ab select status register) indicates which peripheral line is currently selected. for each pin, the corresponding bit at level 0 means peripheral a is selected whereas the corre- sponding bit at level 1 indicates that peripheral b is selected. note that multiplexing of peripheral lines a and b only affects the output line. the peripheral input lines are always connected to the pin input. after reset, pio_absr is 0, thus indicating that all th e pio lines are config ured on peripheral a. however, peripheral a generally does not drive the pin as the pio controller resets in i/o line mode. writing in pio_asr an d pio_bsr manages pio_absr regardless of th e configuration of the pin. however, assignment of a pin to a peripheral function requires a write in the corresponding peripheral selection register (pio_asr or pio_bsr) in addition to a write in pio_pdr. 31.4.4 output control when the i/0 line is assigned to a peripheral func tion, i.e. the corresponding bit in pio_psr is at 0, the drive of the i/o line is controlled by the peripheral. peripheral a or b, depending on the value in pio_absr, determines whet her the pin is driven or not. when the i/o line is controlled by the pio controller, the pin can be configured to be driven. this is done by writing pio_oer (output enable register) and pio_odr (output disable register).
404 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary the results of these write operations are detected in pio_osr (output status register). when a bit in this register is at 0, the corresponding i/o line is used as an input only. when the bit is at 1, the corresponding i/o line is driven by the pio controller. the level driven on an i/o line can be determined by writing in pio_sodr (set output data register) and pio_codr (cle ar output data register). these write operations respectively set and clear pio_odsr (output data status register ), which represents the data driven on the i/o lines. writing in pio_oer and pio_odr manage s pio_osr whether the pin is configured to be controlled by the pio controller or assigned to a peripheral function. this enables configura- tion of the i/o line prior to setting it to be managed by the pio controller. similarly, writing in pio_sodr and pio_codr effects pio_odsr. this is important as it defines the first level driven on the i/o line. 31.4.5 synchronous data output controlling all paralle l busses using several pios requires two successive write operations in the pio_sodr and pio_codr registers. this may lead to unexpected transient values. the pio controller offers a direct control of pio outputs by single write access to pio_odsr (output data status register). only bits unmasked by pio_owsr (output write status register) are written. the mask bits in the pio_owsr are se t by writing to pio_ower (output write enable register) and cleared by writing to pio_owdr (output write disable register). after reset, the synchronous data output is disabled on all the i/o lines as pio_owsr resets at 0x0. 31.4.6 multi drive control (open drain) each i/o can be independently programmed in open drain by using the multi drive feature. this feature permits several drivers to be connected on the i/o line which is driven low only by each device. an external pull-up resistor (or enabling of the internal one) is generally required to guar- antee a high level on the line. the multi drive feature is controlled by pio_mder (multi-driver enable register) and pio_mddr (multi-driver disable register). the multi drive can be selected whether the i/o line is controlled by the pio controller or assigned to a peripheral function. pio_mdsr (multi-driver status register) indicates the pins that are configured to support external drivers. after reset, the multi drive feature is disabled on all pins, i.e. pio_mdsr resets at value 0x0. 31.4.7 output line timings figure 31-4 shows how the outputs are driven either by writing pio_sodr or pio_codr, or by directly writing pio_odsr. this last case is va lid only if the corresponding bit in pio_owsr is set. figure 31-4 also shows when the feedback in pio_pdsr is available.
405 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 31-4. output line timings 31.4.8 inputs the level on each i/o line can be read through pio_pdsr (pin data status register). this reg- ister indicates the level of the i/o lines regardless of their configuration, whether uniquely as an input or driven by the pio controller or driven by a peripheral. reading the i/o line levels requires the clock of the pio controller to be enabled, otherwise pio_pdsr reads the levels present on the i/o line at the time the clock was disabled. 31.4.9 input glitch filtering optional input glitch filters are independently programmable on each i/o line. when the glitch fil- ter is enabled, a glitch with a duration of less than 1/2 master clock (mck) cycle is automatically rejected, while a pulse with a duration of 1 mast er clock cycle or more is accepted. for pulse durations between 1/2 master clock cycle and 1 master clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. thus for a pulse to be visible it must exceed 1 master clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 master clock cycle. the filter introduces one master clock cycle latency if the pin level change occurs before a rising edge. however, this latency does not appear if the pin level chan ge occurs before a falling ed ge. this is illustrated in figure 31-5 . the glitch filters are controlled by the regist er set; pio_ifer (input filter enable register), pio_ifdr (input filter disable register) and pio_ifsr (input filter status register). writing pio_ifer and pio_ifdr respectively sets and clears bits in pio_ifsr. this last register enables the glitch filt er on the i/o lines. when the glitch filter is enabled, it does not modify the behavior of the inputs on the peripherals. it acts only on the value read in pio_pdsr and on the input change interrupt detection. the glitch filters require that the pio controller clock is enabled. 2 cycles apb access 2 cycles apb access mck write pio_sodr write pio_odsr at 1 pio_odsr pio_pdsr write pio_codr write pio_odsr at 0
406 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 31-5. input glitch filter timing 31.4.10 input change interrupt the pio controller can be programmed to generate an interrupt when it detects an input change on an i/o line. the input change interrupt is cont rolled by writing pio_ier (interrupt enable register) and pio_idr (interrupt disable register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in pio_imr (interrupt mask register). as input change detection is possible only by comparing two successive samplings of the input of the i/o line, the pio controller clock must be enabled. the input change interrupt is available, regardless of the configuration of the i/o line, i.e. configured as an input only, con- trolled by the pio controller or assigned to a peripheral function. when an input change is detected on an i/o line, the corresponding bit in pio_isr (interrupt status register) is set. if the corresponding bit in pio_imr is set, the pio controller interrupt line is asserted. the interrupt signals of the thirty-two channels are ored-wired together to gen- erate a single interrupt signal to the advanced interrupt controller. when the software reads pio_isr, all the interrupts are automatically cleared. this signifies that all the interrupts that are pending when pio_isr is read must be handled. figure 31-6. input change interrupt timings 31.5 i/o lines programming example the programing example as shown in table 31-1 below is used to define the following configuration. ? 4-bit output port on i/o lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up resistor mck pin level pio_pdsr if pio_ifsr = 0 pio_pdsr if pio_ifsr = 1 1 cycle 1 cycle 1 cycle up to 1.5 cycles 2 cycles up to 2.5 cycles up to 2 cycles 1 cycle 1 cycle mck pin level read pio_isr apb access pio_isr apb access
407 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? four output signals on i/o lines 4 to 7 (to drive leds for example), driven high and low, no pull-up resistor ? four input signals on i/o lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts ? four input signals on i/o line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter ? i/o lines 16 to 19 assigned to peripheral a functions with pull-up resistor ? i/o lines 20 to 23 assigned to peripheral b functions, no pull-up resistor ? i/o line 24 to 27 assigned to peripheral a with input change interrupt and pull-up resistor table 31-1. programming example register value to be written pio_per 0x0000 ffff pio_pdr 0x0fff 0000 pio_oer 0x0000 00ff pio_odr 0x0fff ff00 pio_ifer 0x0000 0f00 pio_ifdr 0x0fff f0ff pio_sodr 0x0000 0000 pio_codr 0x0fff ffff pio_ier 0x0f00 0f00 pio_idr 0x00ff f0ff pio_mder 0x0000 000f pio_mddr 0x0fff fff0 pio_pudr 0x00f0 00f0 pio_puer 0x0f0f ff0f pio_asr 0x0f0f 0000 pio_bsr 0x00f0 0000 pio_ower 0x0000 000f pio_owdr 0x0fff fff0
408 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 31.6 parallel input/output cont roller (pio) user interface each i/o line controlled by the pio controller is associated with a bit in each of the pio control- ler user interface registers. each register is 32 bits wide. if a parallel i/o line is not defined, writing to the corresponding bits has no effect. undefined bits read zero. if the i/o line is not mul- tiplexed with any peripheral, the i/o line is controlled by the pio controller and pio_psr returns 1 systematically. table 31-2. register mapping offset register name access reset 0x0000 pio enable register pio_per write-only ? 0x0004 pio disable register pio_pdr write-only ? 0x0008 pio status register pio_psr read-only (1) 0x000c reserved 0x0010 output enable register pio_oer write-only ? 0x0014 output disable register pio_odr write-only ? 0x0018 output status regist er pio_osr read-only 0x0000 0000 0x001c reserved 0x0020 glitch input filter enab le register pio_ifer write-only ? 0x0024 glitch input filter disab le register pio_ifdr write-only ? 0x0028 glitch input filter status register pio_ifsr read-only 0x0000 0000 0x002c reserved 0x0030 set output data register pio_sodr write-only ? 0x0034 clear output data register pio_codr write-only 0x0038 output data status register pio_odsr read-only or (2) read/write ? 0x003c pin data status register pio_pdsr read-only (3) 0x0040 interrupt enable register pio_ier write-only ? 0x0044 interrupt disable register pio_idr write-only ? 0x0048 interrupt mask register pio_imr read-only 0x00000000 0x004c interrupt status register (4) pio_isr read-only 0x00000000 0x0050 multi-driver enable register pio_mder write-only ? 0x0054 multi-driver disable register pio_mddr write-only ? 0x0058 multi-driver status re gister pio_mdsr read-only 0x00000000 0x005c reserved 0x0060 pull-up disable register pio_pudr write-only ? 0x0064 pull-up enable register pio_puer write-only ? 0x0068 pad pull-up status regi ster pio_pusr read-only 0x00000000 0x006c reserved
409 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary notes: 1. reset value of pio_psr depends on the product implementation. 2. pio_odsr is read-only or read/write depending on pio_owsr i/o lines. 3. reset value of pio_pdsr depends on the level of the i/o line s. reading the i/o line levels requires the clock of the pio controller to be enabled, ot herwise pio_pdsr reads the levels present on the i/o line at the time the clock was disabled. 4. pio_isr is reset at 0x0. however, the first read of the register may read a different value as input changes may have occurred. 5. only this set of registers clears the stat us by writing 1 in the first register and sets the status by writing 1 in the secon d register. 0x0070 peripheral a select register (5) pio_asr write-only ? 0x0074 peripheral b select register (5) pio_bsr write-only ? 0x0078 ab status register (5) pio_absr read-only 0x00000000 0x007c to 0x009c reserved 0x00a0 output write enab le pio_ower write-only ? 0x00a4 output write disab le pio_owdr write-only ? 0x00a8 output write status re gister pio_owsr read-only 0x00000000 0x00ac reserved table 31-2. register mapping (continued) offset register name access reset
410 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 31.6.1 pio controller pio enable register name: pio_per addresses: 0xfffff400 (pioa), 0xfffff600 (piob), 0xfffff800 (pioc) access type: write-only ? p0-p31: pio enable 0 = no effect. 1 = enables the pio to control the corresponding pin (disables peripheral control of the pin). 31.6.2 pio controller pio disable register name: pio_pdr addresses: 0xfffff404 (pioa), 0xfffff604 (piob), 0xfffff804 (pioc) access type: write-only ? p0-p31: pio disable 0 = no effect. 1 = disables the pio from controllin g the corresponding pin (enables peripheral contro l of the pin). 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
411 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 31.6.3 pio controller pio status register name: pio_psr addresses: 0xfffff408 (pioa), 0xfffff608 (piob), 0xfffff808 (pioc) access type: read-only ? p0-p31: pio status 0 = pio is inactive on the corresponding i/o line (peripheral is active). 1 = pio is active on the corresponding i/o line (peripheral is inactive). 31.6.4 pio controller output enable register name: pio_oer addresses: 0xfffff410 (pioa), 0xfffff610 (piob), 0xfffff810 (pioc) access type: write-only ? p0-p31: output enable 0 = no effect. 1 = enables the output on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
412 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 31.6.5 pio controller output disable register name: pio_odr addresses: 0xfffff414 (pioa), 0xfffff614 (piob), 0xfffff814 (pioc) access type: write-only ? p0-p31: output disable 0 = no effect. 1 = disables the output on the i/o line. 31.6.6 pio controller output status register name: pio_osr addresses: 0xfffff418 (pioa), 0xfffff618 (piob), 0xfffff818 (pioc) access type: read-only ? p0-p31: output status 0 = the i/o line is a pure input. 1 = the i/o line is enabled in output. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
413 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 31.6.7 pio controller input filter enable register name: pio_ifer addresses: 0xfffff420 (pioa), 0xfffff620 (piob), 0xfffff820 (pioc) access type: write-only ? p0-p31: input filter enable 0 = no effect. 1 = enables the input glitch filter on the i/o line. 31.6.8 pio controller input filter disable register name: pio_ifdr addresses: 0xfffff424 (pioa), 0xfffff624 (piob), 0xfffff824 (pioc) access type: write-only ? p0-p31: input filter disable 0 = no effect. 1 = disables the input glitch filter on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
414 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 31.6.9 pio controller input filter status register name: pio_ifsr addresses: 0xfffff428 (pioa), 0xfffff628 (piob), 0xfffff828 (pioc) access type: read-only ? p0-p31: input filer status 0 = the input glitch filter is disabled on the i/o line. 1 = the input glitch filter is enabled on the i/o line. 31.6.10 pio controller set output data register name: pio_sodr addresses: 0xfffff430 (pioa), 0xfffff630 (piob), 0xfffff830 (pioc) access type: write-only ? p0-p31: set output data 0 = no effect. 1 = sets the data to be driven on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
415 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 31.6.11 pio controller clear output data register name: pio_codr addresses: 0xfffff434 (pioa), 0xfffff634 (piob), 0xfffff834 (pioc) access type: write-only ? p0-p31: set output data 0 = no effect. 1 = clears the data to be driven on the i/o line. 31.6.12 pio controller output data status register name: pio_odsr addresses: 0xfffff438 (pioa), 0xfffff638 (piob), 0xfffff838 (pioc) access type: read-only or read/write ? p0-p31: output data status 0 = the data to be driven on the i/o line is 0. 1 = the data to be driven on the i/o line is 1. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
416 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 31.6.13 pio controller pin data status register name: pio_pdsr addresses: 0xfffff43c (pioa), 0xfffff63c (piob), 0xfffff83c (pioc) access type: read-only ? p0-p31: output data status 0 = the i/o line is at level 0. 1 = the i/o line is at level 1. 31.6.14 pio controller interrupt enable register name: pio_ier addresses: 0xfffff440 (pioa), 0xfffff640 (piob), 0xfffff840 (pioc) access type: write-only ? p0-p31: input change interrupt enable 0 = no effect. 1 = enables the input change interrupt on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
417 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 31.6.15 pio controller interrupt disable register name: pio_idr addresses: 0xfffff444 (pioa), 0xfffff644 (piob), 0xfffff844 (pioc) access type: write-only ? p0-p31: input change interrupt disable 0 = no effect. 1 = disables the input change interrupt on the i/o line. 31.6.16 pio controller interrupt mask register name: pio_imr addresses: 0xfffff448 (pioa), 0xfffff648 (piob), 0xfffff848 (pioc) access type: read-only ? p0-p31: input change interrupt mask 0 = input change interrupt is disabled on the i/o line. 1 = input change interrupt is enabled on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
418 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 31.6.17 pio controller interrupt status register name: pio_isr addresses: 0xfffff44c (pioa), 0xfffff64c (piob), 0xfffff84c (pioc) access type: read-only ? p0-p31: input change interrupt status 0 = no input change has been detected on the i/o line since pio_isr was last read or since reset. 1 = at least one input change has been detected on the i/o line since pio_isr was last read or since reset. 31.6.18 pio multi-driver enable register name: pio_mder addresses: 0xfffff450 (pioa), 0xfffff650 (piob), 0xfffff850 (pioc) access type: write-only ? p0-p31: multi drive enable. 0 = no effect. 1 = enables multi drive on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
419 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 31.6.19 pio multi-driver disable register name: pio_mddr addresses: 0xfffff454 (pioa), 0xfffff654 (piob), 0xfffff854 (pioc) access type: write-only ? p0-p31: multi drive disable. 0 = no effect. 1 = disables multi drive on the i/o line. 31.6.20 pio multi-driver status register name: pio_mdsr addresses: 0xfffff458 (pioa), 0xfffff658 (piob), 0xfffff858 (pioc) access type: read-only ? p0-p31: multi drive status. 0 = the multi drive is disabled on the i/o line. the pin is driven at high and low level. 1 = the multi drive is enabled on the i/o lin e. the pin is driven at low level only. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
420 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 31.6.21 pio pull up disable register name: pio_pudr addresses: 0xfffff460 (pioa), 0xfffff660 (piob), 0xfffff860 (pioc) access type: write-only ? p0-p31: pull up disable. 0 = no effect. 1 = disables the pull up resistor on the i/o line. 31.6.22 pio pull up enable register name: pio_puer addresses: 0xfffff464 (pioa), 0xfffff664 (piob), 0xfffff864 (pioc) access type: write-only ? p0-p31: pull up enable. 0 = no effect. 1 = enables the pull up resistor on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
421 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 31.6.23 pio pull up status register name: pio_pusr addresses: 0xfffff468 (pioa), 0xfffff668 (piob), 0xfffff868 (pioc) access type: read-only ? p0-p31: pull up status. 0 = pull up resistor is enabled on the i/o line. 1 = pull up resistor is disabled on the i/o line. 31.6.24 pio peripheral a select register name: pio_asr addresses: 0xfffff470 (pioa), 0xfffff670 (piob), 0xfffff870 (pioc) access type: write-only ? p0-p31: peripheral a select. 0 = no effect. 1 = assigns the i/o line to the peripheral a function. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
422 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 31.6.25 pio peripheral b select register name: pio_bsr addresses: 0xfffff474 (pioa), 0xfffff674 (piob), 0xfffff874 (pioc) access type: write-only ? p0-p31: peripheral b select. 0 = no effect. 1 = assigns the i/o line to the peripheral b function. 31.6.26 pio peripheral a b status register name: pio_absr addresses: 0xfffff478 (pioa), 0xfffff678 (piob), 0xfffff878 (pioc) access type: read-only ? p0-p31: peripheral a b status. 0 = the i/o line is assigned to the peripheral a. 1 = the i/o line is assigned to the peripheral b. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
423 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 31.6.27 pio output write enable register name: pio_ower addresses: 0xfffff4a0 (pioa), 0xfffff6a0 (piob), 0xfffff8a0 (pioc) access type: write-only ? p0-p31: output write enable. 0 = no effect. 1 = enables writing pio_odsr for the i/o line. 31.6.28 pio output write disable register name: pio_owdr addresses: 0xfffff4a4 (pioa), 0xfffff6a4 (piob), 0xfffff8a4 (pioc) access type: write-only ? p0-p31: output write disable. 0 = no effect. 1 = disables writing pio_odsr for the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
424 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 31.6.29 pio output write status register name: pio_owsr addresses: 0xfffff4a8 (pioa), 0xfffff6a8 (piob), 0xfffff8a8 (pioc) access type: read-only ? p0-p31: output write status. 0 = writing pio_odsr does not affect the i/o line. 1 = writing pio_odsr affects the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
425 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 32. serial peripheral interface (spi) 32.1 description the serial peripheral interface (spi) circuit is a synchronous serial data link that provides com- munication with external devices in master or slave mode. it also enables communication between processors if an external processor is connected to the system. the serial peripheral interface is essentially a shift register that serially transmits data bits to other spis. during a data transfer, one spi syste m acts as the ?master?' which controls the data flow, while the other devices act as ?slaves'' whic h have data shifted into and out by the master. different cpus can take turn being masters (multiple master protocol opposite to single master protocol where one cpu is always the master while all of the others are always slaves) and one master may simultaneously shift da ta into multiple slaves. howeve r, only one slave may drive its output to write data back to the master at any given time. a slave device is selected when the master asse rts its nss signal. if multiple slave devices exist, the master generates a separate slav e select signal for each slave (npcs). the spi system consists of two data lines and two control lines: ? master out slave in (mosi): this data line supplies the output data from the master shifted into the input(s) of the slave(s). ? master in slave out (miso): this data line supplies the output data from a slave to the input of the master. there may be no more than one slave transmitting data during any particular transfer. ? serial clock (spck): this control line is driven by the master and regulates the flow of the data bits. the master may transmit data at a variety of baud rates; the spck line cycles once for each bit that is transmitted. ? slave select (nss): this control line allows slaves to be turned on and off by hardware.
426 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 32.2 block diagram figure 32-1. block diagram 32.3 application block diagram figure 32-2. application block diagram: single master/multiple slave implementation spi interface interrupt control pio pdc pmc mck spi interrupt spck miso mosi npcs0/nss npcs1 npcs2 npcs3 apb spi master spck miso mosi npcs0 npcs1 npcs2 spck miso mosi nss slave 0 spck miso mosi nss slave 1 spck miso mosi nss slave 2 nc npcs3
427 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 32.4 signal description 32.5 product dependencies 32.5.1 i/o lines the pins used for interfacing the compliant ex ternal devices may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the spi pins to their peripheral functions. 32.5.2 power management the spi may be clocked through the power management controller (pmc), thus the program- mer must first configure the pmc to enable the spi clock. 32.5.3 interrupt the spi interface has an interrupt line connected to the advanced interrupt controller (aic). handling the spi interrupt requires programming the aic before configuring the spi. table 32-1. signal description pin name pin description type master slave miso master in slave out input output mosi master out slave in output input spck serial clock output input npcs1-npcs3 peripheral chip selects output unused npcs0/nss peripheral chip select/slave select output input
428 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 32.6 functional description 32.6.1 modes of operation the spi operates in master mode or in slave mode. operation in master mode is programmed by writing at 1 the mstr bit in the mode register. the pins npcs0 to npcs3 are all configured as outputs, the spck pin is driven, the miso line is wired on the receiver input and the mosi line driven as an output by the transmitter. if the mstr bit is written at 0, the spi operates in slave mode. the miso line is driven by the transmitter output, the mosi line is wired on the re ceiver input, the spck pin is driven by the transmitter to synchronize the receiver. the npcs0 pin becomes an input, and is used as a slave select signal (nss). the pins npcs1 to npcs3 are not driven and can be used for other purposes. the data transfers are identically programmable for both modes of operations. the baud rate generator is activated only in master mode. 32.6.2 data transfer four combinations of polarity and phase are available for data transfers. the clock polarity is programmed with the cpol bit in the chip select register. the clock phase is programmed with the ncpha bit. these two parameters determine th e edges of the clock signal on which data is driven and sampled. each of the two parameters has two possible states, resulting in four possi- ble combinations that are incompatible with one another. thus, a master/slave pair must use the same parameter pair values to communicate. if multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a dif- ferent slave. table 32-2 shows the four modes and corresponding parameter settings. figure 32-3 and figure 32-4 show examples of data transfers. table 32-2. spi bus protocol mode spi mode cpol ncpha 001 100 211 310
429 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 32-3. spi transfer format (ncpha = 1, 8 bits per transfer) figure 32-4. spi transfer format (ncpha = 0, 8 bits per transfer) 6 * spck (cpol = 0) spck (cpol = 1) mosi (from master) miso (from slave) nss (to slave) spck cycle (for reference) msb msb lsb lsb 6 6 5 5 4 4 3 3 2 2 1 1 * not defined, but normally msb of previous character received. 1 2345 78 6 * spck (cpol = 0) spck (cpol = 1) 1 2345 7 mosi (from master) miso (from slave) nss (to slave) spck cycle (for reference) 8 msb msb lsb lsb 6 6 5 5 4 4 3 3 1 1 * not defined but normally lsb of previous character transmitted. 2 2 6
430 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 32.6.3 master mode operations when configured in master mode, the spi operates on the clock generated by the internal pro- grammable baud rate generator. it fully controls the data transfers to and from the slave(s) connected to the spi bus. the spi drives the chip select line to the slave and the serial clock signal (spck). the spi features two holding registers, the transmit data register and the receive data regis- ter, and a single shift register. the holding registers maintain the data flow at a constant rate. after enabling the spi, a data transfer begins when the processor writes to the spi_tdr (trans- mit data register). the written data is immediat ely transferred in the shift register and transfer on the spi bus starts. while the data in the shift register is shifted on the mosi line, the miso line is sampled and shifted in the shift register. transmission cannot occur without reception. before writing the tdr, the pcs field must be set in order to select a slave. if new data is written in spi_tdr during the transfer, it stays in it until the current transfer is completed. then, the received data is transferred from the shift register to spi_rdr, the data in spi_tdr is loaded in the shift register and a new transfer starts. the transfer of a data written in spi_tdr in t he shift register is indicated by the tdre bit (transmit data register empty) in the status register (spi_sr). when new data is written in spi_tdr, this bit is cleared. the tdre bit is used to trigger the transmit pdc channel. the end of transfer is indicated by the txempty flag in the spi_sr register. if a transfer delay (dlybct) is greater than 0 for the last transfer, txempty is set after the completion of said delay. the master clock (mck) can be switched off at this time. the transfer of received data from the shift register in spi_rdr is indicated by the rdrf bit (receive data register full) in the status register (spi_sr). when the received data is read, the rdrf bit is cleared. if the spi_rdr (receive data register) has not been read before new data is received, the overrun error bit (ovres) in spi_sr is set. as long as this flag is set, data is loaded in spi_rdr. the user has to read the status register to clear the ovres bit. figure 32-5 , shows a block diagram of the spi when operating in master mode. figure 32-6 on page 432 shows a flow chart describing how transfers are handled.
431 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 32.6.3.1 master mode block diagram figure 32-5. master mode block diagram shift register spck mosi lsb msb miso spi_rdr rd spi clock tdre spi_tdr td rdrf ovres spi_csr0..3 cpol ncpha bits mck baud rate generator spi_csr0..3 scbr npcs3 npcs0 npcs2 npcs1 npcs0 0 1 ps spi_mr pcs spi_tdr pcs modf current peripheral spi_rdr pcs spi_csr0..3 csaat pcsdec modfdis mstr
432 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 32.6.3.2 master mode flow diagram figure 32-6. master mode flow diagram spi enable csaat ? ps ? 1 0 0 1 1 npcs = spi_tdr(pcs) npcs = spi_mr(pcs) delay dlybs serializer = spi_tdr(td) tdre = 1 data transfer spi_rdr(rd) = serializer rdrf = 1 tdre ? npcs = 0xf delay dlybcs fixed peripheral variable peripheral delay dlybct 0 1 csaat ? 0 tdre ? 1 0 ps ? 0 1 spi_tdr(pcs) = npcs ? no yes spi_mr(pcs) = npcs ? no npcs = 0xf delay dlybcs npcs = spi_tdr(pcs) npcs = 0xf delay dlybcs npcs = spi_mr(pcs), spi_tdr(pcs) fixed peripheral variable peripheral - npcs defines the current chip select - csaat, dlybs, dlybct refer to the fields of the chip select register corresponding to the current chip select - when npcs is 0xf, csaat is 0.
433 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 32.6.3.3 clock generation the spi baud rate clock is generated by dividing the master clock (mck), by a value between 1 and 255. this allows a maximum operating baud rate at up to master clock and a minimum operating baud rate of mck divided by 255. programming the scbr field at 0 is forbidden. tr iggering a transfer while scbr is at 0 can lead to unpredictable results. at reset, scbr is 0 and the user has to program it at a valid value before performing the first transfer. the divisor can be defined independently for each chip select, as it has to be programmed in the scbr field of the chip select registers. this allows the spi to automatically adapt the baud rate for each interfaced peripheral without reprogramming. 32.6.3.4 transfer delays figure 32-7 shows a chip select transfer change and consecutive transfers on the same chip select. three delays can be programmed to modify the transfer waveforms: ? the delay between chip selects, programmable only once for all the ch ip selects by writing the dlybcs field in the mode register. allows insertion of a delay between release of one chip select and before assertion of a new one. ? the delay before spck, independently programmable for each chip select by writing the field dlybs. allows the start of spck to be delayed after the chip select has been asserted. ? the delay between consecutive transfers, independently programmable for each chip select by writing the dlybct field. allows insertion of a delay between two transfers occurring on the same chip select these delays allow the spi to be adapted to the interfaced peripherals and their speed and bus release time. figure 32-7. programmable delays 32.6.3.5 peripheral selection the serial peripherals are selected through the assertion of the npcs0 to npcs3 signals. by default, all the npcs signals are high before and after each transfer. the peripheral selection can be performed in two different ways: ? fixed peripheral select: spi exchanges data with only one peripheral dlybcs dlybs dlybct dlybct chip select 1 chip select 2 spck
434 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? variable peripheral select: data can be exchanged with more than one peripheral fixed peripheral select is activated by writing the ps bit to zero in spi_mr (mode register). in this case, the current peripheral is defined by the pcs field in spi_mr and the pcs field in the spi_tdr has no effect. variable peripheral select is activated by se tting ps bit to one. the pcs field in spi_tdr is used to select the current peripheral. this means that the peripheral selection can be defined for each new data. the fixed peripheral selection allows buffer transfers with a single peripheral. using the pdc is an optimal means, as the size of the data transfer between the memory and the spi is either 8 bits or 16 bits. however, changing the peripheral selection requires the mode register to be reprogrammed. the variable peripheral selection allows buffer transfers with multiple peripherals without repro- gramming the mode register. data written in spi_tdr is 32 bits wide and defines the real data to be transmitted and the peripheral it is desti ned to. using the pdc in this mode requires 32-bit wide buffers, with the data in the lisps and th e pcs and lastxfer fields in the msbs, how- ever the spi still controls the number of bits (8 to16) to be transferre d through miso and mosi lines with the chip select configuration registers. this is not the optimal means in term of mem- ory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor. 32.6.3.6 peripheral chip select decoding the user can program the spi to operate with up to 15 peripherals by decoding the four chip select lines, npcs0 to npcs3 with an external l ogic. this can be enabled by writing the pcs- dec bit at 1 in the mode register (spi_mr). when operating without decoding, the spi makes sure that in any case only one chip select line is activated, i.e. driven low at a time. if two bits are defined low in a pcs field, only the lowest numbered chip select is driven low. when operating with decoding, the spi directly outputs the value defined by the pcs field of either the mode register or the transmit data register (depending on ps). as the spi sets a default value of 0xf on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded. the spi has only four chip select registers, not 15. as a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. as an example, spi_crs0 defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the pcs values 0x0 to 0x3. thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. 32.6.3.7 peripheral deselection when operating normally, as soon as the transfer of the last data written in spi_tdr is com- pleted, the npcs lines all rise. this might lead to runtime error if the processor is too long in responding to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers. to facilitate interfacing with such devices, the chip select regist er can be prog rammed with the csaat bit (chip select active afte r transfer) at 1. this allows th e chip select lines to remain in their current state (low = active) until transfer to another peripheral is required.
435 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 32-8 shows different peripheral deselction cases and the effect of the csaat bit. figure 32-8. peripheral deselection 32.6.3.8 mode fault detection a mode fault is detected when the spi is programmed in master mode and a low level is driven by an external master on the npcs0/nss sign al. npcs0, mosi, miso and spck must be con- figured in open drain through the pio controller, so that external pull up resistors are needed to guarantee high level. when a mode fault is detected, the modf bit in the spi_sr is set until the spi_sr is read and the spi is automatically disabl ed until re-enabled by writing t he spien bit in the spi_cr (con- trol register) at 1. by default, the mode fault detection circuitr y is enabled. the user can disable mode fault detection by setting the modfdis bit in the spi mode register (spi_mr). a npcs[0..3] write spi_tdr tdre npcs[0..3] write spi_tdr tdre npcs[0..3] write spi_tdr tdre dlybcs pcs = a dlybcs dlybct a pcs = b b dlybcs pcs = a dlybcs dlybct a pcs = b b dlybcs dlybct pcs=a a dlybcs dlybct a pcs = a a a dlybct aa csaat = 0 dlybct aa csaat = 1 a
436 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 32.6.4 spi slave mode when operating in slave mode, the spi processes data bits on the clock provided on the spi clock pin (spck). the spi waits for nss to go active before receiving the serial clock from an external master. when nss falls, the clock is validated on the serializer, which processes the number of bits defined by the bits field of the chip select register 0 (spi_csr0). these bits are processed following a phase and a polarity defined respectively by the ncpha and cpol bits of the spi_csr0. note that bits, cpol and ncpha of the other chip select registers have no effect when the spi is programmed in slave mode. the bits are shifted out on the miso line and sampled on the mosi line. (for more information on bits field, see also, the (note:) below the register table; section 32.7.9 ?spi chip select register? on page 449 .) when all the bits are processed, the received data is transferred in the receive data register and the rdrf bit rises. if the spi_rdr (receive data register) has no t been read be fore new data is received, the overrun error bit (ovres) in spi_sr is set. as long as this flag is set, data is loaded in spi_rdr. the user has to read the status register to clear the ovres bit. when a transfer starts, the data shifted out is the data present in the shift register. if no data has been written in the transmit data register (spi_tdr), the la st data received is transferred. if no data has been received since the last reset, all bits are transmitted low, as the shift regis- ter resets at 0. when a first data is written in sp i_tdr, it is transferred immediat ely in the shift register and the tdre bit rises. if new data is wr itten, it remains in spi_tdr unt il a transfer occurs, i.e. nss falls and there is a valid clock on the spck pin. w hen the transfer occurs, the last data written in spi_tdr is transferred in the shift register and the tdre bit rises. this enables frequent updates of critical variables with single transfers. then, a new data is loaded in the shift register from the transmit data register. in case no character is ready to be transmitted, i.e. no character has been written in spi_tdr since the last load from spi_tdr to the shift register, the shift register is not modified and the last received character is retransmitted. figure 32-9 shows a block diagram of the spi when operating in slave mode.
437 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 32-9. slave mode functional bloc diagram shift register spck spiens lsb msb nss mosi spi_rdr rd spi clock tdre spi_tdr td rdrf ovres spi_csr0 cpol ncpha bits spien spidis miso
438 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 32.7 serial peripheral inte rface (spi) user interface table 32-3. register mapping offset register name access reset 0x00 control register spi_cr write-only --- 0x04 mode register spi_mr read-write 0x0 0x08 receive data register spi_rdr read-only 0x0 0x0c transmit data register spi_tdr write-only --- 0x10 status register spi_sr read-only 0x000000f0 0x14 interrupt enable register spi_ier write-only --- 0x18 interrupt disable register spi_idr write-only --- 0x1c interrupt mask register spi_imr read-only 0x0 0x20 - 0x2c reserved 0x30 chip select register 0 spi_csr0 read-write 0x0 0x34 chip select register 1 spi_csr1 read-write 0x0 0x38 chip select register 2 spi_csr2 read-write 0x0 0x3c chip select register 3 spi_csr3 read-write 0x0 0x004c - 0x00f8 reserved ? ? ? 0x004c - 0x00fc reserved ? ? ? 0x100 - 0x124 reserved for the pdc
439 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 32.7.1 spi control register name: spi_cr addresses: 0xfffc8000 (0), 0xfffcc000 (1) access type: write-only ? spien: spi enable 0 = no effect. 1 = enables the spi to transfer and receive data. ? spidis: spi disable 0 = no effect. 1 = disables the spi. as soon as spidis is set, spi finishes its transfer. all pins are set in input mode and no data is received or transmitted. if a transfer is in progress, the transfer is finished before the spi is disabled. if both spien and spidis are equal to one when the control register is written, the spi is disabled. ? swrst: spi software reset 0 = no effect. 1 = reset the spi. a software-triggered hardware reset of the spi interface is performed. the spi is in slave mode after software reset. pdc channels are not affected by software reset. ? lastxfer: last transfer 0 = no effect. 1 = the current npcs will be deasserted afte r the character written in td has been transferred. when csaat is set, this allows to close the communication with the current serial peri pheral by raising the correspo nding npcs line as soon as td transfer has completed. 31 30 29 28 27 26 25 24 ???????lastxfer 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 swrst?????spidisspien
440 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 32.7.2 spi mode register name: spi_mr addresses: 0xfffc8004 (0), 0xfffcc004 (1) access type: read/write ? mstr: master/slave mode 0 = spi is in slave mode. 1 = spi is in master mode. ? ps: peripheral select 0 = fixed peripheral select. 1 = variable peripheral select. ? pcsdec: chip select decode 0 = the chip selects are directly connected to a peripheral device. 1 = the four chip select lines are connected to a 4- to 16-bit decoder. when pcsdec equals one, up to 15 chip select signals can be generated with the four lines using an external 4- to 16-bit decoder. the chip select registers define the characteristics of the 15 chip selects according to the following rules: spi_csr0 defines peripheral chip select signals 0 to 3. spi_csr1 defines peripheral chip select signals 4 to 7. spi_csr2 defines peripheral chip select signals 8 to 11. spi_csr3 defines peripheral chip select signals 12 to 14. ? modfdis: mode fault detection 0 = mode fault detection is enabled. 1 = mode fault detection is disabled. ? llb: local loopback enable 0 = local loopback path disabled. 1 = local loopback path enabled llb controls the local loopback on the data serializer for te sting in master mode only. (miso is internally connected on mosi.) 31 30 29 28 27 26 25 24 dlybcs 23 22 21 20 19 18 17 16 ???? pcs 15 14 13 12 11 10 9 8 ???????? 76543210 llb ? 0 modfdis ? pcsdec ps mstr
441 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? pcs: peripheral chip select this field is only used if fixed peripheral select is active (ps = 0). if pcsdec = 0: pcs = xxx0 npcs[3:0] = 1110 pcs = xx01 npcs[3:0] = 1101 pcs = x011 npcs[3:0] = 1011 pcs = 0111 npcs[3:0] = 0111 pcs = 1111 forbidden (no peripheral is selected) (x = don?t care) if pcsdec = 1: npcs[3:0] output signals = pcs. ? dlybcs: delay between chip selects this field defines the delay from npcs inactive to the ac tivation of another npcs. the dlybcs time guarantees non-over- lapping chip selects and solves bus contentions in case of peripherals having long data float times. if dlybcs is less than or eq ual to six, six mck periods will be inserted by default. otherwise, the following equat ion determines the delay: delay between chip selects dlybcs mck ---------------------- - =
442 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 32.7.3 spi receive data register name: spi_rdr addresses: 0xfffc8008 (0), 0xfffcc008 (1) access type: read-only ? rd: receive data data received by the spi interface is stored in this register right-justified. unused bits read zero. ? pcs: peripheral chip select in master mode only, these bits indicate the value on the npcs pins at the end of a transfer. otherwise, these bits read zero. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???? pcs 15 14 13 12 11 10 9 8 rd 76543210 rd
443 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 32.7.4 spi transmit data register name: spi_tdr addresses: 0xfffc800c (0), 0xfffcc00c (1) access type: write-only ? td: transmit data data to be transmitted by the spi interface is stored in this register. information to be transmitted must be written to the transmit data register in a right-justified format. ? pcs: peripheral chip select this field is only used if variable peripheral select is active (ps = 1). if pcsdec = 0: pcs = xxx0 npcs[3:0] = 1110 pcs = xx01 npcs[3:0] = 1101 pcs = x011 npcs[3:0] = 1011 pcs = 0111 npcs[3:0] = 0111 pcs = 1111 forbidden (no peripheral is selected) (x = don?t care) if pcsdec = 1: npcs[3:0] output signals = pcs ? lastxfer: last transfer 0 = no effect. 1 = the current npcs will be deasserted afte r the character written in td has been transferred. when csaat is set, this allows to close the communication with the current serial peri pheral by raising the correspo nding npcs line as soon as td transfer has completed. this field is only used if variable peripheral select is active (ps = 1). 31 30 29 28 27 26 25 24 ???????lastxfer 23 22 21 20 19 18 17 16 ???? pcs 15 14 13 12 11 10 9 8 td 76543210 td
444 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 32.7.5 spi status register name: spi_sr addresses: 0xfffc8010 (0), 0xfffcc010 (1) access type: read-only ? rdrf: receive data register full 0 = no data has been received since the last read of spi_rdr 1 = data has been received and the received data has been transferred from the serializer to spi_rdr since the last read of spi_rdr. ? tdre: transmit data register empty 0 = data has been written to spi_tdr and not yet transferred to the serializer. 1 = the last data written in the transmit data register has been transferred to the serializer. tdre equals zero when the spi is disabled or at reset. the spi enable command sets this bit to one. ? modf: mode fault error 0 = no mode fault has been detected since the last read of spi_sr. 1 = a mode fault occurred since the last read of the spi_sr. ? ovres: overrun error status 0 = no overrun has been detected since the last read of spi_sr. 1 = an overrun has occurred since the last read of spi_sr. an overrun occurs when spi_r dr is loaded at least twice from the serializer since the last read of the spi_rdr. ? endrx: end of rx buffer 0 = the receive counter register has not reached 0 since the last write in spi_rcr (1) or spi_rncr (1) . 1 = the receive counter register has reached 0 since the last write in spi_rcr (1) or spi_rncr (1) . ? endtx: end of tx buffer 0 = the transmit counter register has not reached 0 since the last write in spi_tcr (1) or spi_tncr (1) . 1 = the transmit counter register has reached 0 since the last write in spi_tcr (1) or spi_tncr (1) . ? rxbuff: rx buffer full 0 = spi_rcr (1) or spi_rncr (1) has a value other than 0. 1 = both spi_rcr (1) and spi_rncr (1) have a value of 0. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????spiens 15 14 13 12 11 10 9 8 ?????0txemptynssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
445 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? txbufe: tx buffer empty 0 = spi_tcr (1) or spi_tncr (1) has a value other than 0. 1 = both spi_tcr (1) and spi_tncr (1) have a value of 0. ? nssr: nss rising 0 = no rising edge detected on nss pin since last read. 1 = a rising edge occurred on nss pin since last read. ? txempty: transmission registers empty 0 = as soon as data is written in spi_tdr. 1 = spi_tdr and internal shifter are empty. if a transfer delay has been defined, txempty is set after the completion of such delay. ? spiens: spi enable status 0 = spi is disabled. 1 = spi is enabled. note: 1. spi_rcr, spi_rncr, spi_tcr, spi_tncr are physically located in the pdc.
446 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 32.7.6 spi interrupt enable register name: spi_ier addresses: 0xfffc8014 (0), 0xfffcc014 (1) access type: write-only 0 = no effect. 1 = enables the corresponding interrupt. ? rdrf: receive data register full interrupt enable ? tdre: spi transmit data regi ster empty interrupt enable ? modf: mode fault error interrupt enable ? ovres: overrun error interrupt enable ? endrx: end of receive buffer interrupt enable ? endtx: end of transmit buffer interrupt enable ? rxbuff: receive buffer full interrupt enable ? txbufe: transmit buffer empty interrupt enable ? nssr: nss rising interrupt enable ? txempty: transmission registers empty enable 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????0txemptynssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
447 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 32.7.7 spi interrupt disable register name: spi_idr addresses: 0xfffc8018 (0), 0xfffcc018 (1) access type: write-only 0 = no effect. 1 = disables the corresponding interrupt. ? rdrf: receive data register full interrupt disable ? tdre: spi transmit data register empty interrupt disable ? modf: mode fault error interrupt disable ? ovres: overrun error interrupt disable ? endrx: end of receive buffer interrupt disable ? endtx: end of transmit buffer interrupt disable ? rxbuff: receive buffer full interrupt disable ? txbufe: transmit buffer empty interrupt disable ? nssr: nss rising interrupt disable ? txempty: transmission registers empty disable 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????0txemptynssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
448 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 32.7.8 spi interrupt mask register name: spi_imr addresses: 0xfffc801c (0), 0xfffcc01c (1) access type: read-only 0 = the corresponding interrupt is not enabled. 1 = the corresponding interrupt is enabled. ? rdrf: receive data register full interrupt mask ? tdre: spi transmit data register empty interrupt mask ? modf: mode fault error interrupt mask ? ovres: overrun error interrupt mask ? endrx: end of receive buffer interrupt mask ? endtx: end of transmit buffer interrupt mask ? rxbuff: receive buffer full interrupt mask ? txbufe: transmit buffer empty interrupt mask ? nssr: nss rising interrupt mask ? txempty: transmission registers empty mask 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????0txemptynssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
449 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 32.7.9 spi chip select register name: spi_csr0... spi_csr3 addresses: 0xfffc8030 (0), 0xfffcc030 (1) access type: read/write note: spi_csrx registers must be written even if the user wants to use the defaults. the bits field will not be updated with the trans- lated value unless the register is written. ? cpol: clock polarity 0 = the inactive state value of spck is logic level zero. 1 = the inactive state value of spck is logic level one. cpol is used to determine the inactive state value of the serial clock (spck). it is used with ncpha to produce the required clock/data relationship between master and slave devices. ? ncpha: clock phase 0 = data is changed on the leading edge of spck and captured on the following edge of spck. 1 = data is captured on the leading edge of spck and changed on the following edge of spck. ncpha determines which edge of spck causes data to change and which edge causes data to be captured. ncpha is used with cpol to produce the required clock/da ta relationship between master and slave devices. ? csaat: chip select active after transfer 0 = the peripheral chip select line rises as soon as the last transfer is achieved. 1 = the peripheral chip select does not rise after the last transfer is achieved. it remains active until a new transfer is requested on a different chip select. ? bits: bits per transfer (see the (note:) below the register table; section 32.7.9 ?spi chip select register? on page 449 .) the bits field determines the number of data bits transferred. reserved values should not be used. 31 30 29 28 27 26 25 24 dlybct 23 22 21 20 19 18 17 16 dlybs 15 14 13 12 11 10 9 8 scbr 76543210 bits csaat ? ncpha cpol bits bits per transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15
450 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? scbr: serial clock baud rate in master mode, the spi interface uses a modulus counter to derive the spck baud rate from the master clock mck. the baud rate is selected by writing a value from 1 to 255 in the scbr field. the following equations determine the spck baud rate: programming the scbr field at 0 is forbidden. triggering a trans fer while scbr is at 0 can le ad to unpredictable results. at reset, scbr is 0 and the user has to program it at a valid value before performing the first transfer. ? dlybs: delay before spck this field defines the delay from npcs valid to the first valid spck transition. when dlybs equals zero, the npcs valid to spck transition is 1/2 the spck clock period. otherwise, the following equations determine the delay: ? dlybct: delay between consecutive transfers this field defines the delay between two consecutive transfers with the same perip heral without removing the chip select. the delay is always inserted after each transfer and before removing the chip select if needed. when dlybct equals zero, no delay between consecutive transf ers is inserted and the clock keeps its duty cycle over the character transfers. otherwise, the following equat ion determines the delay: 1000 16 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved bits bits per transfer spck baudrate mck scbr -------------- - = delay before spck dlybs mck ------------------ - = delay between consecutive transfers 32 dlybct mck ------------------------------------- =
451 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 33. two-wire interface (twi) 33.1 description the atmel two-wire interface (twi) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 kbits per second, based on a byte-oriented transfer format. it can be used with any atmel two-wire interface bus serial eeprom and iec compatible device such as real time clock (rtc), dot matrix/graphic lcd controllers and temperature sensor, to name but a few. the twi is programmable as a master or a slave with sequential or single-byte access. mu ltiple master capability is supported. arbitra- tion of the bus is performed internally and puts the twi in slave mode automatically if the bus arbitration is lost. a configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies. below, table 33-1 lists the compatibility level of the atme l two-wire interface in master mode and a full i2c compatible device. note: 1. start + b000000001 + ack + sr 33.2 list of abbreviations table 33-1. atmel twi compatibilit y with i2c standard i2c standard atmel twi standard mode speed (100 khz) supported fast mode speed (400 khz) supported 7 or 10 bits slave addressing supported start byte (1) not supported repeated start (sr) condition supported ack and nack management supported slope control and input filtering (fast mode) not supported clock stretching supported table 33-2. abbreviations abbreviation description twi two-wire interface a acknowledge na non acknowledge pstop sstart sr repeated start sadr slave address
452 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 33.3 block diagram figure 33-1. block diagram 33.4 application block diagram figure 33-2. application block diagram adr any address except sadr rread wwrite table 33-2. abbreviations abbreviation description apb bridge pmc mck two-wire interface pio aic twi interrupt twck twd host with twi interface twd twck atmel twi serial eeprom i2c rtc i2c lcd controller slave 1 slave 2 slave 3 vdd i2c temp. sensor slave 4 rp: pull up value as given by the i2c standard rp rp
453 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 33.4.1 i/o lines description 33.5 product dependencies 33.5.1 i/o lines both twd and twck are bidirectional lines, connect ed to a positive supply voltage via a current source or pull-up resistor (see figure 33-2 on page 452 ). when the bus is free, both lines are high. the output stages of devices connected to the bus must have an open-drain or open-col- lector to perform the wired-and function. twd and twck pins may be multiplexed with pi o lines. to enable the twi, the programmer must perform the following step: ? program the pio controller to dedicate twd and twck as peripheral lines. the user must not program twd and twck as open-drain. it is already done by the hardware. 33.5.2 power management ? enable the peripheral clock. the twi interface may be clocked through the power management controller (pmc), thus the programmer must first configure the pmc to enable the twi clock. 33.5.3 interrupt the twi interface has an interrupt line connected to the advanced interrupt controller (aic). in order to handle interrupts, the aic must be programmed before configuring the twi. 33.6 functional description 33.6.1 transfer format the data put on the twd line must be 8 bits long. data is transferred msb first; each byte must be followed by an acknowledgement. the number of bytes per transfer is unlimited (see figure 33-4 ). each transfer begins with a start condition and terminates with a stop condition (see figure 33-3 ). ? a high-to-low transition on the twd line while twck is high defines the start condition. ? a low-to-high transition on the twd line while twck is high defines a stop condition. table 33-3. i/o lines description pin name pin description type twd two-wire serial data input/output twck two-wire serial clock input/output
454 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 33-3. start and stop conditions figure 33-4. transfer format 33.6.2 modes of operation the twi has six modes of operations: ? master transmitter mode ? master receiver mode ? multi-master transmitter mode ? multi-master receiver mode ? slave transmitter mode ? slave receiver mode these modes are described in the following chapters. twd twck start stop twd twck start address r/w ack data ack data ack stop
455 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 33.7 master mode 33.7.1 definition the master is the device that starts a transfer, generates a clock and stops it. 33.7.2 application block diagram figure 33-5. master mode typical application block diagram 33.7.3 programming master mode the following registers have to be programmed before entering master mode: 1. dadr (+ iadrsz + iadr if a 10 bit device is addressed): the device address is used to access slave devices in read or write mode. 2. ckdiv + chdiv + cldiv: clock waveform. 3. svdis: disable the slave mode. 4. msen: enable the master mode. 33.7.4 master transmitter mode after the master initiates a start condition when writing into the tran smit holding register, twi_thr, it sends a 7-bit slave address, configured in the master mode register (dadr in twi_mmr), to notify the slave device. the bit following the slave address indicates the transfer direction, 0 in this case (mread = 0 in twi_mmr). the twi transfers require the slave to acknowledge each received byte. during the acknowl- edge clock pulse (9th pulse), the master releases the data line (high), enabling the slave to pull it down in order to generate the acknowledge. t he master polls the data line during this clock pulse and sets the not acknowledge bit ( nack) in the status register if the slave does not acknowledge the byte. as with the other status bits, an interrupt can be generated if enabled in the interrupt enable register (twi_ier). if the slave acknowledges the byte, the data written in the twi_thr, is then shifted in the internal shifter and transferred. when an acknowledge is detected, the txrdy bit is set until a new write in the twi_thr. host with twi interface twd twck atmel twi serial eeprom i2c rtc i2c lcd controller slave 1 slave 2 slave 3 vdd i2c temp. sensor slave 4 rp: pull up value as given by the i2c standard rp rp
456 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary while no new data is writ ten in the twi_thr, the serial clock line is tied low. when new data is written in the twi_thr, the scl is released and the data is sent. to generate a stop event, the stop command must be performed by writing in the stop field of twi_cr. after a master write transfer, the serial clock line is stretched (tied low) while no new data is written in the twi_thr or until a stop command is performed. see figure 33-6 , figure 33-7 , and figure 33-8 . figure 33-6. master write with one data byte figure 33-7. master write with mu ltiple data bytes txcomp txrdy write thr (data) stop command sent (write in twi_cr) twd a data a s dadr w p a data n a s dadr w data n+1 a p data n+2 a txcomp txrdy write thr (data n) write thr (data n+1) write thr (data n+2) last data sent stop command performed (by writing in the twi_cr) twd twck
457 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 33-8. master write with one byte internal address and multiple data bytes txrdy is used as transmit read y for the pdc transmit channel. 33.7.5 master receiver mode the read sequence begins by setting the start bit. after the start condition has been sent, the master sends a 7-bit slave address to notify th e slave device. the bit following the slave address indicates the transfer direction, 1 in this ca se (mread = 1 in twi_mmr). during the acknowl- edge clock pulse (9th pulse), the master releases the data line (high), enabling the slave to pull it down in order to generate the acknowledge. t he master polls the data line during this clock pulse and sets the nack bit in the status register if the slave does not acknowledge the byte. if an acknowledge is received, the master is then ready to receive data from the slave. after data has been received, the master sends an acknowle dge condition to notify the slave that the data has been received except for the last data, after the stop condition. see figure 33-9 . when the rxrdy bit is set in the status register, a character has been received in the receive-holding reg- ister (twi_rhr). the rxrdy bit is reset when reading the twi_rhr. when a single data byte read is performed, with or without internal address (iadr ), the start and stop bits must be set at the same time. see figure 33-9 . when a multiple data byte read is performed, with or without internal address (iadr ), the stop bit must be set after the next-to- last data received. see figure 33-10 . for internal address usage see section 33.7.6 . figure 33-9. master read with one data byte a data n a s dadr w data n+1 a p data n+2 a txcomp txrdy write thr (data n) write thr (data n+1) write thr (data n+2) last data sent stop command performed (by writing in the twi_cr) twd iadr a twck a s dadr r data n p txcomp write start & stop bit rxrdy read rhr twd
458 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 33-10. master read with mu ltiple data bytes rxrdy is used as receive ready for the pdc receive channel. 33.7.6 internal address the twi interface can perform various transfe r formats: transfers with 7-bit slave address devices and 10-bit slave address devices. 33.7.6.1 7-bit slave addressing when addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, within a memory page loca- tion in a serial memory, for example. when performing read operations with an internal address, the twi performs a write operation to set the internal address into the slave device, and then switch to master receiver mode. note that the second start condition (after sending the iadr) is sometimes called ??repeated start?? (sr) in i2c fully-compatible devices. see figure 33-12 . see figure 33-11 and figure 33-13 for master write operation with internal address. the three internal address bytes are configurable through the master mode register (twi_mmr). if the slave device supports only a 7-bit address, i.e. no internal address, iadrsz must be set to 0. in the figures below the following abbreviations are used: n a s dadr r data n a a data (n+1) a data (n+m) data (n+m)-1 p twd txcomp write start bit rxrdy write stop bit after next-to-last data read read rhr data n read rhr data (n+1) read rhr data (n+m)-1 read rhr data (n+m) ?s start ?sr repeated start ?p stop ?w write ?r read ?a acknowledge ?n not acknowledge ?dadr device address ?iadr internal address
459 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 33-11. master write with one, two or three bytes internal address and one data byte figure 33-12. master read with one, two or three bytes internal address and one data byte 33.7.6.2 10-bit slave addressing for a slave address higher than 7 bits, the user must configure the address size (iadrsz ) and set the other slave address bits in the internal address register (twi_iadr). the two remaining internal address bytes, iadr[15:8] and iadr[23:16] can be used the same as in 7-bit slave addressing. example: address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10) 1. program iadrsz = 1, 2. program dadr with 1 1 1 1 0 b1 b2 (b1 is the msb of the 10-bit address, b2, etc.) 3. program twi_iadr with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the lsb of the 10-bit address) figure 33-13 below shows a byte write to an atmel at24lc512 eeprom. this demonstrates the use of internal addresses to access the device. figure 33-13. internal address usage s dadr w a iadr(23:16) a iadr(15:8) a iadr(7:0) a data a p s dadr w a iadr(15:8) a iadr(7:0) a p data a a iadr(7:0) a p data a s dadr w twd three bytes internal address two bytes internal address one byte internal address twd twd s dadr w a iadr(23:16) a iadr(15:8) a iadr(7:0) a s dadr w a iadr(15:8) a iadr(7:0) a a iadr(7:0) a s dadr w data n p sr dadr r a sr dadr r a data n p sr dadr ra data np twd twd twd three bytes internal address two bytes internal address one byte internal address s t a r t m s b device address 0 l s b r / w a c k m s b w r i t e a c k a c k l s b a c k first word address second word address data s t o p
460 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 33.7.7 using the peripheral dma controller (pdc) the use of the pdc significantly reduces the cpu load. to assure correct implementation, respect the following programming sequences: 33.7.7.1 data transmit with the pdc 1. initialize the transmit pdc (me mory pointers, size, etc.). 2. configure the master mode (dadr, ckdiv, etc.). 3. start the transfer by setting the pdc txten bit. 4. wait for the pdc end tx flag. 5. disable the pdc by setting the pdc txdis bit. 33.7.7.2 data receive with the pdc 1. initialize the receive pdc (memory pointers, size - 1, etc.). 2. configure the master mode (dadr, ckdiv, etc.). 3. start the transfer by setting the pdc rxten bit. 4. wait for the pdc end rx flag. 5. disable the pdc by setting the pdc rxdis bit. 33.7.8 smbus quick command (master mode only) the twi interface can perform a quick command: 1. configure the master mode (dadr, ckdiv, etc.). 2. write the mread bit in the twi_mmr register at the value of the one-bit command to be sent. 3. start the transfer by setting the quick bit in the twi_cr. figure 33-14. smbus quick command 33.7.9 read-write flowcharts the following flowcharts shown in figure 33-16 on page 462 , figure 33-17 on page 463 , figure 33-18 on page 464 , figure 33-19 on page 465 and figure 33-20 on page 466 give examples for read and write operations. a polling or interrupt method can be used to check the status bits. the interrupt method requires that the interrupt enable register (twi_ier) be configured first. txcomp txrdy write quick command in twi_cr twd a s dadr r/w p
461 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 33-15. twi write operation with single data byte without internal address set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address (dadr) - transfer direction bit write ==> bit mread = 0 load transmit register twi_thr = data to send read status register txrdy = 1? read status register txcomp = 1? transfer finished ye s ye s begin no no write stop command twi_cr = stop
462 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 33-16. twi write operation with single data byte and internal address begin set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address (dadr) - internal address size (iadrsz) - transfer direction bit write ==> bit mread = 0 load transmit register twi_thr = data to send read status register txrdy = 1? read status register txcomp = 1? transfer finished set the internal address twi_iadr = address yes yes no no write stop command twi_cr = stop
463 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 33-17. twi write operation with multiple data bytes with or without internal address set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address - internal address size (if iadr used) - transfer direction bit write ==> bit mread = 0 internal address size = 0? load transmit register twi_thr = data to send read status register txrdy = 1? data to send? read status register txcomp = 1? end begin set the internal address twi_iadr = address ye s twi_thr = data to send ye s ye s ye s no no no write stop command twi_cr = stop set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once)
464 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 33-18. twi read operation with single data byte without internal address set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address - transfer direction bit read ==> bit mread = 1 start the transfer twi_cr = start | stop read status register rxrdy = 1? read status register txcomp = 1? end begin ye s ye s set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) read receive holding register no no
465 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 33-19. twi read operation with single data byte and internal address set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address - internal address size (iadrsz) - transfer direction bit read ==> bit mread = 1 read status register txcomp = 1? end begin ye s set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) ye s set the internal address twi_iadr = address start the transfer twi_cr = start | stop read status register rxrdy = 1? read receive holding register no no
466 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 33-20. twi read operation with multiple data bytes with or without internal address internal address size = 0? start the transfer twi_cr = start stop the transfer twi_cr = stop read status register rxrdy = 1? last data to read but one? read status register txcomp = 1? end set the internal address twi_iadr = address ye s ye s ye s no ye s read receive holding register (twi_rhr) no set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address - internal address size (if iadr used) - transfer direction bit read ==> bit mread = 1 begin set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) no read status register rxrdy = 1? ye s read receive holding register (twi_rhr) no
467 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 33.8 multi-master mode 33.8.1 definition more than one master may handle the bus at the same time without data corruption by using arbitration. arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. as soon as arbitration is lost by a master, it st ops sending data and listens to the bus in order to detect a stop. when the stop is detected, the master who has lost arbitration may put its data on the bus by respecting arbitration. arbitration is illustrated in figure 33-22 on page 468 . 33.8.2 different multi-master modes two multi-master modes may be distinguished: 1. twi is considered as a master only and will never be addressed. 2. twi may be either a master or a slave and may be addressed. note: in both multi-master modes arbitration is supported. 33.8.2.1 twi as master only in this mode, twi is considered as a master only (msen is always at one) and must be driven like a master with the arblst (arbitration lost) flag in addition. if arbitration is lost (arblst = 1), the programmer must reinitiate the data transfer. if the user starts a transfer (ex.: dadr + start + w + write in thr) and if the bus is busy, the twi automatically waits for a stop conditi on on the bus to initiate the transfer (see figure 33- 21 on page 468 ). note: the state of the bus (busy or free) is not indicated in the user interface. 33.8.2.2 twi as master or slave the automatic reversal from master to slave is not supported in case of a lost arbitration. then, in the case where twi may be either a master or a slave, the programmer must manage the pseudo multi-master mode described in the steps below. 1. program twi in slave mode (sadr + ms dis + sven) and perform slave access (if twi is addressed). 2. if twi has to be set in master mode, wait until txcomp flag is at 1. 3. program master mode (dadr + svdis + msen ) and start the transfer (ex: start + write in thr). 4. as soon as the master mode is enabled, twi scans the bus in order to detect if it is busy or free. when the bus is considered as free, twi initiates the transfer. 5. as soon as the transfer is initiated and until a stop condition is sent, the arbitration becomes relevant and the user must monitor the arblst flag. 6. if the arbitration is lost (arblst is set to 1), the user must program the twi in slave mode in the case where the master that won the arbitration wanted to access the twi. 7. if twi has to be set in slave mode, wait until txcomp flag is at 1 and then program the slave mode.
468 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary note: in the case where the arbitration is lost and tw i is addressed, twi will not acknowledge even if it is programmed in slave mode as soon as arblst is set to 1. then, the master must repeat sadr. figure 33-21. programmer sends data while the bus is busy figure 33-22. arbitration cases the flowchart shown in figure 33-23 on page 469 gives an example of read and write operations in multi-master mode. twck twd data sent by a master stop sent by the master start sent by the twi data sent by the twi bus is busy bus is free a transfer is programmed (dadr + w + start + write thr) transfer is initiated twi data transfer transfer is kept bus is considered as free twck bus is busy bus is free a transfer is programmed (dadr + w + start + write thr) transfer is initiated twi data transfer transfer is kept bus is considered as free data from a master data from twi s 0 s 0 0 1 1 1 arblst s 0 s 0 0 1 1 1 twd s 0 0 1 1 1 1 1 arbitration is lost twi stops sending data p s 0 1 p 0 1 1 1 1 data from the master data from the twi arbitration is lost the master stops sending data transfer is stopped transfer is programmed again (dadr + w + start + write thr) twck twd
469 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 33-23. multi-master flowchart programm the slave mode: sadr + msdis + sven svacc = 1 ? txcomp = 1 ? gacc = 1 ? decoding of the programming sequence prog seq ok ? change sadr svread = 0 ? read status register rxrdy= 0 ? read twi_rhr txrdy= 1 ? eosacc = 1 ? write in twi_thr need to perform a master access ? program the master mode dadr + svdis + msen + clk + r / w read status register arblst = 1 ? mread = 1 ? txrdy= 0 ? write in twi_thr data to send ? rxrdy= 0 ? read twi_rhr data to read? read status register txcomp = 0 ? general call treatment ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s stop transfer twi_cr = stop no no no no no no no no no no no no no no no no start
470 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 33.9 slave mode 33.9.1 definition the slave mode is defined as a mode where the device receives the clock and the address from another device called the master. in this mode, the device never initiates and never completes the transmission (start, repeated_start and stop conditions are always provided by the master). 33.9.2 application block diagram figure 33-24. slave mode typical application block diagram 33.9.3 programming slave mode the following fields must be programmed before entering slave mode: 1. sadr (twi_smr): the slave device address is used in order to be accessed by mas- ter devices in read or write mode. 2. msdis (twi_cr): disable the master mode. 3. sven (twi_cr): enable the slave mode. as the device receives the clock, values written in twi_cwgr are not taken into account. 33.9.4 receiving data after a start or repeated start condition is detected and if the address sent by the master matches with the slave addre ss programmed in the sadr (slave address) field, svacc (slave access) flag is set and svread (slave read) indicates the direction of the transfer. svacc remains high until a stop condition or a repeated start is detected. when such a condition is detected, eosacc (end of slave access) flag is set. 33.9.4.1 read sequence in the case of a read sequence (svread is high), twi transfers data written in the twi_thr (twi transmit holding register) until a stop condition or a repeated _start + an address different from sadr is detected. note that at the end of the read sequence txcomp (transmis- sion complete) flag is set and svacc reset. as soon as data is written in the twi_t hr, txrdy (transmit holding register ready) flag is reset, and it is set when the shift register is empty and the sent data acknowledged or not. if the data is not acknowledged, the nack flag is set. host with twi interface twd twck lcd controller slave 1 slave 2 slave 3 rr vdd host with twi interface host with twi interface master
471 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary note that a stop or a repeated start always follows a nack. see figure 33-25 on page 472 . 33.9.4.2 write sequence in the case of a write sequence (svread is low), the rxrdy (receive holding register ready) flag is set as soon as a character has been received in the twi_rhr (twi receive holding register). rxrdy is re set when reading the twi_rhr. twi continues receiving data until a stop co ndition or a repeated_start + an address dif- ferent from sadr is detected. note that at the end of the write sequence txcomp flag is set and svacc reset. see figure 33-26 on page 472 . 33.9.4.3 clock synchronization sequence in the case where twi_thr or twi_rhr is not written/read in time, twi performs a clock synchronization. clock stretching information is given by the sclws (clock wait state) bit. see figure 33-28 on page 474 and figure 33-29 on page 475 . 33.9.4.4 general call in the case where a general call is perfor med, gacc (general call access) flag is set. after gacc is set, it is up to the programmer to interpret the meaning of the general call and to decode the new address programming sequence. see figure 33-27 on page 473 . 33.9.4.5 pdc as it is impossible to know the exact number of data to receive/send, the use of pdc is not rec- ommended in slave mode. 33.9.5 data transfer 33.9.5.1 read operation the read mode is defined as a data requirement from the master. after a start or a repeated start condition is detected, the decoding of the address starts. if the slave address (sadr) is decoded, svacc is set and svread indicates the direc- tion of the transfer. until a stop or repeated start condition is detected, twi continues sending data loaded in the twi_thr register. if a stop condition or a repeated start + an address different from sadr is detected, svacc is reset. figure 33-25 on page 472 describes the write operation.
472 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 33-25. read access ordered by a master notes: 1. when svacc is low, the state of svread becomes irrelevant. 2. txrdy is reset when data has been transmitted from twi_thr to the shift register and set when this data has been acknowledged or non acknowledged. 33.9.5.2 write operation the write mode is defined as a data transmission from the master. after a start or a repeated start, the decodi ng of the address starts . if the slave address is decoded, svacc is set and svread indicates the direction of the transfer (svread is low in this case). until a stop or repeated start condition is detected, twi stores the received data in the twi_rhr register. if a stop condition or a repeated start + an address different from sadr is detected, svacc is reset. figure 33-26 on page 472 describes the write operation. figure 33-26. write access ordered by a master notes: 1. when svacc is low, the state of svread becomes irrelevant. 2. rxrdy is set when data has been transmitted from the shift register to the twi_rhr and reset when this data is read. write thr read rhr svread has to be taken into account only while svacc is active twd txrdy nack svacc svread eosvacc sadr s adr r na r a data a a data na s/sr data na p/s/sr sadr matches, twi answers with an ack sadr does not match, twi answers with a nack ack/nack from the master rxrdy read rhr svread has to be taken into account only while svacc is active twd svacc svread eosvacc sadr does not match, twi answers with a nack sadr s adr w na w a data a a data na s/sr data na p/s/sr sadr matches, twi answers with an ack
473 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 33.9.5.3 general call the general call is performed in order to change the address of the slave. if a general call is detected, gacc is set. after the detection of general call, it is up to the programmer to decode the commands which come afterwards. in case of a write command, the programmer has to decode the programming sequence and program a new sadr if the programming sequence matches. figure 33-27 on page 473 describes the general call access. figure 33-27. master performs a general call note: this method allows the user to create an own programming sequence by choosing the program- ming bytes and the number of them. the programming sequence has to be provided to the master. 0000000 + w general call p s a general call reset or write dadd a new sadr data 1 a data 2 a a new sadr programming sequence txd gcacc svacc reset command = 00000110x write command = 00000100x reset after read
474 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 33.9.5.4 clock synchronization in both read and write modes, it may happen that twi_thr/tw i_rhr buffer is not filled /emp- tied before the emission/reception of a new charac ter. in this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. 33.9.5.5 clock synchron ization in read mode the clock is tied low if the shif t register is empty and if a stop or repeated start condition was not detected. it is tied low until the shift register is loaded. figure 33-28 on page 474 describes the clock synchronization in read mode. figure 33-28. clock synchronization in read mode notes: 1. txrdy is reset when data has been written in the twi_ thr to the shift register and set when this data has been acknowl- edged or non acknowledged. 2. at the end of the read sequence, txcomp is set after a stop or after a repeated_start + an address different from sadr. 3. sclws is automatically set when the cl ock synchronization mechanism is started. data 1 the clock is stretched after the ack, the state of twd is undefined during clock stretching sclws svacc svread txrdy twck twi_thr txcomp the data is memorized in twi_thr until a new value is written twi_thr is transmitted to the shift register ack or nack from the master data 0 data 0 data 2 1 2 1 clock is tied low by the twi as long as thr is empty s sadr s r data 0 a a data 1 a data 2 na s xxxxxxx 2 write thr as soon as a start is detected
475 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 33.9.5.6 clock synchronization in write mode the clock is tied low if the shift regi ster and the twi_rhr is full. if a stop or repeated_start condition was not detected , it is tied low until twi_rhr is read. figure 33-29 on page 475 describes the clock synchronization in read mode. figure 33-29. clock synchronization in write mode notes: 1. at the end of the read sequence, txcomp is set after a stop or after a repeated_start + an address different from sadr. 2. sclws is automatically set when the cl ock synchronization mechanism is started and automatically reset when the mecha- nism is finished. rd data0 rd data1 rd data2 svacc svread rxrdy sclws txcomp data 1 data 2 scl is stretched on the last bit of data1 as soon as a start is detected twck twd twi_rhr clock is tied low by the twi as long as rhr is full data0 is not read in the rhr adr s sadr w a data 0 a a data 2 data 1 s na
476 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 33.9.5.7 reversal after a repeated start 33.9.5.8 reversal of read to write the master initiates the communication by a read command and finishes it by a write command. figure 33-30 on page 476 describes the repeated start + reversal from read to write mode. figure 33-30. repeated start + reversal from read to write mode 1. txcomp is only set at the end of the transmission because after the repeated start, sadr is detected again. 33.9.5.9 reversal of write to read the master initiates the communication by a write command and finishes it by a read com- mand. figure 33-31 on page 476 describes the repeated start + reversal from write to read mode. figure 33-31. repeated start + reversal from write to read mode notes: 1. in this case, if twi_thr has not bee n written at the end of the read command, the clock is automatically stretched befo re the ack. 2. txcomp is only set at the end of the transmission because after the repeated st art, sadr is detected again. s sadr r a data 0 a data 1 sadr sr na w a data 2 a data 3 a p cleared after read data 0 data 1 data 2 data 3 svacc svread twd twi_thr twi_rhr eosacc txrdy rxrdy txcomp as soon as a start is detected s sadr w a data 0 a data 1 sadr sr a r a data 2 a data 3 n a p cleared after read data 0 data 2 data 3 data 1 txcomp txrdy rxrdy as soon as a start is detected read twi_rhr svacc svread twd twi_rhr twi_thr eosacc
477 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 33.9.6 read write flowcharts the flowchart shown in figure 33-32 on page 477 gives an example of read and write operations in slave mode. a polling or interr upt method can be used to check the status bits. the interrupt method requires that the interrupt enable register (twi_ier) be configured first. figure 33-32. read write flowchart in slave mode set the slave mode: sadr + msdis + sven svacc = 1 ? txcomp = 1 ? gacc = 1 ? decoding of the programming sequence prog seq ok ? change sadr svread = 0 ? read status register rxrdy= 0 ? read twi_rhr txrdy= 1 ? eosacc = 1 ? write in twi_thr end general call treatment no no no no no no no no
478 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 33.10 two-wire interface (twi) user interface table 33-4. register mapping offset register name access reset 0x00 control register twi_cr write-only n / a 0x04 master mode register twi_mmr read-write 0x00000000 0x08 slave mode register twi_smr read-write 0x00000000 0x0c internal address register twi_iadr read-write 0x00000000 0x10 clock waveform generator register twi_cwgr read-write 0x00000000 0x20 status register twi_sr read-only 0x0000f009 0x24 interrupt enable register twi_ier write-only n / a 0x28 interrupt disable register twi_idr write-only n / a 0x2c interrupt mask register twi_imr read-only 0x00000000 0x30 receive holding register twi_rhr read-only 0x00000000 0x34 transmit holding register twi_thr write-only 0x00000000 0x38 - 0xfc reserved ? ? ? 0x100 - 0x124 reserved for the pdc ? ? ?
479 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 33.10.1 twi control register name: twi_cr addresses: 0xfffac000 (0), 0xfffd8000 (1) access: write-only reset value: 0x00000000 ? start: send a start condition 0 = no effect. 1 = a frame beginning with a start bit is transmitted according to the features defined in the mode register. this action is necessary when the twi peripheral wants to read data from a slave. when configured in master mode with a write operation, a frame is sent as soon as the user writes a character in the transmit holding register (twi_thr). ? stop: send a stop condition 0 = no effect. 1 = stop condition is sent just after completing the current byte transmission in master read mode. ? in single data byte master read, the start and stop must both be set. ? in multiple data bytes master read, the stop must be set after the last data received but one. ? in master read mode, if a nack bit is received, the stop is automatically performed. ? in master data write operation, a st op condition will be sent after the tr ansmission of the current data is finished. ? msen: twi master mode enabled 0 = no effect. 1 = if msdis = 0, the master mode is enabled. note: switching from slave to master mo de is only permitted when txcomp = 1. ? msdis: twi master mode disabled 0 = no effect. 1 = the master mode is disabled, all pending data is transmitted. the shifter and holding characters (if it contains data) are transmitted in case of write operation. in read operation, the character being transferred must be completely received before disabling. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 swrst quick svdis sven msdis msen stop start
480 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? sven: twi slave mode enabled 0 = no effect. 1 = if svdis = 0, the slave mode is enabled. note: switching from master to slave mode is only permitted when txcomp = 1. ? svdis: twi slave mode disabled 0 = no effect. 1 = the slave mode is disabled. the shifter and holding characte rs (if it contains data) are transmitted in case of read oper- ation. in write operation, the character being transferred must be completely received before disabling. ? quick: smbus quick command 0 = no effect. 1 = if master mode is enabled, a smbus quick command is sent. ? swrst: software reset 0 = no effect. 1 = equivalent to a system reset.
481 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 33.10.2 twi master mode register name: twi_mmr addresses: 0xfffac004 (0), 0xfffd8004 (1) access: read-write reset value: 0x00000000 ? iadrsz: internal device address size ? mread: master read direction 0 = master write direction. 1 = master read direction. ? dadr: device address the device address is used to access slave devices in read or write mode. those bits are only used in master mode. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?dadr 15 14 13 12 11 10 9 8 ???mread?? iadrsz 76543210 ???????? iadrsz[9:8] 0 0 no internal device address 0 1 one-byte internal device address 1 0 two-byte internal device address 1 1 three-byte internal device address
482 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 33.10.3 twi slave mode register name: twi_smr addresses: 0xfffac008 (0), 0xfffd8008 (1) access: read-write reset value: 0x00000000 ? sadr: slave address the slave device address is used in slav e mode in order to be accessed by master devices in read or write mode. sadr must be programmed before enabling the slave mode or after a general call. writes at other times have no effect. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?sadr 15 14 13 12 11 10 9 8 ?????? 76543210 ????????
483 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 33.10.4 twi internal address register name: twi_iadr addresses: 0xfffac00c (0), 0xfffd800c (1) access: read-write reset value: 0x00000000 ? iadr: internal address 0, 1, 2 or 3 bytes depending on iadrsz. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 iadr 15 14 13 12 11 10 9 8 iadr 76543210 iadr
484 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 33.10.5 twi clock waveform generator register name: twi_cwgr addresses: 0xfffac010 (0), 0xfffd8010 (1) access: read-write reset value: 0x00000000 twi_cwgr is only used in master mode. ? cldiv: clock low divider the scl low period is defined as follows: ? chdiv: clock high divider the scl high period is defined as follows: ? ckdiv: clock divider the ckdiv is used to increase both scl high and low periods. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ckdiv 15 14 13 12 11 10 9 8 chdiv 76543210 cldiv t low cldiv ( 2 ckdiv () 4 ) + t mck = t high chdiv ( 2 ckdiv () 4 ) + t mck =
485 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 33.10.6 twi status register name: twi_sr addresses: 0xfffac020 (0), 0xfffd8020 (1) access: read-only reset value: 0x0000f009 ? txcomp: transmission completed (automatically set / reset) txcomp used in master mode : 0 = during the length of the current frame. 1 = when both holding and shifter registers are empty and stop condition has been sent. txcomp behavior in master mode can be seen in figure 33-8 on page 457 and in figure 33-10 on page 458 . txcomp used in slave mode : 0 = as soon as a start is detected. 1 = after a stop or a repeated start + an address different from sadr is detected. txcomp behavior in slave mode can be seen in figure 33-28 on page 474 , figure 33-29 on page 475 , figure 33-30 on page 476 and figure 33-31 on page 476 . ? rxrdy: receive holding register ready (automatically set / reset) 0 = no character has been received since the last twi_rhr read operation. 1 = a byte has been received in the twi_rhr since the last read. rxrdy behavior in master mode can be seen in figure 33-10 on page 458 . rxrdy behavior in slave mode can be seen in figure 33-26 on page 472 , figure 33-29 on page 475 , figure 33-30 on page 476 and figure 33-31 on page 476 . ? txrdy: transmit holding register ready (automatically set / reset) txrdy used in master mode : 0 = the transmit holding register has not been transferred into shift register. set to 0 when writing into twi_thr register. 1 = as soon as a data byte is transferred from twi_thr to inte rnal shifter or if a nack erro r is detected, txrdy is set at the same time as txcomp and nack. txrdy is also set when msen is set (enable twi). txrdy behavior in master mode can be seen in figure 33-8 on page 457 . 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 txbufe rxbuff endtx endrx eosacc sclws arblst nack 76543210 ? ovre gacc svacc svread txrdy rxrdy txcomp
486 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary txrdy used in slave mode : 0 = as soon as data is written in the twi_thr, until this data has been transmitted and acknowledged (ack or nack). 1 = it indicates that the twi_thr is empty and that data has been transmitted and acknowledged. if txrdy is high and if a nack has been detected, the tr ansmission will be stopped. thus when trdy = nack = 1, the programmer must not fill tw i_thr to avoid losing it. txrdy behavior in slave mode can be seen in figure 33-25 on page 472 , figure 33-28 on page 474 , figure 33-30 on page 476 and figure 33-31 on page 476 . ? svread: slave read (automatically set / reset) this bit is only used in slave mode. when svacc is low (no slave access has been detected) svread is irrelevant. 0 = indicates that a write access is performed by a master. 1 = indicates that a read access is performed by a master. svread behavior can be seen in figure 33-25 on page 472 , figure 33-26 on page 472 , figure 33-30 on page 476 and figure 33-31 on page 476 . ? svacc: slave access (automatically set / reset) this bit is only used in slave mode. 0 = twi is not addressed. svacc is automatically cleared af ter a nack or a stop condition is detected. 1 = indicates that the address decoding sequence has matched (a master has sent sadr). svacc remains high until a nack or a stop condition is detected. svacc behavior can be seen in figure 33-25 on page 472 , figure 33-26 on page 472 , figure 33-30 on page 476 and fig- ure 33-31 on page 476 . ? gacc: general call access (clear on read) this bit is only used in slave mode. 0 = no general call has been detected. 1 = a general call has been detected. after the detection of general call, if need be, the programmer may acknowledge this access and decode the following bytes and respond according to the value of the bytes. gacc behavior can be seen in figure 33-27 on page 473 . ? ovre: overrun error (clear on read) this bit is only used in master mode. 0 = twi_rhr has not been loaded while rxrdy was set 1 = twi_rhr has been loaded while rxrdy was set. reset by read in twi_sr when txcomp is set. ? nack: not acknowledged (clear on read) nack used in master mode : 0 = each data byte has been correctly received by the far-end side twi slave component. 1 = a data byte has not been acknowledged by the sl ave component. set at the same time as txcomp.
487 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary nack used in slave read mode : 0 = each data byte has been correctly received by the master. 1 = in read mode, a data byte has not been acknowledged by the master. when nack is set the programmer must not fill twi_thr even if txrdy is set, because it means that the master will stop the data transfer or re initiate it. note that in slave write mode all data are acknowledged by the twi. ? arblst: arbitration lost (clear on read) this bit is only used in master mode. 0: arbitration won. 1: arbitration lost. another master of the twi bus has won the multi-master arbitration. txcomp is set at the same time. ? sclws: clock wait state (automatically set / reset) this bit is only used in slave mode. 0 = the clock is not stretched. 1 = the clock is stretched. twi_thr / tw i_rhr buffer is not filled / emptied bef ore the emission / reception of a new character. sclws behavior can be seen in figure 33-28 on page 474 and figure 33-29 on page 475 . ? eosacc: end of slave access (clear on read) this bit is only used in slave mode. 0 = a slave access is being performing. 1 = the slave access is finished. end of slave access is automatically set as soon as svacc is reset. eosacc behavior can be seen in figure 33-30 on page 476 and figure 33-31 on page 476 ? endrx: end of rx buffer this bit is only used in master mode. 0 = the receive counter register has not reached 0 since the last write in twi_rcr or twi_rncr. 1 = the receive counter register has reached 0 since the last write in twi_rcr or twi_rncr. ? endtx: end of tx buffer this bit is only used in master mode. 0 = the transmit counter register has not reached 0 since the last write in twi_tcr or twi_tncr. 1 = the transmit counter register has reached 0 since the last write in twi_tcr or twi_tncr. ? rxbuff: rx buffer full this bit is only used in master mode. 0 = twi_rcr or twi_rncr have a value other than 0. 1 = both twi_rcr and twi_rncr have a value of 0.
488 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? txbufe: tx buffer empty this bit is only used in master mode. 0 = twi_tcr or twi_tncr have a value other than 0. 1 = both twi_tcr and twi_tncr have a value of 0.
489 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 33.10.7 twi interrupt enable register name: twi_ier addresses: 0xfffac024 (0), 0xfffd8024 (1) access: write-only reset value: 0x00000000 ? txcomp: transmission completed interrupt enable ? rxrdy: receive holding register ready interrupt enable ? txrdy: transmit holding register ready interrupt enable ? svacc: slave access interrupt enable ? gacc: general call access interrupt enable ? ovre: overrun error interrupt enable ? nack: not acknowledge interrupt enable ? arblst: arbitration lost interrupt enable ? scl_ws: clock wait state interrupt enable ? eosacc: end of slave access interrupt enable ? endrx: end of receive buffer interrupt enable ? endtx: end of transmit buffer interrupt enable ? rxbuff: receive buffer full interrupt enable ? txbufe: transmit buffer empty interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 txbufe rxbuff endtx endrx eosacc scl_ws arblst nack 76543210 ? ovre gacc svacc ? txrdy rxrdy txcomp
490 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 33.10.8 twi interrupt disable register name: twi_idr addresses: 0xfffac028 (0), 0xfffd8028 (1) access: write-only reset value: 0x00000000 ? txcomp: transmission completed interrupt disable ? rxrdy: receive holding regi ster ready interrupt disable ? txrdy: transmit holding register ready interrupt disable ? svacc: slave access interrupt disable ? gacc: general call access interrupt disable ? ovre: overrun error interrupt disable ? nack: not acknowledge interrupt disable ? arblst: arbitration lost interrupt disable ? scl_ws: clock wait state interrupt disable ? eosacc: end of slave access interrupt disable ? endrx: end of receive buffer interrupt disable ? endtx: end of transmit buffer interrupt disable ? rxbuff: receive buffer full interrupt disable ? txbufe: transmit buffer empty interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 txbufe rxbuff endtx endrx eosacc scl_ws arblst nack 76543210 ? ovre gacc svacc ? txrdy rxrdy txcomp
491 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 33.10.9 twi interrupt mask register name: twi_imr addresses: 0xfffac02c (0), 0xfffd802c (1) access: read-only reset value: 0x00000000 ? txcomp: transmission completed interrupt mask ? rxrdy: receive holding regi ster ready interrupt mask ? txrdy: transmit holding register ready interrupt mask ? svacc: slave access interrupt mask ? gacc: general call access interrupt mask ? ovre: overrun error interrupt mask ? nack: not acknowledge interrupt mask ? arblst: arbitration lost interrupt mask ? scl_ws: clock wait state interrupt mask ? eosacc: end of slave access interrupt mask ? endrx: end of receive buffer interrupt mask ? endtx: end of transmit buffer interrupt mask ? rxbuff: receive buffer full interrupt mask ? txbufe: transmit buffer empty interrupt mask 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 txbufe rxbuff endtx endrx eosacc scl_ws arblst nack 76543210 ? ovre gacc svacc ? txrdy rxrdy txcomp
492 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 33.10.10 twi receive holding register name: twi_rhr addresses: 0xfffac030 (0), 0xfffd8030 (1) access: read-only reset value: 0x00000000 ? rxdata: master or slave receive holding data 33.10.11 twi transmit holding register name: twi_thr addresses: 0xfffac034 (0), 0xfffd8034 (1) access: read-write reset value: 0x00000000 ? txdata: master or slave transmit holding data 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rxdata 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 txdata
493 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34. universal synchronous asynchrono us receiver transceiver (usart) 34.1 description the universal synchronous asynchronous rece iver transceiver (usart) provides one full duplex universal synchronous asynchronous serial link. data frame format is widely programma- ble (data length, parity, number of stop bits) to support a maximum of standards. the receiver implements parity error, framing error and overrun error detection. the receiver time-out enables handling variable-length frames and the transmitt er timeguard facilitates communications with slow remote devices. multidrop communications are also supported through address bit han- dling in reception and transmission. the usart features three test modes: remote loopback, local loopback and automatic echo. the usart supports specific operating modes providing interfaces on rs485 buses, with iso7816 t = 0 or t = 1 smart card slots, infrared transceivers and connection to modem ports. the hardware handshaking feature enables an out-of-band flow control by automatic manage- ment of the pins rts and cts. the usart supports the connection to the peripheral dma controller, which enables data transfers to the transmitter and from the receiver. the pdc provides chained buffer manage- ment without any intervention of the processor.
494 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.2 block diagram figure 34-1. usart block diagram peripheral dma controller channel channel aic receiver usart interrupt rxd txd sck usart pio controller cts rts dtr dsr dcd ri transmitter modem signals control baud rate generator user interface pmc mck slck div mck/div apb
495 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.3 application block diagram figure 34-2. application block diagram smart card slot usart rs232 drivers modem rs485 drivers differential bus irda transceivers modem driver field bus driver emv driver irda driver irlap rs232 drivers serial port serial driver ppp pstn
496 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.4 i/o lines description table 34-1. i/o line description name description type active level sck serial clock i/o txd transmit serial data i/o rxd receive serial data input ri ring indicator input low dsr data set ready input low dcd data carrier detect input low dtr data terminal ready output low cts clear to send input low rts request to send output low
497 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.5 product dependencies 34.5.1 i/o lines the pins used for interfacing the usart may be multiplexed with the pio lines. the program- mer must first program the pio controller to assign the desired usart pins to their peripheral function. if i/o lines of the usart are not used by the application, they can be used for other purposes by the pio controller. to prevent the txd line from falling when the usart is di sabled, the use of an internal pull up is mandatory. if the hardware handshaking feature or modem mode is used, the internal pull up on txd must also be enabled. all the pins of the modems may or may not be implemented on the usart. only usart 0 is fully equipped with all the modem signals. on usarts not equipped with the corresponding pin, the associated control bits and statuses have no effect on the behavior of the usart. 34.5.2 power management the usart is not continuously clocked. the pr ogrammer must first enable the usart clock in the power management controller (pmc) before usin g the usart. however, if the application does not require usart operations, the usart clock can be stopped when not needed and be restarted later. in this case, the usart will resume its operations where it left off. configuring the usart does not require the usart clock to be enabled. 34.5.3 interrupt the usart interrupt line is connected on one of the internal sources of the advanced interrupt controller. using the usart interrup t requires the aic to be programmed first. note that it is not recommended to use the usart interrupt line in edge sensitive mode.
498 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.6 functional description the usart is capable of managing several ty pes of serial synchronous or asynchronous communications. it supports the following communication modes: ? 5- to 9-bit full-duplex asynchronous serial communication ? msb- or lsb-first ? 1, 1.5 or 2 stop bits ? parity even, odd, marked, space or none ? by 8 or by 16 over-sampling receiver frequency ? optional hardware handshaking ? optional modem signals management ? optional break management ? optional multidrop serial communication ? high-speed 5- to 9-bit full-duplex synchronous serial communication ? msb- or lsb-first ? 1 or 2 stop bits ? parity even, odd, marked, space or none ? by 8 or by 16 over-sampling frequency ? optional hardware handshaking ? optional modem signals management ? optional break management ? optional multidrop serial communication ? rs485 with driver control signal ? iso7816, t0 or t1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit ? infrared irda modulation and demodulation ? test modes ? remote loopback, local loopback, automatic echo
499 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.6.1 baud rate generator the baud rate generator provides the bit period clock named the baud rate clock to both the receiver and the transmitter. the baud rate generator clock source can be selected by setting the usclks field in the mode register (us_mr) between: ? the master clock mck ? a division of the master clock, the divider being product dependent, but generally set to 8 ? the external clock, available on the sck pin the baud rate generator is based upon a 16-bit divider, which is programmed with the cd field of the baud rate generator register (us_brgr). if cd is programmed at 0, the baud rate generator does not generate any clock. if cd is programmed at 1, the divider is bypassed and becomes inactive. if the external sck clock is selected, the duration of the low and high levels of the signal pro- vided on the sck pin must be longer than a master clock (mck) period. the frequency of the signal provided on sck must be at least 4.5 times lower than mck. figure 34-3. baud rate generator 34.6.1.1 baud rate in asynchronous mode if the usart is programmed to operate in as ynchronous mode, the selected clock is first divided by cd, which is field programmed in the baud rate generator register (us_brgr). the resulting clock is provided to the receiv er as a sampling clock and then divided by 16 or 8, depending on the programming of the over bit in us_mr. if over is set to 1, the receiver sampling is 8 times higher than the baud rate clock. if over is cleared, the sampling is performed at 16 times the baud rate clock. the following formula performs the calculation of the baud rate. this gives a maximum baud rate of mck divided by 8, assuming that mck is the highest possi- ble clock and that over is programmed at 1. mck/div 16-bit counter 0 baud rate clock cd cd sampling divider 0 1 >1 sampling clock reserved mck sck usclks over sck sync sync usclks = 3 1 0 2 3 0 1 0 1 fidi baudrate selectedclock 82 over ? () cd () -------------------------------------------- =
500 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.6.1.2 baud rate calculation example table 34-2 shows calculations of cd to obtain a baud rate at 38400 bauds for different source clock frequencies. this table also shows the actual resulting baud rate and the error. the baud rate is calculated with the following formula: the baud rate error is calculated with the following formula. it is not recommended to work with an error higher than 5%. 34.6.1.3 fractional baud rate in asynchronous mode the baud rate generator previously defined is su bject to the following limitation: the output fre- quency changes by only integer multiples of the reference frequency. an approach to this problem is to integrate a fractional n clock generator that has a high resolution. the generator architecture is modified to obtain baud rate c hanges by a fraction of the reference source clock. this fractional part is programmed with the fp field in the baud rate generator register (us_brgr). if fp is not 0, the fractional part is activated. the resolution is one eighth of the table 34-2. baud rate example (over = 0) source clock expected baud rate calculation result cd actual baud rate error mhz bit/s bit/s 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.00% 8 000 000 38 400 13.02 13 38 461.54 0.16% 12 000 000 38 400 19.53 20 37 500.00 2.40% 12 288 000 38 400 20.00 20 38 400.00 0.00% 14 318 180 38 400 23.30 23 38 908.10 1.31% 14 745 600 38 400 24.00 24 38 400.00 0.00% 18 432 000 38 400 30.00 30 38 400.00 0.00% 24 000 000 38 400 39.06 39 38 461.54 0.16% 24 576 000 38 400 40.00 40 38 400.00 0.00% 25 000 000 38 400 40.69 40 38 109.76 0.76% 32 000 000 38 400 52.08 52 38 461.54 0.16% 32 768 000 38 400 53.33 53 38 641.51 0.63% 33 000 000 38 400 53.71 54 38 194.44 0.54% 40 000 000 38 400 65.10 65 38 461.54 0.16% 50 000 000 38 400 81.38 81 38 580.25 0.47% baudrate mck cd 16 ? = error 1 expectedbaudrate actualbaudrate -------------------------------------------------- - ?? ?? ? =
501 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary clock divider. this feature is only available when using usart normal mode. the fractional baud rate is calculated using the following formula: the modified architecture is presented below: figure 34-4. fractional baud rate generator 34.6.1.4 baud rate in synchronous mode if the usart is programmed to operate in synchronous mode, the selected clock is simply divided by the field cd in us_brgr. in synchronous mode, if the external clock is selected (usclks = 3), the clock is provided directly by the signal on the usart sck pin. no division is active. the value written in us_brgr has no effect. the external clock frequency must be at least 4.5 times lower than the system clock. when either the external clock sck or the inte rnal clock divided (mck/div) is selected, the value programmed in cd must be even if the user has to ensure a 50:50 mark/space ratio on the sck pin. if the internal clock mck is selected, the baud rate generator ensures a 50:50 duty cycle on the sck pin, even if the value programmed in cd is odd. 34.6.1.5 baud rate in iso 7816 mode the iso7816 specification defines the bit rate with the following formula: baudrate selectedclock 82 over ? () cd fp 8 ------- + ?? ?? ?? ?? ---------------------------------------------------------------- - = mck/div 16-bit counter 0 baud rate clock cd cd sampling divider 0 1 >1 sampling clock reserved mck sck usclks over sck sync sync usclks = 3 1 0 2 3 0 1 0 1 fidi glitch-free logic modulus control fp fp baudrate selectedclock cd ------------------------------------- - =
502 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary where: ? b is the bit rate ? di is the bit-rate adjustment factor ? fi is the clock frequency division factor ? f is the iso7816 clock frequency (hz) di is a binary value encoded on a 4-bit field, named di, as represented in table 34-3 . fi is a binary value encoded on a 4-bi t field, named fi, as represented in table 34-4 . table 34-5 shows the resulting fi/di ratio, which is the ratio between the iso7816 clock and the baud rate clock. if the usart is configured in iso7816 mode, th e clock selected by the usclks field in the mode register (us_mr) is first divided by the value programmed in the field cd in the baud rate generator register (us_brgr). the resulting clock can be provided to the sck pin to feed the smart card clock inputs. this means that the clko bit can be set in us_mr. this clock is then divided by the value progra mmed in the fi_di_ratio field in the fi_di_ratio register (us_fidi). this is performed by the sampling divider, which performs a division by up to 2047 in iso7816 mode. the non-integer values of the fi/di ratio are not supported and the user must program the fi_di_ratio field to a va lue as close as possible to the expected value. the fi_di_ratio field resets to the value 0x174 (372 in decimal) and is the most common divider between the iso7816 clock and the bit rate (fi = 372, di = 1). figure 34-5 shows the relation between the elementary time unit, corresponding to a bit time, and the iso 7816 clock. b di fi ----- - f = table 34-3. binary and decimal values for di di field 0001 0010 0011 0100 0101 0110 1000 1001 di (decimal)1 2 4 8 163212 20 table 34-4. binary and decimal values for fi fi field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 fi (decimal 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048 table 34-5. possible values for the fi/di ratio fi/di 372 558 774 1116 1488 1806 512 768 1024 1536 2048 1 372 558 744 1116 1488 1860 512 768 1024 1536 2048 2 186 279 372 558 744 930 256 384 512 768 1024 4 93 139.5 186 279 372 465 128 192 256 384 512 8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256 16 23.25 34.87 46.5 69.75 93 116.2 32 48 64 96 128 32 11.62 17.43 23.25 34.87 46.5 58.13 16 24 32 48 64 12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6 20 18.6 27.9 37.2 55.8 74.4 93 25.6 38.4 51.2 76.8 102.4
503 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 34-5. elementary time unit (etu) 34.6.2 receiver and transmitter control after reset, the receiver is disabled. the user must enable the receiver by setting the rxen bit in the control register (us_cr). however, the receiver registers can be programmed before the receiver clock is enabled. after reset, the transmitter is disabled. the user must enable it by setting the txen bit in the control register (us_cr). however, the transmitter registers can be programmed before being enabled. the receiver and the transmitter can be enabled together or independently. at any time, the software can perform a reset on the receiver or the transmitter of the usart by setting the corresponding bit, rstrx and rsttx respectively, in the control register (us_cr). the software resets clear the status flag and reset internal state machines but the user interface configuration registers hold the value configured prior to software reset. regard- less of what the receiver or the transmitter is performing, the communi cation is immediately stopped. the user can also independently disable the receiv er or the transmitter by setting rxdis and txdis respectively in us_cr. if the receiver is disabled during a character reception, the usart waits until the end of reception of the current character, then the reception is stopped. if the transmitter is disabled while it is operating, the usart waits the end of transmission of both the current character and character being stored in the transmit holding register (us_thr). if a timeguard is programmed, it is handled normally. 34.6.3 synchronous and asynchronous modes 34.6.3.1 transmitter operations the transmitter performs the same in both synchronous and asynchronous operating modes (sync = 0 or sync = 1). one start bit, up to 9 da ta bits, one optional parity bit and up to two stop bits are successively shifted out on the txd pin at each falling edge of the programmed serial clock. the number of data bits is selected by the chrl field and the mode 9 bit in the mode register (us_mr). nine bits are selected by setting the mode 9 bit regardless of the chrl field. the parity bit is set according to the par field in us_mr. the even, odd, space, marked or none parity bit can be configured. the msbf field in us _mr configures which data bit is sent first. if written at 1, the most significant bit is sent first. at 0, the less significant bit is sent first. the num- ber of stop bits is selected by the nbstop fiel d in us_mr. the 1.5 stop bit is supported in asynchronous mode only. 1 etu iso7816 clock on sck iso7816 i/o line on txd fi_di_ratio iso7816 clock cycles
504 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 34-6. character transmit the characters are sent by writing in the tran smit holding register (us_thr). the transmitter reports two status bits in the channel status register (us_csr): txrdy (transmitter ready), which indicates that us_thr is empty and txempty, which indicates that all the characters written in us_thr have been processed. when the current character processing is completed, the last character written in us_thr is transferred into the shift register of the transmitter and us_thr becomes empty, thus txrdy rises. both txrdy and txempty bits are low when the transmitter is disabled. writing a character in us_thr while txrdy is low has no effect and the written character is lost. figure 34-7. transmitter status 34.6.3.2 manchester encoder when the manchester encoder is in use, c haracters transmitted through the usart are encoded based on biphase manchester ii format. to enable this mode, set the man field in the us_mr register to 1. depending on polarity configur ation, a logic level (zero or one), is transmit- ted as a coded signal one-to-zero or zero-to-one. thus, a transition always occurs at the midpoint of each bit time. it consumes more bandwidth than the original nrz signal (2x) but the receiver has more error control since the expected input must show a change at the center of a bit cell. an example of manchester encoded sequence is: the byte 0xb1 or 10110001 encodes to 10 01 10 10 01 01 01 10, assuming the default polarity of the encoder. figure 34-8 illustrates this coding scheme. d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit example: 8-bit, parity enabled one stop baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock start bit write us_thr d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit txrdy txempty
505 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 34-8. nrz to manchester encoding the manchester encoded character can also be enc apsulated by adding both a configurable preamble and a start frame delimiter pattern. depending on the configuration, the preamble is a training sequence, composed of a pre-defined pattern with a programmable length from 1 to 15 bit times. if the preamble length is set to 0, the preamble waveform is not generated prior to any character. the preamble pattern is chosen among the following sequences: all_one, all_zero, one_zero or zero_one, writing th e field tx_pp in the us_man register, the field tx_pl is used to configure the preamble length. figure 34-9 illustrates and defines the valid patterns. to improve flexibility, the encoding scheme can be configured using the tx_mpol field in the us_man register. if the tx _mpol field is set to zero (default), a logic zero is encoded with a zero-to-one transition and a logic one is encoded with a one-to-zero tran- sition. if the tx_mpol field is set to one, a logic one is encoded with a one-to-zero transition and a logic zero is encoded with a zero-to-one transition. figure 34-9. preamble patterns, default polarity assumed a start frame delimiter is to be configured using the onebit field in the us_mr register. it con- sists of a user-defined pattern that indicates the beginning of a valid data. figure 34-10 illustrates these pattern s. if the start frame delimiter, also kn own as start bit, is one bit, (onebit at 1), a logic zero is manchester encoded and in dicates that a new character is being sent seri- ally on the line. if the start frame delimiter is a synchronization pattern also referred to as sync (onebit at 0), a sequence of 3 bit times is sent serially on the line to indicate the start of a new nrz encoded data manchester encoded data 10110001 txd manchester encoded data txd sfd data 8 bit width "all_one" preamble manchester encoded data txd sfd data 8 bit width "all_zero" preamble manchester encoded data txd sfd data 8 bit width "zero_one" preamble manchester encoded data txd sfd data 8 bit width "one_zero" preamble
506 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary character. the sync waveform is in itself an invalid manchester waveform as the transition occurs at the middle of the second bit time. tw o distinct sync patterns are used: the command sync and the data sync. the co mmand sync has a logic one level for one and a half bit times, then a transition to logic zero for the second one and a half bit times. if the modsync field in the us_mr register is set to 1, the next character is a command. if it is set to 0, the next charac- ter is a data. when direct memory access is used, the modsync field can be immediately updated with a modified character located in memory. to enable this mode, var_sync field in us_mr register must be set to 1. in this ca se, the modsync field in us_mr is bypassed and the sync configuration is held in the txsynh in the us_thr register. the usart character for- mat is modified and includes sync information. figure 34-10. start frame delimiter 34.6.3.3 drift compensation drift compensation is available only in 16x oversampling mode. an ha rdware recovery system allows a larger clock drift. to enable the ha rdware system, the bit in the usart_man register must be set. if the rxd edge is one 16x clock c ycle from the expected edge, this is considered as normal jitter and no corrective actions is taken. if the rxd event is between 4 and 2 clock cycles before the expected edge, then the current per iod is shortened by one clock cycle. if the rxd event is between 2 and 3 clock cycles after the expected edge, then the current period is lengthened by one clock cycle. these intervals are considered to be drift and so corrective actions are automatically taken. manchester encoded data txd sfd data one bit start frame delimiter preamble length is set to 0 manchester encoded data txd sfd data command sync start frame delimiter manchester encoded data txd sfd data data sync start frame delimiter
507 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 34-11. bit resynchronization 34.6.3.4 asynchronous receiver if the usart is programmed in asynchronous operating mode (sync = 0), the receiver over- samples the rxd input line. the oversampling is either 16 or 8 times the baud rate clock, depending on the over bit in the mode register (us_mr). the receiver samples the rxd line. if the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. if the oversampling is 16, (over at 0), a start is detected at the eighth sample at 0. then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. if the oversampling is 8 (over at 1), a start bit is detected at the fourth sample at 0. then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. the number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively chrl , mode9, msbf and par. for the synchronization mechanism only , the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field nbstop, so that resynchronization between the receiver and the transmitter can occur. moreover, as soon as the st op bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. figure 34-12 and figure 34-13 illustrate start detection and character reception when usart operates in asynchronous mode. rxd oversampling 16x clock sampling point expected edge tolerance synchro. jump sync jump synchro. error synchro. error
508 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 34-12. asynchronous start detection figure 34-13. asynchronous character reception 34.6.3.5 manchester decoder when the man field in us_mr register is set to 1, the manchester decoder is enabled. the decoder performs both preamble and start frame delimiter detection. one input line is dedicated to manchester encoded input data. an optional preamble sequence can be defined, it s length is user-defined and totally indepen- dent of the emitter side. use rx_pl in us_man register to configure the length of the preamble sequence. if the length is set to 0, no preamble is detected and the function is disabled. in addi- tion, the polarity of the input stream is programmable with rx_mpol field in us_man register. depending on the desired application the preamble pattern matching is to be defined via the rx_pp field in us_man. see figure 34-9 for available preamble patterns. unlike preamble, the start frame delimiter is shared between manchester encoder and decoder. so, if onebit field is set to 1, only a zero encoded manchester can be detected as a valid start frame delimiter. if onebit is set to 0, only a sync pattern is detected as a valid start frame delimiter. decoder operates by detecting transition on incoming stream. if rxd is sampled dur- ing one quarter of a bit time at zero, a start bit is detected. see figure 34-14 .. the sample pulse rejection mechanism applies. sampling clock (x16) rxd start detection sampling baud rate clock rxd start rejection sampling 12345678 12345670 1234 12345678 9 10111213141516 d0 sampling d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit stop bit example: 8-bit, parity enabled baud rate clock start detection 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples
509 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 34-14. asynchronous star t bit detection the receiver is activated and starts preamble and frame delimiter detection, sampling the data at one quarter and then three quarters. if a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding with the same synchronization. if the stream does not match a valid pattern or a valid start frame delimiter, the receiver re-synchronizes on the next valid edge.the minimum time threshold to estimate the bit value is three quarters of a bit time. if a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming stream is decoded into nrz data and passed to usart for processing. figure 34-15 illustrates manchester pattern mismatch. when incoming data stream is passed to the usart, the receiver is also able to detect manchester code vi olation. a code violation is a lack of transition in the middle of a bit cell. in this case, mane flag in us_csr register is raised. it is cleared by writing the control register (us_cr) with the rststa bit at 1. see figure 34-16 for an exam- ple of manchester error detection during data phase. figure 34-15. preamble pattern mismatch figure 34-16. manchester error flag manchester encoded data txd 1234 sampling clock (16 x) start detection manchester encoded data txd sfd data preamble length is set to 8 preamble mismatch invalid pattern preamble mismatch manchester coding error manchester encoded data txd sfd preamble length is set to 4 elementary character bit time manchester coding error detected sampling points preamble subpacket and start frame delimiter were successfully decoded entering usart character area
510 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary when the start frame delimiter is a sync pattern (onebit field at 0), both command and data delimiter are supported. if a valid sync is detec ted, the received character is written as rxchr field in the us_rhr register and the rxsynh is updated. rxchr is set to 1 when the received character is a command, and it is set to 0 if the received character is a data. this mechanism alleviates and simplifies the direct memory access as the character contains its own sync field in the same register. as the decoder is setup to be used in unipolar mode, the first bit of the frame has to be a zero-to- one transition. 34.6.3.6 radio interface: manchester encoded usart application this section describes low data rate rf transm ission systems and their integration with a man- chester encoded usart. these systems are based on transmitter and receiver ics that support ask and fsk modulation schemes. the goal is to perform full duplex radio transmissi on of characters using two different frequency carriers. see the configuration in figure 34-17 . figure 34-17. manchester encoded characters rf transmission the usart module is configured as a manchester encoder/decoder. looking at the down- stream communication channel, manchester encoded characters are serially sent to the rf emitter. this may also include a user defined preamble and a start frame delimiter. mostly, pre- amble is used in the rf receiver to distinguish between a valid data from a transmitter and signals due to noise. the manchester stream is then modulated. see figure 34-18 for an exam- ple of ask modulation scheme. when a logic one is sent to the ask modulator, the power amplifier, referred to as pa, is enabled and transmits an rf signal at downstream frequency. when a logic zero is transmitted, the rf signal is turned off. if the fsk modulator is activated, two different frequencies are used to transmit dat a. when a logic 1 is sent, the modulator out- puts an rf signal at frequency f0 and switches to f1 if the data sent is a 0. see figure 34-19 . lna vco rf filter demod control bi-dir line pa rf filter mod vco control manchester decoder manchester encoder usart receiver usart emitter ask/fsk upstream receiver ask/fsk downstream transmitter upstream emitter downstream receiver serial configuration interface fup frequency carrier fdown frequency carrier
511 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary from the receiver side, another carrier frequency is used. the rf receiver performs a bit check operation examining demodulated data stream. if a valid pattern is detected, the receiver switches to receiving mode. the demodulated stream is sent to the manchester decoder. because of bit checking inside rf ic, the data transferred to the microcontroller is reduced by a user-defined number of bits. the manchester preamble length is to be defined in accordance with the rf ic configuration. figure 34-18. ask modulator output figure 34-19. fsk modulator output 34.6.3.7 synchronous receiver in synchronous mode (sync = 1), the receiver samples the rxd signal on each rising edge of the baud rate clock. if a lo w level is detected, it is considered as a start. all data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. synchronous mode operations provide a high speed transfer capability. configuration fields and bits are the same as in asynchronous mode. figure 34-20 illustrates a character rec eption in synchronous mode. manchester encoded data default polarity unipolar output txd ask modulator output uptstream frequency f0 nrz stream 10 0 1 manchester encoded data default polarity unipolar output txd fsk modulator output uptstream frequencies [f0, f0+offset] nrz stream 10 0 1
512 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 34-20. synchronous mode character reception 34.6.3.8 receiver operations when a character reception is completed, it is transferred to the receive holding register (us_rhr) and the rxrdy bit in the status regist er (us_csr) rises. if a character is com- pleted while the rxrdy is set, the ovre (ove rrun error) bit is set. the last character is transferred into us_rhr and overwrites the previous one. the ovre bit is cleared by writing the control register (us_cr) with the rststa (reset status) bit at 1. figure 34-21. receiver status d0 d1 d2 d3 d4 d5 d6 d7 rxd start sampling parity bit stop bit example: 8-bit, parity enabled 1 stop baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit parity bit stop bit baud rate clock write us_cr rxrdy ovre d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit rststa = 1 read us_rhr
513 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.6.3.9 parity the usart supports five parity modes selected by programming the par field in the mode register (us_mr). the par field also enables the multidrop mode, see ?multidrop mode? on page 514 . even and odd parity bit generation and error detection are supported. if even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a num- ber of 1s in the character data bit is even, and at 1 if the number of 1s is odd. accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sam- pled parity bit does not correspond. if odd parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. if the mark parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters. the receiver parity checker reports an error if the parity bit is sampled at 0. if the space parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. the receiver parity checker reports an error if the parity bit is sampled at 1. if parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. table 34-6 shows an example of the parity bit for the character 0x41 (character ascii ?a?) depending on the configuration of the usart. because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. when the receiver detects a parity error, it sets the pare (parity error) bit in the channel status register (us_csr). the pare bit can be cleared by writing the control register (us_cr) with the rststa bit at 1. figure 34-22 illustrates the parity bit status setting and clearing. table 34-6. parity bit examples character hexa binary parity bit parity mode a 0x41 0100 0001 1 odd a 0x41 0100 0001 0 even a 0x41 0100 0001 1 mark a 0x41 0100 0001 0 space a 0x41 0100 0001 none none
514 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 34-22. parity error 34.6.3.10 multidrop mode if the par field in the mode register (us_mr) is programmed to the value 0x6 or 0x07, the usart runs in multidrop mode. this mode differentiates the data characters and the address characters. data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. if the usart is configured in multidrop mode, the receiver sets the pare parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the control register is written with the senda bit at 1. to handle parity error, the pare bit is cleared when the control register is written with the bit rststa at 1. the transmitter sends an address byte (parity bit set) when senda is written to us_cr. in this case, the next byte written to us_thr is trans mitted as an address. any character written in us_thr without having written the command senda is transmitted normally with the parity at 0. 34.6.3.11 transmitter timeguard the timeguard feature enables the usar t interface with slow remote devices. the timeguard function enables the transmitter to insert an idle state on the txd line between two characters. this idle state actually acts as a long stop bit. the duration of the idle state is programmed in the tg field of the transmitter timeguard regis- ter (us_ttgr). when this field is programmed at zero no timeguard is generated. otherwise, the transmitter holds a high level on txd after each transmitted byte during the number of bit periods programmed in tg in addition to the number of stop bits. as illustrated in figure 34-23 , the behavior of txrdy and txempty status bits is modified by the programming of a timeguard. txrdy rises only when the start bit of the next character is sent, and thus remains at 0 during the timeguard transmission if a character has been written in us_thr. txempty remains low until the timeguard transmission is completed as the time- guard is part of the current character being transmitted. d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit bad parity bit stop bit baud rate clock write us_cr pare rxrdy rststa = 1
515 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 34-23. timeguard operations table 34-7 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the baud rate. 34.6.3.12 receiver time-out the receiver time-out provides support in handling variable-length frames. this feature detects an idle condition on the rxd line. when a time-out is detected, the bit timeout in the channel status register (us_csr) rises and can generate an interrupt, thus indicating to the driver an end of frame. the time-out delay period (during which the receiver waits for a new character) is programmed in the to field of the receiver time-out regist er (us_rtor). if the to field is programmed at 0, the receiver time-out is disabled and no time-out is detected. the timeout bit in us_csr remains at 0. otherwise, the receiver loads a 16-bit counter with the value programmed in to. this counter is decremented at each bit per iod and reloaded each time a new character is received. if the counter reaches 0, the timeout bit in the status register rises. then, the user can either: ? stop the counter clock until a new character is received. this is performed by writing the control register (us_cr) with the sttto (start time-out) bit at 1. in this case, the idle state d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock start bit tg = 4 write us_thr d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit txrdy txempty tg = 4 table 34-7. maximum timeguard length depending on baud rate baud rate bit time timeguard bit/sec s ms 1 200 833 212.50 9 600 104 26.56 14400 69.4 17.71 19200 52.1 13.28 28800 34.7 8.85 33400 29.9 7.63 56000 17.9 4.55 57600 17.4 4.43 115200 8.7 2.21
516 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary on rxd before a new character is received will not provide a time-out. this prevents having to handle an interrupt before a character is received and allows waiting for the next idle state on rxd after a frame is received. ? obtain an interrupt while no character is rece ived. this is performed by writing us_cr with the retto (reload and start time-out) bit at 1. if retto is performed, the counter starts counting down immediately from the value to. this enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. if sttto is performed, the counter clock is stopped until a first character is received. the idle state on rxd before the start of the frame does not provide a time-out. this prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on rxd is detected. if retto is performed, the counter starts counting down immediately from the value to. this enables generation of a periodic interrupt so t hat a user time-out can be handled, for example when no key is pressed on a keyboard. figure 34-24 shows the block diagram of the receiver time-out feature. figure 34-24. receiver time-out block diagram table 34-8 gives the maximum time-out period for some standard baud rates. table 34-8. maximum time-out period baud rate bit time time-out bit/sec s ms 600 1 667 109 225 1 200 833 54 613 2 400 417 27 306 4 800 208 13 653 9 600 104 6 827 14400 69 4 551 19200 52 3 413 28800 35 2 276 33400 30 1 962 16-bit time-out counter 0 to timeout baud rate clock = character received retto load clock 16-bit value sttto dq 1 clear
517 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.6.3.13 framing error the receiver is capable of detecting framing errors. a framing error happens when the stop bit of a received character is detected at level 0. this can occur if the receiver and the transmitter are fully desynchronized. a framing error is reported on the frame bit of the channel status register (us_csr). the frame bit is asserted in the middle of the stop bit as soon as the framing error is detected. it is cleared by writing the control register (us_cr) with the rststa bit at 1. figure 34-25. framing error status 34.6.3.14 transmit break the user can request the transmitter to generate a break condition on the txd line. a break con- dition drives the txd line low during at least one complete character. it appears the same as a 0x00 character sent with the parity and the stop bits at 0. however, the transmitter holds the txd line at least during one character until the user requests the break condition to be removed. a break is transmitted by writing the control register (us_cr) with the sttbrk bit at 1. this can be performed at any time, either while the transmitter is empty (no character in either the shift register or in us_thr) or when a character is being transmitted. if a break is requested while a character is being shifted out, the charac ter is first completed before the txd line is held low. once sttbrk command is requested further sttbrk commands are ignored until the end of the break is completed. the break condition is removed by writing us_cr with the stpbrk bit at 1. if the stpbrk is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. 56000 18 1 170 57600 17 1 138 200000 5 328 table 34-8. maximum time-out period (continued) baud rate bit time time-out d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit parity bit stop bit baud rate clock write us_cr frame rxrdy rststa = 1
518 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary the transmitter considers the break as though it is a character, i.e. the sttbrk and stpbrk commands are taken into account only if the txrdy bit in us_csr is at 1 and the start of the break condition clears the txrdy and txempty bits as if a character is processed. writing us_cr with the both sttbrk and stpb rk bits at 1 can lead to an unpredictable result. all stpbrk commands requested without a previous sttbrk command are ignored. a byte written into the transmit holding register while a break is pending, but not started, is ignored. after the break condition, the transmitter returns the txd line to 1 for a minimum of 12 bit times. thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. if the timeguard is programmed with a value higher than 12, the txd line is held high for the timeguard period. after holding the txd line for this period, the transmitter resumes normal operations. figure 34-26 illustrates the effect of both the start break (sttbrk ) and stop break (stpbrk) commands on the txd line. figure 34-26. break transmission 34.6.3.15 receive break the receiver detects a break condition when all data, parity and stop bits are low. this corre- sponds to detecting a framing error with data at 0x00, but frame remains low. when the low stop bit is detected, the receiver asserts the rxbrk bit in us_csr. this bit may be cleared by writing the control regi ster (us_cr) with the bit rststa at 1. an end of receive break is detected by a high leve l for at least 2/16 of a bit period in asynchro- nous operating mode or one sample at high level in synchronous operating mode. the end of break detection also asserts the rxbrk bit. 34.6.3.16 hardware handshaking the usart features a hardware handshaking out-of-band flow control. the rts and cts pins are used to connect with the remote device, as shown in figure 34-27 . d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock write us_cr txrdy txempty stpbrk = 1 sttbrk = 1 break transmission end of break
519 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 34-27. connection with a remote device for hardware handshaking setting the usart to operate with hardware handshaking is performed by writing the usart_mode field in the mode register (us_mr) to the value 0x2. the usart behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the rts pin as described below and the level on the cts pin modifies the behavior of the transmitter as described below. using this mode requires usin g the pdc channel for reception. the transmitter can handle hardware handshaking in any case. figure 34-28 shows how the receiver operates if hardware handshaking is enabled. the rts pin is driven high if the receiver is disabled and if the status rxbuff (receive buffer full) com- ing from the pdc channel is high. normally, the remote device does not start transmitting while its cts pin (driven by rts) is high. as soon as the receiver is enabled , the rts falls, indicating to the remote device that it can start transmitt ing. defining a new buffer to the pdc clears the status bit rxbuff and, as a result, asserts the pin rts low. figure 34-28. receiver behavior when operating with hardware handshaking figure 34-29 shows how the transmitter operates if hardware handshaking is enabled. the cts pin disables the transmitt er. if a character is being processi ng, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin cts falls. figure 34-29. transmitter behavior when operating with hardware handshaking usart txd cts remote device rxd txd rxd rts rts cts rts rxbuff write us_cr rxen = 1 rxd rxdis = 1 cts txd
520 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.6.4 iso7816 mode the usart features an iso7816-compatible operating mode. this mode permits interfacing with smart cards and security access modules (sam) communicating through an iso7816 link. both t = 0 and t = 1 protocols defined by the iso7816 specification are supported. setting the usart in iso7816 mode is performed by writing the usart_mode field in the mode register (us_mr) to the value 0x4 for protoc ol t = 0 and to the value 0x5 for protocol t = 1. 34.6.4.1 iso7816 mode overview the iso7816 is a half duplex communication on only one bidirectional line. the baud rate is determined by a division of the clo ck provided to the remote device (see ?baud rate generator? on page 499 ). the usart connects to a smart card as shown in figure 34-30 . the txd line becomes bidirec- tional and the baud rate generator feeds the iso7816 clock on the sck pin. as the txd pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is direct ed to the input of the receiver. the usart is con- sidered as the master of the communication as it generates the clock. figure 34-30. connection of a smart card to the usart when operating in iso7816, either in t = 0 or t = 1 modes, the character format is fixed. the configuration is 8 data bits, ev en parity and 1 or 2 stop bits, regardless of the values pro- grammed in the chrl, mode9, par and chmode fields. msbf can be used to transmit lsb or msb first. parity bit (par) can be used to transmit in normal or inverse mode. refer to ?usart mode register? on page 532 and ?par: parity type? on page 533 . the usart cannot operate concurrently in both receiver and transmitter modes as the commu- nication is unidirectional at a time. it has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. enabling both the receiver and the transmitter at the same time in iso7816 mode may lead to unpredictable results. the iso7816 specification defines an inverse transmission format. data bits of the character must be transmitted on the i/o line at their negative value. the usart does not support this for- mat and the user has to perform an exclusive or on the data before writing it in the transmit holding register (us_thr) or after reading it in the receive holding register (us_rhr). 34.6.4.2 protocol t = 0 in t = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. the transmitter shifts out the bits and does not drive the i/o line during the guard time. if no parity error is detected, the i/o line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in figure 34-31 . smart card sck clk txd i/o usart
521 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary if a parity error is detected by the receiver, it drives the i/o line at 0 during the guard time, as shown in figure 34-32 . this error bit is also named nack, for non acknowledge. in this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. when the usart is the receiver and it detects an error, it does not load the erroneous character in the receive holding register (us_rhr). it appropriately sets the pare bit in the status reg- ister (us_sr) so that the software can handle the error. figure 34-31. t = 0 protocol without parity error figure 34-32. t = 0 protocol with parity error 34.6.4.3 receive error counter the usart receiver also records the total number of errors. this can be read in the number of error (us_ner) register. the nb_errors field can record up to 255 errors. reading us_ner automatically clears the nb_errors field. 34.6.4.4 receive nack inhibit the usart can also be configured to inhibit an error. this can be achieved by setting the inack bit in the mode register (us_mr). if inack is at 1, no error signal is driven on the i/o line even if a parity bit is detected, but the inac k bit is set in the status register (us_sr). the inack bit can be cleared by writing the control register (us_cr) with the rstnack bit at 1. moreover, if inack is set, the erroneous receiv ed character is stored in the receive holding register, as if no error occurred. however, the rxrdy bit does not raise. 34.6.4.5 transmit character repetition when the usart is transmitting a character and gets a nack, it can automatically repeat the character before moving on to the next one. repetition is enabled by writing the max_iteration field in the mode register (us_mr) at a value higher than 0. each character can be transmitted up to eight times; the first transmission plus seven repetitions. if max_iteration does not equal zero, the u sart repeats the character as many times as the value loaded in max_iteration. d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit baud rate clock start bit guard time 1 next start bit guard time 2 d0 d1 d2 d3 d4 d5 d6 d7 i/o parity bit baud rate clock start bit guard time 1 start bit guard time 2 d0 d1 error repetition
522 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary when the usart repetition number reaches max_iteration, the iteration bit is set in the channel status register (us_csr). if the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. the iteration bit in us_csr can be cleared by writing the control register with the rsit bit at 1. 34.6.4.6 disable successive receive nack the receiver can limit the number of successive nacks sent back to the remote transmitter. this is programmed by setting the bit dsnack in the mode register (us_mr). the maximum number of nack transmitted is programmed in the max_iteration field. as soon as max_iteration is reached, the character is cons idered as correct, an acknowledge is sent on the line and the iteration bit in the channel status register is set. 34.6.4.7 protocol t = 1 when operating in iso7816 protocol t = 1, the transmission is similar to an asynchronous for- mat with only one stop bit. the parity is generated when transmitting and checked when receiving. parity error detection sets the pare bit in the channel status register (us_csr). 34.6.5 irda mode the usart features an irda mode supplying half-duplex point-to-point wireless communica- tion. it embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in figure 34-33 . the modulator and demodulator are compliant with the irda specification version 1.1 and support data transfer speeds ranging from 2.4 kb/s to 115.2 kb/s. the usart irda mode is enabled by setting t he usart_mode field in the mode register (us_mr) to the value 0x8. the irda filter register (us_if) allows configuring the demodulator filter. the usart transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. note that the modulator and the demodulator are activated. figure 34-33. connection to irda transceivers the receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. to receive irda signals, the following needs to be done: ? disable tx and enable rx irda transceivers rxd rx txd tx usart demodulator modulator receiver transmitter
523 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? configure the txd pin as pio and set it as an output at 0 (to avoid led emission). disable the internal pull-up (better for power consumption). ? receive data 34.6.5.1 irda modulation for baud rates up to and including 115.2 kbits/sec, the rzi modulation scheme is used. ?0? is represented by a light pulse of 3/16th of a bit time. some examples of signal pulse duration are shown in table 34-9 . figure 34-34 shows an example of character transmission. figure 34-34. irda modulation 34.6.5.2 irda baud rate table 34-10 gives some examples of cd values, baud rate error and pulse duration. note that the requirement on the maximum acceptable error of 1.87% must be met. table 34-9. irda pulse duration baud rate pulse duration (3/16) 2.4 kb/s 78.13 s 9.6 kb/s 19.53 s 19.2 kb/s 9.77 s 38.4 kb/s 4.88 s 57.6 kb/s 3.26 s 115.2 kb/s 1.63 s bit period bit period 3 16 start bit data bits stop bit 0 0 0 0 0 1 1 1 1 1 transmitter output txd table 34-10. irda baud rate error peripheral clock baud rate cd baud rate error pulse time 3 686 400 115 200 2 0.00% 1.63 20 000 000 115 200 11 1.38% 1.63 32 768 000 115 200 18 1.25% 1.63 40 000 000 115 200 22 1.38% 1.63 3 686 400 57 600 4 0.00% 3.26 20 000 000 57 600 22 1.38% 3.26 32 768 000 57 600 36 1.25% 3.26
524 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.6.5.3 irda demodulator the demodulator is based on the irda receive filter co mprised of an 8-bit down counter which is loaded with the value programmed in us_if. when a falling edge is detected on the rxd pin, the filter counter starts counting down at the master clock (mck) speed. if a rising edge is detected on the rxd pin, the counter stops and is reloaded with us_if. if no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. figure 34-35 illustrates the operations of the irda demodulator. figure 34-35. irda demodulator operations as the irda mode uses the same logic as the iso7816, note that the fi_di_ratio field in us_fidi must be set to a value higher than 0 in order to assure irda communications operate correctly. 40 000 000 57 600 43 0.93% 3.26 3 686 400 38 400 6 0.00% 4.88 20 000 000 38 400 33 1.38% 4.88 32 768 000 38 400 53 0.63% 4.88 40 000 000 38 400 65 0.16% 4.88 3 686 400 19 200 12 0.00% 9.77 20 000 000 19 200 65 0.16% 9.77 32 768 000 19 200 107 0.31% 9.77 40 000 000 19 200 130 0.16% 9.77 3 686 400 9 600 24 0.00% 19.53 20 000 000 9 600 130 0.16% 19.53 32 768 000 9 600 213 0.16% 19.53 40 000 000 9 600 260 0.16% 19.53 3 686 400 2 400 96 0.00% 78.13 20 000 000 2 400 521 0.03% 78.13 32 768 000 2 400 853 0.04% 78.13 table 34-10. irda baud rate error (continued) peripheral clock baud rate cd baud rate error pulse time mck rxd receiver input pulse rejected 65432 6 1 65432 0 pulse accepted counter value
525 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.6.6 rs485 mode the usart features the rs485 mode to enable li ne driver control. while operating in rs485 mode, the usart behaves as though in asynch ronous or synchronous mode and configuration of all the parameters is possible. the differenc e is that the rts pin is driven high when the transmitter is operating. the behavior of the rts pin is controlled by the txempty bit. a typical connection of the usart to a rs485 bus is shown in figure 34-36 . figure 34-36. typical connection to a rs485 bus the usart is set in rs485 mode by programming the usart_mode field in the mode regis- ter (us_mr) to the value 0x1. the rts pin is at a level inverse to the txempt y bit. significantly, the rts pin remains high when a timeguard is programmed so that the line can remain driven after the last character com- pletion. figure 34-37 gives an example of the rts waveform during a character transmission when the timeguard is enabled. figure 34-37. example of rts drive with timeguard usart rts txd rxd differential bus d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock tg = 4 write us_thr txrdy txempty rts
526 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.6.7 modem mode the usart features modem mode, which enables control of the signals: dtr (data terminal ready), dsr (data set ready), rts (request to send), cts (clear to send), dcd (data car- rier detect) and ri (ring indicator). while operating in modem mode, the usart behaves as a dte (data terminal equipment) as it drives dtr and rts and can detect level change on dsr, dcd, cts and ri. setting the usart in modem mode is performed by writing the usart_mode field in the mode register (us_mr) to the value 0x3. while operating in modem mode the usart behaves as though in asynchronous mode and all the parameter configurations are available. table 34-11 gives the correspondence of the usart signals with modem connection standards. the control of the dtr output pin is performed by writing the control register (us_cr) with the dtrdis and dtren bits respectively at 1. th e disable command forces the corresponding pin to its inactive level, i.e. high. the enable command forces the corresponding pin to its active level, i.e. low. rts ou tput pin is automatically controlled in this mode the level changes are detected on the ri, dsr, dcd and cts pins. if an input change is detected, the riic, dsric, dcdic and ctsic bi ts in the channel status register (us_csr) are set respectively and can trigger an interrupt. the status is automatically cleared when us_csr is read. furthermore, the cts automatically disables the transmitter when it is detected at its inactive state. if a character is being transmitted when the cts rises, the charac- ter transmission is completed before the transmitter is actually disabled. table 34-11. circuit references usart pin v24 ccitt direction txd 2 103 from terminal to modem rts 4 105 from terminal to modem dtr 20 108.2 from terminal to modem rxd 3 104 from modem to terminal cts 5 106 from terminal to modem dsr 6 107 from terminal to modem dcd 8 109 from terminal to modem ri 22 125 from terminal to modem
527 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.6.8 test modes the usart can be programmed to operate in three different test modes. the internal loopback capability allows on-boar d diagnostics. in the loopback mode the usart interface pins are dis- connected or not and reconfigured for loopback internally or externally. 34.6.8.1 normal mode normal mode connects the rxd pin on the receiver input and the transmitter output on the txd pin. figure 34-38. normal mode configuration 34.6.8.2 automatic echo mode automatic echo mode allows bit-by-bit retransmission. when a bit is received on the rxd pin, it is sent to the txd pin, as shown in figure 34-39 . programming the transmitter has no effect on the txd pin. the rxd pin is still connected to the receiver input, thus the receiver remains active. figure 34-39. automatic echo mode configuration 34.6.8.3 local loopback mode local loopback mode c onnects the output of the transmitter directly to the input of the receiver, as shown in figure 34-40 . the txd and rxd pins are not used. the rxd pin has no effect on the receiver and the txd pin is continuously driven high, as in idle state. figure 34-40. local loopback mode configuration receiver transmitter rxd txd receiver transmitter rxd txd receiver transmitter rxd txd 1
528 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.6.8.4 remote loopback mode remote loopback mode directly connects the rxd pin to the txd pin, as shown in figure 34-41 . the transmitter and the receiver are disabled an d have no effect. this mode allows bit-by-bit retransmission. figure 34-41. remote loopback mode configuration receiver transmitter rxd txd 1
529 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.7 universal synchronous async hronous recevier transeive r (usart) u ser interface table 34-13. register mapping offset register name access reset 0x0000 control register us_cr write-only ? 0x0004 mode register us_mr read-write ? 0x0008 interrupt enable register us_ier write-only ? 0x000c interrupt disable register us_idr write-only ? 0x0010 interrupt mask register us_imr read-only 0x0 0x0014 channel status register us_csr read-only ? 0x0018 receiver holding register us_rhr read-only 0x0 0x001c transmitter holding register us_thr write-only ? 0x0020 baud rate generator register us_brgr read-write 0x0 0x0024 receiver time-out register us_rtor read-write 0x0 0x0028 transmitter timeguard register us_ttgr read-write 0x0 0x2c - 0x3c reserved ? ? ? 0x0040 fi di ratio regist er us_fidi read-write 0x174 0x0044 number of errors register us_ner read-only ? 0x0048 reserved ? ? ? 0x004c irda filter regi ster us_if read-write 0x0 0x0050 manchester encoder decoder register us_man read-write 0x30011004 0x5c - 0xfc reserved ? ? ? 0x100 - 0x128 reserved for pdc registers ? ? ?
530 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.7.1 usart control register name: us_cr addresses: 0xfffb0000 (0), 0xfffb4000 (1), 0xfffb8000 (2), 0xfffd0000 (3), 0xfffd4000 (4) access type: write-only ? rstrx: reset receiver 0: no effect. 1: resets the receiver. ? rsttx: reset transmitter 0: no effect. 1: resets the transmitter. ? rxen: receiver enable 0: no effect. 1: enables the receiver, if rxdis is 0. ? rxdis: receiver disable 0: no effect. 1: disables the receiver. ? txen: transmitter enable 0: no effect. 1: enables the transmitter if txdis is 0. ? txdis: transmitter disable 0: no effect. 1: disables the transmitter. ? rststa: reset status bits 0: no effect. 1: resets the status bits pare, frame, ovre, manerr and rxbrk in us_csr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????rtsdisrtsendtrdisdtren 15 14 13 12 11 10 9 8 retto rstnack rstit senda sttto stpbrk sttbrk rststa 76543210 txdis txen rxdis rxen rsttx rstrx ? ?
531 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? sttbrk: start break 0: no effect. 1: starts transmission of a break after the characters present in us_thr and the transmit shi ft register have been trans- mitted. no effect if a break is already being transmitted. ? stpbrk: stop break 0: no effect. 1: stops transmission of the break after a minimum of one char acter length and transmits a high level during 12-bit periods. no effect if no break is being transmitted. ? sttto: start time-out 0: no effect. 1: starts waiting for a character before clocking the time-out counter. resets the status bit timeout in us_csr. ? senda: send address 0: no effect. 1: in multidrop mode only, the next character written to the us_thr is sent with the address bit set. ? rstit: reset iterations 0: no effect. 1: resets iteration in us_csr. no e ffect if the iso7816 is not enabled. ? rstnack: reset non acknowledge 0: no effect 1: resets nack in us_csr. ? retto: rearm time-out 0: no effect 1: restart time-out ? dtren: data terminal ready enable 0: no effect. 1: drives the pin dtr at 0. ? dtrdis: data terminal ready disable 0: no effect. 1: drives the pin dtr to 1. ? rtsen: request to send enable 0: no effect. 1: drives the pin rts to 0. ? rtsdis: request to send disable 0: no effect. 1: drives the pin rts to 1.
532 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.7.2 usart mode register name: us_mr addresses: 0xfffb0004 (0), 0xfffb4004 (1), 0xfffb8004 (2), 0xfffd0004 (3), 0xfffd4004 (4) access type: read-write ? usart_mode ? usclks: clock selection 31 30 29 28 27 26 25 24 onebit modsync? man filter ? max_iteration 23 22 21 20 19 18 17 16 ? var_sync dsnack inack over clko mode9 msbf 15 14 13 12 11 10 9 8 chmode nbstop par sync 76543210 chrl usclks usart_mode usart_mode mode of the usart 0000normal 0001rs485 0 0 1 0 hardware handshaking 0011modem 0 1 0 0 is07816 protocol: t = 0 0 1 1 0 is07816 protocol: t = 1 1000irda others reserved usclks selected clock 00mck 0 1 mck/div (div = 8 ) 10reserved 11sck
533 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? chrl: character length. ? sync: synchronous mode select 0: usart operates in asynchronous mode. 1: usart operates in synchronous mode. ? par: parity type ? nbstop: number of stop bits ? chmode: channel mode ? msbf: bit order 0: least significant bit is sent/received first. 1: most significant bit is sent/received first. chrl character length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits par parity type 0 0 0 even parity 001odd parity 0 1 0 parity forced to 0 (space) 0 1 1 parity forced to 1 (mark) 1 0 x no parity 1 1 x multidrop mode nbstop asynchronous (sync = 0) synchronous (sync = 1) 0 0 1 stop bit 1 stop bit 0 1 1.5 stop bits reserved 1 0 2 stop bits 2 stop bits 1 1 reserved reserved chmode mode description 0 0 normal mode 0 1 automatic echo. receiver input is connected to the txd pin. 1 0 local loopback. transmitter output is connected to the receiver input.. 1 1 remote loopback. rxd pin is internally connected to the txd pin.
534 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? mode9: 9-bit character length 0: chrl defines character length. 1: 9-bit character length. ? clko: clock output select 0: the usart does not drive the sck pin. 1: the usart drives the sck pin if usclks does not select the external clock sck. ? over: oversampling mode 0: 16x oversampling. 1: 8x oversampling. ? inack: inhibit non acknowledge 0: the nack is generated. 1: the nack is not generated. ? dsnack: disable successive nack 0: nack is sent on the iso line as soon as a parity erro r occurs in the received character (unless inack is set). 1: successive parity errors are counted up to the value spec ified in the max_iteration field. these parity errors gener- ate a nack on the iso line. as soon as this value is r eached, no additional nack is sent on the iso line. the flag iteration is asserted. ? var_sync: variable synchronization of command/data sync start frame delimiter 0: user defined configuration of command or data sync field depending on sync value. 1: the sync field is updated when a char acter is written into us_thr register. ? max_iteration defines the maximum number of iterations in mode iso7816, protocol t= 0. ? filter: infrared receive line filter 0: the usart does not filter the receive line. 1: the usart filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority). ? man: manchester encoder/decoder enable 0: manchester encoder/decoder are disabled. 1: manchester encoder/decoder are enabled. ? modsync : manchester synchronization mode 0:the manchester start bit is a 0 to 1 transition 1: the manchester start bit is a 1 to 0 transition. ? onebit: start frame delimiter selector 0: start frame delimiter is command or data sync. 1: start frame delimiter is one bit.
535 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.7.3 usart interrupt enable register name: us_ier addresses: 0xfffb0008 (0), 0xfffb4008 (1), 0xfffb8008 (2), 0xfffd0008 (3), 0xfffd4008 (4) access type: write-only ? rxrdy: rxrdy interrupt enable ? txrdy: txrdy interrupt enable ? rxbrk: receiver break interrupt enable ? endrx: end of receive transfer interrupt enable ? endtx: end of transmit interrupt enable ? ovre: overrun error interrupt enable ? frame: framing error interrupt enable ? pare: parity error interrupt enable ? timeout: time-out interrupt enable ? txempty: txempty interrupt enable ? iter: iteration interrupt enable ? txbufe: buffer empty interrupt enable ? rxbuff: buffer full interrupt enable ? nack: non acknowledge interrupt enable ? riic: ring indicator input change enable ? dsric: data set ready input change enable ? dcdic: data carrier detect input change interrupt enable ? ctsic: clear to send input change interrupt enable ? mane: manchester error interrupt enable 31 30 29 28 27 26 25 24 ???????mane 23 22 21 20 19 18 17 16 ? ? ? mane ctsic dcdic dsric riic 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iter txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
536 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.7.4 usart interrupt disable register name: us_idr addresses: 0xfffb000c (0), 0xfffb400c (1), 0xfffb 800c (2), 0xfffd000c (3), 0xfffd400c (4) access type: write-only ? rxrdy: rxrdy interrupt disable ? txrdy: txrdy interrupt disable ? rxbrk: receiver bre ak interrupt disable ? endrx: end of receive transfer interrupt disable ? endtx: end of transmit interrupt disable ? ovre: overrun error interrupt disable ? frame: framing error interrupt disable ? pare: parity error interrupt disable ? timeout: time-out interrupt disable ? txempty: txempty interrupt disable ? iter: iteration interrupt enable ? txbufe: buffer empty interrupt disable ? rxbuff: buffer full interrupt disable ? nack: non acknowledge interrupt disable ? riic: ring indicator input change disable ? dsric: data set ready input change disable ? dcdic: data carrier detect input change interrupt disable ? ctsic: clear to send input change interrupt disable ? mane: manchester error interrupt disable 31 30 29 28 27 26 25 24 ???????mane 23 22 21 20 19 18 17 16 ? ? ? mane ctsic dcdic dsric riic 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iter txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
537 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.7.5 usart interrupt mask register name: us_imr addresses: 0xfffb0010 (0), 0xfffb4010 (1), 0xfffb8010 (2), 0xfffd0010 (3), 0xfffd4010 (4) access type: read-only ? rxrdy: rxrdy interrupt mask ? txrdy: txrdy interrupt mask ? rxbrk: receiver break interrupt mask ? endrx: end of receive transfer interrupt mask ? endtx: end of transmit interrupt mask ? ovre: overrun error interrupt mask ? frame: framing error interrupt mask ? pare: parity error interrupt mask ? timeout: time-out interrupt mask ? txempty: txempty interrupt mask ? iter: iteration interrupt enable ? txbufe: buffer empty interrupt mask ? rxbuff: buffer full interrupt mask ? nack: non acknowledge interrupt mask ? riic: ring indicator input change mask ? dsric: data set ready input change mask ? dcdic: data carrier detect input change interrupt mask ? ctsic: clear to send input change interrupt mask ? mane: manchester error interrupt mask 31 30 29 28 27 26 25 24 ???????mane 23 22 21 20 19 18 17 16 ? ? ? mane ctsic dcdic dsric riic 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iter txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
538 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.7.6 usart channel status register name: us_csr addresses: 0xfffb0014 (0), 0xfffb4014 (1), 0xfffb8014 (2), 0xfffd0014 (3), 0xfffd4014 (4) access type: read-only ? rxrdy: receiver ready 0: no complete character has been received since the last read of us_rhr or the receiver is disabled. if characters were being received when the receiver was disabled, rx rdy changes to 1 when the receiver is enabled. 1: at least one complete char acter has been rece ived and us_rhr has not yet been read. ? txrdy: transmitter ready 0: a character is in the us_thr waiting to be transferred to the transmit shift register, or an sttbrk command has been requested, or the transmitter is disabled. as soon as the transmitter is enabled, txrdy becomes 1. 1: there is no char acter in the us_thr. ? rxbrk: break received/end of break 0: no break received or end of break detected since the last rststa. 1: break received or end of break detected since the last rststa. ? endrx: end of receiver transfer 0: the end of transfer signal from the receive pdc channel is inactive. 1: the end of transfer signal from the receive pdc channel is active. ? endtx: end of transmitter transfer 0: the end of transfer signal from the transmit pdc channel is inactive. 1: the end of transfer signal from the transmit pdc channel is active. ? ovre: overrun error 0: no overrun error has occurred since the last rststa. 1: at least one overrun error has occurred since the last rststa. ? frame: framing error 0: no stop bit has been detected low since the last rststa. 1: at least one stop bit has been detected low since the last rststa. 31 30 29 28 27 26 25 24 ???????manerr 23 22 21 20 19 18 17 16 cts dcd dsr ri ctsic dcdic dsric riic 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iter txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
539 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? pare: parity error 0: no parity error has been detected since the last rststa. 1: at least one parity error has been detected since the last rststa. ? timeout: receiver time-out 0: there has not been a time-out since t he last start time-out command (sttto in us_cr) or the time-out register is 0. 1: there has been a time-out since the last start time-out command (sttto in us_cr). ? txempty: transmitter empty 0: there are characters in either us_thr or the tr ansmit shift register, or the transmitter is disabled. 1: there are no characters in us_thr, nor in the transmit shift register. ? iter: max number of repetitions reached 0: maximum number of repetitions has not been reached since the last rststa. 1: maximum number of repetitions has been reached since the last rststa. ? txbufe: transmission buffer empty 0: the signal buffer empty from the transmit pdc channel is inactive. 1: the signal buffer empty from the transmit pdc channel is active. ? rxbuff: reception buffer full 0: the signal buffer full from the receive pdc channel is inactive. 1: the signal buffer full from th e receive pdc channel is active. ? nack: non acknowledge 0: no non acknowledge has not been detected since the last rstnack. 1: at least one non acknowledge has been detected since the last rstnack. ? riic: ring indicator input change flag 0: no input change has been detected on the ri pin since the last read of us_csr. 1: at least one input change has been detected on the ri pin since the last read of us_csr. ? dsric: data set ready input change flag 0: no input change has been detected on the dsr pin since the last read of us_csr. 1: at least one input change has been detected on the dsr pin since the last read of us_csr. ? dcdic: data carrier detect input change flag 0: no input change has been detected on the dcd pin since the last read of us_csr. 1: at least one input change has been detected on the dcd pin since the last read of us_csr. ? ctsic: clear to send input change flag 0: no input change has been detected on the cts pin since the last read of us_csr. 1: at least one input change has been detected on the cts pin since the last read of us_csr. ? ri: image of ri input 0: ri is at 0. 1: ri is at 1.
540 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? dsr: image of dsr input 0: dsr is at 0 1: dsr is at 1. ? dcd: image of dcd input 0: dcd is at 0. 1: dcd is at 1. ? cts: image of cts input 0: cts is at 0. 1: cts is at 1. ? manerr: manchester error 0: no manchester error has been detected since the last rststa. 1: at least one manchester error has been detected since the last rststa.
541 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.7.7 usart receive holding register name: us_rhr addresses: 0xfffb0018 (0), 0xfffb4018 (1), 0xfffb8018 (2), 0xfffd0018 (3), 0xfffd4018 (4) access type: read-only ? rxchr: received character last character received if rxrdy is set. ? rxsynh: received sync 0: last character received is a data. 1: last character received is a command. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rxsynh ??????rxchr 76543210 rxchr
542 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.7.8 usart transmit holding register name: us_thr addresses: 0xfffb001c (0), 0xfffb401c (1), 0xfffb 801c (2), 0xfffd001c (3), 0xfffd401c (4) access type: write-only ? txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. ? txsynh: sync field to be transmitted 0: the next character sent is encoded as a data. start frame delimiter is data sync. 1: the next character sent is encoded as a command. start frame delimiter is command sync. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 txsynh ??????txchr 76543210 txchr
543 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.7.9 usart baud rate generator register name: us_brgr addresses: 0xfffb0020 (0), 0xfffb4020 (1), 0xfffb8020 (2), 0xfffd0020 (3), 0xfffd4020 (4) access type: read-write ? cd: clock divider ? fp: fractional part 0: fractional divider is disabled. 1 - 7: baudrate resolution, defined by fp x 1/8. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????? fp? 15 14 13 12 11 10 9 8 cd 76543210 cd cd usart_mode iso7816 usart_mode = iso7816 sync = 0 sync = 1 over = 0 over = 1 0 baud rate clock disabled 1 to 65535 baud rate = selected clock/16/cd baud rate = selected clock/8/cd baud rate = selected clock /cd baud rate = selected clock/cd/fi_di_ratio
544 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.7.10 usart receiver time-out register name: us_rtor addresses: 0xfffb0024 (0), 0xfffb4024 (1), 0xfffb8024 (2), 0xfffd0024 (3), 0xfffd4024 (4) access type: read-write ? to: time-out value 0: the receiver time-out is disabled. 1 - 65535: the receiver time-out is enabled and the time-out delay is to x bit period. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 to 76543210 to
545 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.7.11 usart transmitter timeguard register name: us_ttgr addresses: 0xfffb0028 (0), 0xfffb4028 (1), 0xfffb8028 (2), 0xfffd0028 (3), 0xfffd4028 (4) access type: read-write ? tg: timeguard value 0: the transmitter timeguard is disabled. 1 - 255: the transmitter timeguard is enabled and the timeguard delay is tg x bit period. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 tg
546 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.7.12 usart fi di ratio register name: us_fidi addresses: 0xfffb0040 (0), 0xfffb4040 (1), 0xfffb8040 (2), 0xfffd0040 (3), 0xfffd4040 (4) access type: read-write reset value: 0x174 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????? fi_di_ratio 76543210 fi_di_ratio
547 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? fi_di_ratio: fi over di ratio value 0: if iso7816 mode is selected, the baud rate generator generates no signal. 1 - 2047: if iso7816 mode is selected, the baud rate is the clock provided on sck divided by fi_di_ratio. 34.7.13 usart number of errors register name: us_ner addresses: 0xfffb0044 (0), 0xfffb4044 (1), 0xfffb8044 (2), 0xfffd0044 (3), 0xfffd4044 (4) access type: read-only ? nb_errors: number of errors total number of errors that occurred during an iso7816 transfer. this register automatically clears when read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 nb_errors
548 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.7.14 usart irda filter register name: us_if addresses: 0xfffb004c (0), 0xfffb404c (1), 0xfffb 804c (2), 0xfffd004c (3), 0xfffd404c (4) access type: read-write ? irda_filter: irda filter sets the filter of the irda demodulator. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 irda_filter
549 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 34.7.15 usart manchester configuration register name: us_man access type: read-write ? tx_pl: transmitter preamble length 0: the transmitter preamble pattern generation is disabled 1 - 15: the preamble length is tx_pl x bit period ? tx_pp: transmitter preamble pattern ? tx_mpol: transmitter manchester polarity 0: logic zero is coded as a zero-to-one transition , logic one is coded as a one-to-zero transition. 1: logic zero is coded as a one-to-zero transition , logic one is coded as a zero-to-one transition. ? rx_pl: receiver preamble length 0: the receiver preamble pattern detection is disabled 1 - 15: the detected preamble length is rx_pl x bit period ? rx_pp: receiver preamble pattern detected 31 30 29 28 27 26 25 24 ? drift 1 rx_mpol ? ? rx_pp 23 22 21 20 19 18 17 16 ???? rx_pl 15 14 13 12 11 10 9 8 ? ? ? tx_mpol ? ? tx_pp 76543210 ???? tx_pl tx_pp preamble pattern default polari ty assumed (tx_mpol field not set) 0 0 all_one 0 1 all_zero 10zero_one 11one_zero rx_pp preamble pattern de fault polarity assumed (rx_mpol fi eld not set) 0 0 all_one 0 1 all_zero 10zero_one 11one_zero
550 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? rx_mpol: receiver manchester polarity 0: logic zero is coded as a zero-to-one transition , logic one is coded as a one-to-zero transition. 1: logic zero is coded as a one-to-zero transition , logic one is coded as a zero-to-one transition. ? drift: drift compensation 0: the usart can not recover from an important clock drift 1: the usart can recover from clock drift. the 16x clock mode must be enabled.
551 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 35. synchronous serial controller (ssc) 35.1 description the atmel synchronous serial controller (ssc ) provides a synchronous communication link with external devices. it supports many serial synchronous communication protocols generally used in audio and telecom applications such as i2s, short frame sync, long frame sync, etc. the ssc contains an independent receiver and transmitter and a common clock divider. the receiver and the transmitter each interface with three signals: the td/rd signal for data, the tk/rk signal for the clock and the tf/rf signal for the frame sync. the transfers can be pro- grammed to start automatically or on different events detected on the frame sync signal. the ssc?s high-level of programmability and its two dedicated pdc channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention. featuring connection to two pdc channels, the ssc permits interfacing with low processor overhead to the following: ? codec?s in master or slave mode ? dac through dedicated serial interface, particularly i2s ? magnetic card reader
552 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 35.2 block diagram figure 35-1. block diagram 35.3 application block diagram figure 35-2. application block diagram ssc interface pio pdc apb bridge mck system bus peripheral bus tf tk td rf rk rd interrupt control ssc interrupt pmc interrupt management power management test management ssc serial audio os or rtos driver codec frame management line interface time slot management
553 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 35.4 pin name list 35.5 product dependencies 35.5.1 i/o lines the pins used for interfacing the compliant external devices may be multiplexed with pio lines. before using the ssc receiver, the pio contro ller must be configured to dedicate the ssc receiver i/o lines to the ssc peripheral mode. before using the ssc transmitter, the pio controller must be configured to dedicate the ssc transmitter i/o lines to the ssc peripheral mode. 35.5.2 power management the ssc is not continuously clocked. the ssc interface may be clocked through the power management controller (pmc), therefore the programmer must first configure the pmc to enable the ssc clock. 35.5.3 interrupt the ssc interface has an interrupt line connected to the advanced interrupt controller (aic). handling interrupts requires programming the aic before configuring the ssc. all ssc interrupts can be enabled/disabled configur ing the ssc interrupt mask register. each pending and unmasked ssc interrupt will assert the ssc interrupt line. the ssc interrupt ser- vice routine can get the interrupt origin by reading the ssc interrupt status register. 35.6 functional description this chapter contains the functional description of the following: ssc functional block, clock management, data format, start, transmitter, receiver and frame sync. the receiver and transmitter operate separately. however, they can work synchronously by pro- gramming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. the transmitter and the receiver can be pro- grammed to operate with the clock signals provided on either the tk or rk pins. this allows the ssc to support many slave-mode data transfer s. the maximum clock speed allowed on the tk and rk pins is the master clock divided by 2. table 35-1. i/o lines description pin name pin description type rf receiver frame synchro input/output rk receiver clock input/output rd receiver data input tf transmitter frame synchro input/output tk transmitter clock input/output td transmitter data output
554 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 35-3. ssc functional block diagram 35.6.1 clock management the transmitter clock can be generated by: ? an external clock received on the tk i/o pad ? the receiver clock ? the internal clock divider the receiver clock can be generated by: ? an external clock received on the rk i/o pad ? the transmitter clock ? the internal clock divider furthermore, the transmitter block can generate an external clock on the tk i/o pad, and the receiver block can generate an external clock on the rk i/o pad. this allows the ssc to support many master and slave mode data transfers. interrupt control aic user interface apb mck receive clock controller start selector tx clock rk input rf tf clock output controller frame sync controller transmit clock controller transmit shift register start selector transmit sync holding register transmit holding register load shift rx clock tx clock tk input tf tx pdc rf rd rf rk clock output controller frame sync controller receive shift register receive sync holding register receive holding register load shift td tf tk rx clock rx pdc receiver pdc transmitter clock divider
555 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 35.6.1.1 clock divider figure 35-4. divided clock block diagram the master clock divider is determined by the 12-bit field div counter and comparator (so its maximal value is 4095) in the clock mode register ssc_cmr, allowing a master clock division by up to 8190. the divided clock is provided to both the receiver and transmitter. when this field is programmed to 0, the clock divider is not used and remains inactive. when div is set to a value equal to or greater than 1, the divided clock has a frequency of mas- ter clock divided by 2 times div. each level of the divided clock has a duration of the master clock multiplied by div. this ensures a 50 % duty cycle for the divided clock regardless of whether the div value is even or odd. figure 35-5. divided clock generation 35.6.1.2 transmitter clock management the transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the tk i/o pad. the transm itter clock is selected by the cks field in ssc_tcmr (transmit clock mode register). transmit clock can be inverted independently by the cki bits in ssc_tcmr. table 35-2. maximum minimum mck / 2 mck / 8190 mck divided clock clock divider / 2 12-bit counter ssc_cmr master clock divided clock div = 1 master clock divided clock div = 3 divided clock frequency = mck/2 divided clock frequency = mck/6
556 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary the transmitter can also drive the tk i/o pad cont inuously or be limited to the actual data trans- fer. the clock output is configured by the ssc_tcmr register. the transmit clock inversion (cki) bits have no effect on the clock outputs. programming the tcmr register to select tk pin (cks field) and at the same time continuous transmit clock (cko field) might lead to unpredict- able results. figure 35-6. transmitter clock management 35.6.1.3 receiver clock management the receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the rk i/o pad. the receive clock is selected by the cks field in ssc_rcmr (receive clock mode register). receive clocks can be inverted independently by the cki bits in ssc_rcmr. the receiver can also drive the rk i/o pad continuo usly or be limited to the actual data transfer. the clock output is configured by the ssc_rcmr register. the receive clock inversion (cki) bits have no effect on the clock outputs. programming the rcmr register to select rk pin (cks field) and at the same time continuous receive clock (cko field) can lead to unpredictable results. tk (pin) receiver clock divider clock cks cko data transfer cki ckg transmitter clock clock output mux tri_state controller tri-state controller inv mux
557 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 35-7. receiver clock management 35.6.1.4 serial clock ratio considerations the transmitter and the receiver can be programmed to operate with the clock signals provided on either the tk or rk pins. this allows the ssc to support many slave-mode data transfers. in this case, the maximum clock speed allowed on the rk pin is: ? master clock divided by 2 if receiver frame synchro is input ? master clock divided by 3 if receiver frame synchro is output in addition, the maximum clock speed allowed on the tk pin is: ? master clock divided by 6 if transmit frame synchro is input ? master clock divided by 2 if transmit frame synchro is output 35.6.2 transmitter operations a transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. the start event is configured by setting the transmit clock mode register (ssc_tcmr). see ?start? on page 559. the frame synchronization is configured setting the transmit frame mode register (ssc_tfmr). see ?frame sync? on page 561. to transmit data, the transmitter uses a shift re gister clocked by the transmitter clock signal and the start mode selected in the ssc_tcmr. data is written by the application to the ssc_thr register then transferred to the shift register according to the data format selected. when both the ssc_thr and the transmit shift register are empty, the status flag txempty is set in ssc_sr. when the transmit holding register is transferred in the transmit shift register, the status flag txrdy is set in ssc_sr and additional data can be loaded in the holding register. rk (pin) transmitter clock divider clock cks cko data transfer cki ckg receiver clock clock output mux tri-state controller tri-state controller inv mux
558 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 35-8. transmitter block diagram 35.6.3 receiver operations a received frame is triggered by a start event and can be followed by synchronization data before data transmission. the start event is configured setting the receive clock mode register (ssc_rcmr). see ?start? on page 559. the frame synchronization is configured setting the receive frame mode register (ssc_rfmr). see ?frame sync? on page 561. the receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the ssc_rcmr. the data is transferred from the shift register depending on the data format selected. when the receiver shift register is full, the ssc transfers this data in the holding register, the sta- tus flag rxrdy is set in ssc_sr and the data c an be read in the receiver holding register. if another transfer occurs before read of the rhr register, the status flag overun is set in ssc_sr and the receiver shift register is transferred in the rhr register. transmit shift register start selector ssc_tshr ssc_thr transmitter clock td ssc_tfmr.fslen ssc_tfmr.datlen ssc_cr.txen ssc_cr.txdis ssc_tcmr.sttdly ssc_tfmr.fsden ssc_tfmr.datnb ssc_sr.txen ssc_tfmr.datdef ssc_tfmr.msbf ssc_tcmr.sttdly ssc_tfmr.fsden 0 1 1 0 rf tf
559 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 35-9. receiver block diagram 35.6.4 start the transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the transmit start sele ction (start) field of ssc_tcmr and in the receive start selection (start) field of ssc_rcmr. under the following conditions the start event is independently programmable: ? continuous. in this case, the transmission st arts as soon as a word is written in ssc_thr and the reception starts as soon as the receiver is enabled. ? synchronously with the transmitter/receiver ? on detection of a falling/rising edge on tf/rf ? on detection of a low level/high level on tf/rf ? on detection of a level change or an edge on tf/rf a start can be programmed in the same manner on either side of the transmit/receive clock register (rcmr/tcmr). thus, the start coul d be on tf (transmit) or rf (receive). moreover, the receiver can start when data is detected in the bit stream with the compare functions. detection on tf/rf input/output is done by the field fsos of the transmit/receive frame mode register (tfmr/rfmr). receive shift register start selector ssc_rhr ssc_rshr receiver clock rd ssc_rfmr.fslen ssc_rfmr.datlen rf ssc_cr.rxen ssc_cr.rxdis ssc_sr.rxen ssc_rfmr.msbf ssc_rcmr.sttdly ssc_rfmr.datnb tf
560 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 35-10. transmit start mode figure 35-11. receive pulse/ed ge start modes x tk tf (input) td (output) td (output) td (output) td (output) td (output) td (output) xbob1 x bo b1 bo b1 bo b1 bo b1 bo b1 bo b1 b1 bo x x x sttdly sttdly sttdly sttdly sttdly sttdly start = falling edge on tf start = rising edge on tf start = low level on tf start = high level on tf start = any edge on tf start = level change on tf x rk rf (input) rd (input) rd (input) rd (input) rd (input) rd (input) rd (input) xbob1 x bo b1 bo b1 bo b1 bo b1 bo b1 bo b1 b1 bo x x x sttdly sttdly sttdly sttdly sttdly sttdly start = falling edge on rf start = rising edge on rf start = low level on rf start = high level on rf start = any edge on rf start = level change on rf
561 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 35.6.5 frame sync the transmitter and receiver frame sync pins, tf and rf, can be programmed to generate different kinds of frame synchron ization signals. the frame sync output selection (fsos) field in the receive frame mode register (ssc_rfmr) and in the transmit frame mode register (ssc_tfmr) are used to select the required waveform. ? programmable low or high levels during data transfer are supported. ? programmable high levels before the start of data transfers or toggling are also supported. if a pulse waveform is selected, the frame sync length (fslen) field in ssc_rfmr and ssc_tfmr programs the length of the pulse, from 1 bit time up to 16 bit time. the periodicity of the receive and transmit frame sync pulse output can be programmed through the period divider selection ( period) field in ssc_rcmr and ssc_tcmr. 35.6.5.1 frame sync data frame sync data transmits or receives a specific tag during the frame sync signal. during the frame sync signal, the receiver can sample the rd line and store the data in the receive sync holding register and the transmitter can transfer transmit sync holding register in the shifter register. the data length to be sampled/shifted out during the frame sync signal is programmed by the fslen field in ssc_rfmr/ssc_tfmr and has a maximum value of 16. concerning the receive frame sync data operation, if the frame sync length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the re ceive sync holding register thr ough the receive shift register. the transmit frame sync operation is performed by the transmitter only if the bit frame sync data enable (fsden) in ssc_tfmr is set. if the frame sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the transmit sync holding register is transferred in the trans- mit register, then shifted out. 35.6.5.2 frame sync edge detection the frame sync edge detection is programmed by the fsedge field in ssc_rfmr/ssc_tfmr. this sets the corres ponding flags rxsyn/txsyn in the ssc status register (ssc_sr) on frame synchro edge detection (signals rf/tf). 35.6.6 receive compare modes figure 35-12. receive compare modes cmp0 cmp3 cmp2 cmp1 ignored b0 b2 b1 start rk rd (input) fslen up to 16 bits (4 in this example) stdly datlen
562 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 35.6.6.1 compare functions length of the comparison patterns (compare 0, compare 1) and thus the number of bits they are compared to is defined by fslen, but with a maximum value of 16 bits. comparison is always done by comparing the last bits received with the comparison pattern. compare 0 can be one start event of the receiver. in this case, the receiver compares at each new sample the last bits received at the compare 0 pattern contained in the compare 0 register (ssc_rc0r). when this start event is selected, the user can program the receiver to start a new data transfer either by writing a new compare 0, or by receiving continuously until compare 1 occurs. this selection is done with the bit (stop) in ssc_rcmr. 35.6.7 data format the data framing format of both the transmitter and the receiver are programmable through the transmitter frame mode register (ssc_tfmr) and the receiver frame mode register (ssc_rfmr). in either case, the user can independently select: ? the event that starts the data transfer (start) ? the delay in number of bit periods between the start event and the first data bit (sttdly) ? the length of the data (datlen) ? the number of data to be transferred for each start event (datnb). ? the length of synchronization transferred for each start event (fslen) ? the bit sense: most or lowest significant bit first (msbf) additionally, the transmitter can be used to tr ansfer synchronization and select the level driven on the td pin while not in data transfer operation. this is done respectively by the frame sync data enable (fsden) and by the data default value (datdef) bits in ssc_tfmr. table 35-3. data frame registers transmitter receiver field length comment ssc_tfmr ssc_rfmr datlen up to 32 size of word ssc_tfmr ssc_rfmr datnb up to 16 number of words transmitted in frame ssc_tfmr ssc_rfmr msbf most significant bit first ssc_tfmr ssc_rfmr fslen up to 16 size of synchro data register ssc_tfmr datdef 0 or 1 data default value ended ssc_tfmr fsden enable send ssc_tshr ssc_tcmr ssc_rcmr period up to 512 frame size ssc_tcmr ssc_rcmr sttdly up to 255 size of transmit start delay
563 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 35-13. transmit and receive frame format in edge/pulse start modes note: 1. example of input on falling edge of tf/rf. figure 35-14. transmit frame format in continuous mode note: 1. sttdly is set to 0. in this example, ssc_thr is loaded twice. fsden value has no effect on the transmission. syncdata cannot be output in continuous mode. figure 35-15. receive frame format in continuous mode note: 1. sttdly is set to 0. sync data default sttdly sync data ignored rd default data datlen data data data datlen data data default default ignored sync data sync data fslen tf/rf (1) start start from ssc_tshr from ssc_thr from ssc_thr from ssc_thr from ssc_thr to ssc_rhr to ssc_rhr to ssc_rshr td (if fsden = 0) td (if fsden = 1) datnb period fromdatdef fromdatdef from datdef from datdef datlen data datlen data default start from ssc_thr from ssc_thr td start: 1. txempty set to 1 2. write into the ssc_thr data datlen data datlen start = enable receiver to ssc_rhr to ssc_rhr rd
564 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 35.6.8 loop mode the receiver can be programmed to receive transmissions from the transmitter. this is done by setting the loop mode (loop) bit in ssc_rfmr. in this case, rd is connected to td, rf is connected to tf and rk is connected to tk. 35.6.9 interrupt most bits in ssc_sr have a corresponding bit in interrupt management registers. the ssc can be programmed to generate an interrupt when it detects an event. the interrupt is controlled by writing ssc_ier (interrupt enable register) and ssc_idr (interrupt disable reg- ister) these registers enable and disable, respectively, the corresponding interrupt by setting and clearing the corresponding bit in ssc_imr (interrupt mask register), which controls the generation of interrupts by asserting the ssc interrupt line connected to the aic. figure 35-16. interrupt block diagram 35.7 ssc application examples the ssc can support several serial communica tion modes used in audio or high speed serial links. some standard applications are shown in t he following figures. all se rial link applications supported by the ssc are not listed here. ssc_imr pdc interrupt control ssc interrupt set rxrdy ovrun rxsync receiver transmitter txrdy txempty txsync txbufe endtx rxbuff endrx clear ssc_ier ssc_idr
565 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 35-17. audio application block diagram figure 35-18. codec application block diagram ssc rk rf rd td tf tk clock sck word select ws data sd i2s receiver clock sck word select ws data sd right channel left channel msb msb lsb ssc rk rf rd td tf tk serial data clock (sclk) frame sync (fsync) serial data out serial data in codec serial data clock (sclk) frame sync (fsync) serial data out serial data in first time slot dstart dend
566 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 35-19. time slot application block diagram ssc rk rf rd td tf tk sclk fsync data out data in codec first time slot serial data clock (sclk) frame sync (fsync) serial data out serial data in codec second time slot first time slot second time slot dstart dend
567 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 35.8 synchronous serial contro ller (ssc) user interface table 35-4. register mapping offset register name access reset 0x0 control register ssc_cr write-only ? 0x4 clock mode register ssc_cmr read-write 0x0 0x8 reserved ? ? ? 0xc reserved ? ? ? 0x10 receive clock mode register ssc_rcmr read-write 0x0 0x14 receive frame mode register ssc_rfmr read-write 0x0 0x18 transmit clock mode register ssc_tcmr read-write 0x0 0x1c transmit frame mode register ssc_tfmr read-write 0x0 0x20 receive holding register ssc_rhr read-only 0x0 0x24 transmit holding register ssc_thr write-only ? 0x28 reserved ? ? ? 0x2c reserved ? ? ? 0x30 receive sync. holding register ssc_rshr read-only 0x0 0x34 transmit sync. holding register ssc_tshr read-write 0x0 0x38 receive compare 0 register ssc_rc0r read-write 0x0 0x3c receive compare 1 register ssc_rc1r read-write 0x0 0x40 status register ssc_sr read-only 0x000000cc 0x44 interrupt enable register ssc_ier write-only ? 0x48 interrupt disable register ssc_idr write-only ? 0x4c interrupt mask register ssc_imr read-only 0x0 0x50-0xfc reserved ? ? ? 0x100- 0x124 reserved for peripheral data controller (pdc) ? ? ?
568 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 35.8.1 ssc control register name: ssc_cr address: 0xfffbc000 access type: write-only ? rxen: receive enable 0 = no effect. 1 = enables receive if rxdis is not set. ? rxdis: receive disable 0 = no effect. 1 = disables receive. if a character is currently being re ceived, disables at end of current character reception. ? txen: transmit enable 0 = no effect. 1 = enables transmit if txdis is not set. ? txdis: transmit disable 0 = no effect. 1 = disables transmit. if a character is currently being trans mitted, disables at end of current character transmission. ? swrst: software reset 0 = no effect. 1 = performs a software reset. has priority on any other bit in ssc_cr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 swrst?????txdistxen 76543210 ??????rxdisrxen
569 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 35.8.2 ssc clock mode register name: ssc_cmr address: 0xfffbc004 access type: read-write ? div: clock divider 0 = the clock divider is not active. any other value: the divided clock equals the master clock divided by 2 times div. the maximum bit rate is mck/2. the minimum bit rate is mck/2 x 4095 = mck/8190. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???? div 76543210 div
570 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 35.8.3 ssc receive clock mode register name: ssc_rcmr address: 0xfffbc010 access type: read-write ? cks: receive clock selection ? cko: receive clock output mode selection ? cki: receive clock inversion 0 = the data inputs (data and frame sync signals) are sampled on receive clock falling edge. the frame sync signal output is shifted out on receive clock rising edge. 1 = the data inputs (data and frame sync signals) are samp led on receive clock rising edge. the frame sync signal out- put is shifted out on receive clock falling edge. cki affects only the receive clock and not the output clock signal. 31 30 29 28 27 26 25 24 period 23 22 21 20 19 18 17 16 sttdly 15 14 13 12 11 10 9 8 ? ? ? stop start 76543210 ckg cki cko cks cks selected receive clock 0x0 divided clock 0x1 tk clock signal 0x2 rk pin 0x3 reserved cko receive clock output mode rk pin 0x0 none input-only 0x1 continuous receive clock output 0x2 receive clock only during data transfers output 0x3-0x7 reserved
571 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? ckg: receive clock gating selection ? start: receive start selection ? stop: receive stop selection 0 = after completion of a data transfer when starting with a compare 0, the receiver stops the data transfer and waits for a new compare 0. 1 = after starting a receive with a compare 0, the receiver operates in a continuous mode until a compare 1 is detected. ? sttdly: receive start delay if sttdly is not 0, a delay of sttdly clock cycles is inserted between the start event and the actual start of reception. when the receiver is programmed to start synchronously with the transmitter, the delay is also applied. note: it is very important that sttdly be set carefully. if sttdly must be set, it should be done in relation to tag (receive sync data) reception. ? period: receive period divider selection this field selects the divider to apply to the selected receive clock in order to generate a new frame sync signal. if 0, no period signal is generated. if not 0, a period sig nal is generated each 2 x (period+1) receive clock. ckg receive clock gating 0x0 none, continuous clock 0x1 receive clock enabled only if rf low 0x2 receive clock enabled only if rf high 0x3 reserved start receive start 0x0 continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 0x1 transmit start 0x2 detection of a low level on rf signal 0x3 detection of a high level on rf signal 0x4 detection of a falling edge on rf signal 0x5 detection of a rising edge on rf signal 0x6 detection of any level change on rf signal 0x7 detection of any edge on rf signal 0x8 compare 0 0x9-0xf reserved
572 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 35.8.4 ssc receive frame mode register name: ssc_rfmr address: 0xfffbc014 access type: read-write ? datlen: data length 0 = forbidden value (1-bit data length not supported). any other value: the bit stream contains datlen + 1 data bits. moreover, it defines the transfer size performed by the pdc2 assigned to the receiver. if datlen is lower or equal to 7, data transfers are in bytes. if datlen is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. ? loop: loop mode 0 = normal operating mode. 1 = rd is driven by td, rf is driven by tf and tk drives rk. ? msbf: most significant bit first 0 = the lowest significant bit of the data register is sampled first in the bit stream. 1 = the most significant bit of the data register is sampled first in the bit stream. ? datnb: data number per frame this field defines the number of data words to be received after each transfer start, which is equal to (datnb + 1). ? fslen: receive frame sync length this field defines the number of bits sampled and stored in the receive sync data register. when this mode is selected by the start field in the receive clock mode register, it also determines the length of the sampled data to be compared to the compare 0 or compare 1 register. 31 30 29 28 27 26 25 24 ??? ? ???fsedge 23 22 21 20 19 18 17 16 ? fsos fslen 15 14 13 12 11 10 9 8 ??? ? datnb 765 4 3210 msbf ? loop datlen
573 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? fsos: receive frame sync output selection ? fsedge: frame sync edge detection determines which edge on frame sy nc will generate the in terrupt rxsyn in the ssc status register. fsos selected receive frame sync signal rf pin 0x0 none input-only 0x1 negative pulse output 0x2 positive pulse output 0x3 driven low during data transfer output 0x4 driven high during data transfer output 0x5 toggling at each start of data transfer output 0x6-0x7 reserved undefined fsedge frame sync edge detection 0x0 positive edge detection 0x1 negative edge detection
574 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 35.8.5 ssc transmit clock mode register name: ssc_tcmr address: 0xfffbc018 access type: read-write ? cks: transmit clock selection ? cko: transmit clock output mode selection ? cki: transmit clock inversion 0 = the data outputs (data and frame sync signals) are shi fted out on transmit clock falling edge. the frame sync signal input is sampled on transmit clock rising edge. 1 = the data outputs (data and frame sync signals) are shifte d out on transmit clock rising edge. the frame sync signal input is sampled on tran smit clock falling edge. cki affects only the transmit clock and not the output clock signal. 31 30 29 28 27 26 25 24 period 23 22 21 20 19 18 17 16 sttdly 15 14 13 12 11 10 9 8 ???? start 76543210 ckg cki cko cks cks selected transmit clock 0x0 divided clock 0x1 rk clock signal 0x2 tk pin 0x3 reserved cko transmit clock output mode tk pin 0x0 none input-only 0x1 continuous transmit clock output 0x2 transmit clock only during data transfers output 0x3-0x7 reserved
575 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? ckg: transmit clock gating selection ? start: transmit start selection ? sttdly: transmit start delay if sttdly is not 0, a delay of sttdly clock cycles is inse rted between the start event and the actual start of transmission of data. when the transmitter is programmed to start sync hronously with the receiver, the delay is also applied. note: sttdly must be set carefully. if sttdly is too short in respect to tag (transmit sync data) emission, data is emit- ted instead of the end of tag. ? period: transmit period divider selection this field selects the divider to apply to the selected transmi t clock to generate a new frame sync signal. if 0, no period signal is generated. if not 0, a period signal is generated at each 2 x (period+1) transmit clock. ckg transmit clock gating 0x0 none, continuous clock 0x1 transmit clock enabled only if tf low 0x2 transmit clock enabled only if tf high 0x3 reserved start transmit start 0x0 continuous, as soon as a word is written in the ssc_thr register (if transmit is enabled), and immediately after the end of transfer of the previous data. 0x1 receive start 0x2 detection of a low level on tf signal 0x3 detection of a high level on tf signal 0x4 detection of a falling edge on tf signal 0x5 detection of a rising edge on tf signal 0x6 detection of any level change on tf signal 0x7 detection of any edge on tf signal 0x8 - 0xf reserved
576 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 35.8.6 ssc transmit frame mode register name: ssc_tfmr address: 0xfffbc01c access type: read-write ? datlen: data length 0 = forbidden value (1-bit data length not supported). any other value: the bit stream contains datlen + 1 data bits. moreover, it defines the transfer size performed by the pdc2 assigned to the transmit. if datlen is lower or equal to 7, data transfers are bytes, if datlen is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. ? datdef: data default value this bit defines the level driven on the td pin while out of tran smission. note that if the pin is defined as multi-drive by th e pio controller, the pin is enabled only if the scc td output is 1. ? msbf: most significant bit first 0 = the lowest significant bit of the data register is shifted out first in the bit stream. 1 = the most significant bit of the data register is shifted out first in the bit stream. ? datnb: data number per frame this field defines the number of data words to be transferred after each transfer start, which is equal to (datnb +1). ? fslen: transmit frame syn length this field defines the length of the transmit frame sync sig nal and the number of bits shifted out from the transmit sync data register if fsden is 1. 31 30 29 28 27 26 25 24 ??? ? ???fsedge 23 22 21 20 19 18 17 16 fsden fsos fslen 15 14 13 12 11 10 9 8 ??? ? datnb 765 4 3210 m s b f ? dat d e f dat l e n
577 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? fsos: transmit frame sync output selection ? fsden: frame sync data enable 0 = the td line is driven with the default value during the transmit frame sync signal. 1 = ssc_tshr value is shifted out during the transmission of the transmit frame sync signal. ? fsedge: frame sync edge detection determines which edge on frame sync will gene rate the interrupt tx syn (status register). fsos selected transmit frame sync signal tf pin 0x0 none input-only 0x1 negative pulse output 0x2 positive pulse output 0x3 driven low during data transfer output 0x4 driven high during data transfer output 0x5 toggling at each start of data transfer output 0x6-0x7 reserved undefined fsedge frame sync edge detection 0x0 positive edge detection 0x1 negative edge detection
578 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 35.8.7 ssc receive holding register name: ssc_rhr address: 0xfffbc020 access type: read-only ? rdat: receive data right aligned regardless of the number of data bits defined by datlen in ssc_rfmr. 35.8.8 ssc transmit holding register name: ssc_thr address: 0xfffbc024 access type: write-only ? tdat: transmit data right aligned regardless of the number of data bits defined by datlen in ssc_tfmr. 31 30 29 28 27 26 25 24 rdat 23 22 21 20 19 18 17 16 rdat 15 14 13 12 11 10 9 8 rdat 76543210 rdat 31 30 29 28 27 26 25 24 tdat 23 22 21 20 19 18 17 16 tdat 15 14 13 12 11 10 9 8 tdat 76543210 tdat
579 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 35.8.9 ssc receive synchronization holding register name: ssc_rshr address: 0xfffbc030 access type: read-only ? rsdat: receive synchronization data 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rsdat 76543210 rsdat
580 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 35.8.10 ssc transmit synchronization holding register name: ssc_tshr address: 0xfffbc034 access type: read-write ? tsdat: transmit synchronization data 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 tsdat 76543210 tsdat
581 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 35.8.11 ssc receive compare 0 register name: ssc_rc0r address: 0xfffbc038 access type: read-write ? cp0: receive compare data 0 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cp0 76543210 cp0
582 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 35.8.12 ssc receive compare 1 register name: ssc_rc1r address: 0xfffbc03c access type: read-write ? cp1: receive compare data 1 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cp1 76543210 cp1
583 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 35.8.13 ssc status register name: ssc_sr address: 0xfffbc040 access type: read-only ? txrdy: transmit ready 0 = data has been loaded in ssc_thr and is waiting to be loaded in the transmit shift register (tsr). 1 = ssc_thr is empty. ? txempty: transmit empty 0 = data remains in ssc_thr or is currently transmitted from tsr. 1 = last data written in ssc_thr has been loaded in tsr and last data loaded in tsr has been transmitted. ? endtx: end of transmission 0 = the register ssc_tcr has not reached 0 since the last write in ssc_tcr or ssc_tncr. 1 = the register ssc_tcr has reached 0 si nce the last write in ssc_tcr or ssc_tncr. ? txbufe: transmit buffer empty 0 = ssc_tcr or ssc_tncr have a value other than 0. 1 = both ssc_tcr and ssc_tncr have a value of 0. ? rxrdy: receive ready 0 = ssc_rhr is empty. 1 = data has been receiv ed and loaded in ssc_rhr. ? ovrun: receive overrun 0 = no data has been loaded in ssc_rhr while previous data has not been read since the last read of the status register. 1 = data has been loaded in ssc_rhr while previous data has not yet been read since the last read of the status register. ? endrx: end of reception 0 = data is written on the receive counter register or receive next counter register. 1 = end of pdc transfer when receive counter register has arrived at zero. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ??????rxentxen 15 14 13 12 11 10 9 8 ????rxsynt xsyn cp1 cp0 76543210 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy
584 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? rxbuff: receive buffer full 0 = ssc_rcr or ssc_rncr have a value other than 0. 1 = both ssc_rcr and ssc_rncr have a value of 0. ?cp0: compare 0 0 = a compare 0 has not occurred since the last read of the status register. 1 = a compare 0 has occurred since the last read of the status register. ?cp1: compare 1 0 = a compare 1 has not occurred since the last read of the status register. 1 = a compare 1 has occurred since the last read of the status register. ? txsyn: transmit sync 0 = a tx sync has not occurred since the last read of the status register. 1 = a tx sync has occurred since the last read of the status register. ? rxsyn: receive sync 0 = an rx sync has not occurred since the last read of the status register. 1 = an rx sync has occurred since the last read of the status register. ? txen: transmit enable 0 = transmit is disabled. 1 = transmit is enabled. ? rxen: receive enable 0 = receive is disabled. 1 = receive is enabled.
585 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 35.8.14 ssc interrupt enable register name: ssc_ier address: 0xfffbc044 access type: write-only ? txrdy: transmit ready interrupt enable 0 = 0 = no effect. 1 = enables the transmit ready interrupt. ? txempty: transmit empty interrupt enable 0 = no effect. 1 = enables the transmit empty interrupt. ? endtx: end of transmission interrupt enable 0 = no effect. 1 = enables the end of transmission interrupt. ? txbufe: transmit buffer empty interrupt enable 0 = no effect. 1 = enables the transmit buffer empty interrupt ? rxrdy: receive ready interrupt enable 0 = no effect. 1 = enables the receive ready interrupt. ? ovrun: receive overrun interrupt enable 0 = no effect. 1 = enables the receive overrun interrupt. ? endrx: end of reception interrupt enable 0 = no effect. 1 = enables the end of reception interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????rxsynt xsyn cp1 cp0 76543210 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy
586 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? rxbuff: receive buffer full interrupt enable 0 = no effect. 1 = enables the receive buffer full interrupt. ? cp0: compare 0 interrupt enable 0 = no effect. 1 = enables the compare 0 interrupt. ? cp1: compare 1 interrupt enable 0 = no effect. 1 = enables the compare 1 interrupt. ? txsyn: tx sync interrupt enable 0 = no effect. 1 = enables the tx sync interrupt. ? rxsyn: rx sync interrupt enable 0 = no effect. 1 = enables the rx sync interrupt.
587 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 35.8.15 ssc interrupt disable register name: ssc_idr address: 0xfffbc048 access type: write-only ? txrdy: transmit ready interrupt disable 0 = no effect. 1 = disables the transmit ready interrupt. ? txempty: transmit empty interrupt disable 0 = no effect. 1 = disables the transmit empty interrupt. ? endtx: end of transmission interrupt disable 0 = no effect. 1 = disables the end of transmission interrupt. ? txbufe: transmit buffer empty interrupt disable 0 = no effect. 1 = disables the transmit buffer empty interrupt. ? rxrdy: receive ready interrupt disable 0 = no effect. 1 = disables the receive ready interrupt. ? ovrun: receive overrun interrupt disable 0 = no effect. 1 = disables the receive overrun interrupt. ? endrx: end of reception interrupt disable 0 = no effect. 1 = disables the end of reception interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????rxsynt xsyn cp1 cp0 76543210 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy
588 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? rxbuff: receive buffer full interrupt disable 0 = no effect. 1 = disables the receive buffer full interrupt. ? cp0: compare 0 interrupt disable 0 = no effect. 1 = disables the compare 0 interrupt. ? cp1: compare 1 interrupt disable 0 = no effect. 1 = disables the compare 1 interrupt. ? txsyn: tx sync interrupt enable 0 = no effect. 1 = disables the tx sync interrupt. ? rxsyn: rx sync interrupt enable 0 = no effect. 1 = disables the rx sync interrupt.
589 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 35.8.16 ssc interrupt mask register name: ssc_imr address: 0xfffbc04c access type: read-only ? txrdy: transmit ready interrupt mask 0 = the transmit ready interrupt is disabled. 1 = the transmit ready interrupt is enabled. ? txempty: transmit empty interrupt mask 0 = the transmit empty interrupt is disabled. 1 = the transmit empty interrupt is enabled. ? endtx: end of transmission interrupt mask 0 = the end of transmission interrupt is disabled. 1 = the end of transmission interrupt is enabled. ? txbufe: transmit buffer empty interrupt mask 0 = the transmit buffer empty interrupt is disabled. 1 = the transmit buffer empty interrupt is enabled. ? rxrdy: receive ready interrupt mask 0 = the receive ready interrupt is disabled. 1 = the receive ready interrupt is enabled. ? ovrun: receive overrun interrupt mask 0 = the receive overrun interrupt is disabled. 1 = the receive overrun interrupt is enabled. ? endrx: end of reception interrupt mask 0 = the end of reception interrupt is disabled. 1 = the end of reception interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????rxsynt xsyn cp1 cp0 76543210 rxbuf endrx ovrun rxrdy txbufe endtx txempty txrdy
590 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? rxbuff: receive buffer full interrupt mask 0 = the receive buffer full interrupt is disabled. 1 = the receive buffer full interrupt is enabled. ? cp0: compare 0 interrupt mask 0 = the compare 0 interrupt is disabled. 1 = the compare 0 interrupt is enabled. ? cp1: compare 1 interrupt mask 0 = the compare 1 interrupt is disabled. 1 = the compare 1 interrupt is enabled. ? txsyn: tx sync interrupt mask 0 = the tx sync interrupt is disabled. 1 = the tx sync interrupt is enabled. ? rxsyn: rx sync interrupt mask 0 = the rx sync interrupt is disabled. 1 = the rx sync interrupt is enabled.
591 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 36. timer counter (tc) 36.1 description the timer counter (tc) includes three identical 16-bit timer counter channels. each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. each channel has three external clock inputs, fi ve internal clock inputs and two multi-purpose input/output signals which can be configured by the user. each channel drives an internal inter- rupt signal which can be programmed to generate processor interrupts. the timer counter block has two global registers which act upon all three tc channels. the block control register allows the three channels to be started simultaneously with the same instruction. the block mode register defines the external clock inputs for each channel, allowing them to be chained. table 36-1 gives the assignment of the device timer counter clock inputs common to timer counter 0 to 2 table 36-1. timer counter clock assignment name definition timer_clock1 mck/2 timer_clock2 mck/8 timer_clock3 mck/32 timer_clock4 mck/128 timer_clock5 slck
592 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 36.2 block diagram figure 36-1. timer counter block diagram timer/counter channel 0 timer/counter channel 1 timer/counter channel 2 sync parallel i/o controller tc1xc1s tc0xc0s tc2xc2s int0 int1 int2 tioa0 tioa1 tioa2 tiob0 tiob1 tiob2 xc0 xc1 xc2 xc0 xc1 xc2 xc0 xc1 xc2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tioa1 tioa2 tioa0 tioa2 tioa0 tioa1 advanced interrupt controller tclk0 tclk1 tclk2 tioa0 tiob0 tioa1 tiob1 tioa2 tiob2 timer counter tioa tiob tioa tiob tioa tiob sync sync timer_clock2 timer_clock3 timer_clock4 timer_clock5 timer_clock1 table 36-2. signal name description block/channel signal name description channel signal xc0, xc1, xc2 external clock inputs tioa capture mode: timer counter input waveform mode: timer counter output tiob capture mode: timer counter input waveform mode: timer counter input/output int interrupt signal output sync synchronization input signal
593 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 36.3 pin name list 36.4 product dependencies 36.4.1 i/o lines the pins used for interfacing the compliant ex ternal devices may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the tc pins to their peripheral functions. 36.4.2 power management the tc is clocked through the power management controller (pmc), thus the programmer must first configure the pmc to enable the timer counter clock. 36.4.3 interrupt the tc has an interrupt line connected to the advanced interrupt controller (aic). handling the tc interrupt requires programming the aic before configuring the tc. table 36-3. tc pin list pin name description type tclk0-tclk2 external clock input input tioa0-tioa2 i/o line a i/o tiob0-tiob2 i/o line b i/o
594 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 36.5 functional description 36.5.1 tc description the three channels of the timer counter are independent and identical in operation. the regis- ters for channel programming are listed in table 36-4 on page 607 . 36.5.2 16-bit counter each channel is organized around a 16-bit counter. the value of the counter is incremented at each positive edge of the selected clock. when the counter has reached the value 0xffff and passes to 0x0000, an overflow occurs and the covfs bit in tc_sr (status register) is set. the current value of the counter is accessible in real time by reading the counter value regis- ter, tc_cv. the counter can be reset by a trigger. in this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 36.5.3 clock selection at block level, input clock signals of each channel can either be connected to the external inputs tclk0, tclk1 or tclk2, or be connected to t he internal i/o signals tioa0, tioa1 or tioa2 for chaining by programming the tc_bmr (block mode). see figure 36-2 on page 595 . each channel can independently select an internal or external clock source for its counter: ? internal clock signals: timer_cl ock1, timer_clock2, timer_clock3, timer_clock4, timer_clock5 ? external clock signals: xc0, xc1 or xc2 this selection is made by the tcclks bits in the tc channel mode register. the selected clock can be inverted with the clki bit in tc_cmr. this allows counting on the opposite edges of the clock. the burst function allows the clock to be validat ed when an external signal is high. the burst parameter in the mode register defines this signal (none, xc0, xc1, xc2). see figure 36-3 on page 595 note: in all cases, if an external clock is used, the du ration of each of its leve ls must be longer than the master clock period. the external clock frequen cy must be at least 2.5 times lower than the mas- ter clock
595 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 36-2. clock chaining selection figure 36-3. clock selection timer/counter channel 0 sync tc0xc0s tioa0 tiob0 xc0 xc1 = tclk1 xc2 = tclk2 tclk0 tioa1 tioa2 timer/counter channel 1 sync tc1xc1s tioa1 tiob1 xc0 = tclk2 xc1 xc2 = tclk2 tclk1 tioa0 tioa2 timer/counter channel 2 sync tc2xc2s tioa2 tiob2 xc0 = tclk0 xc1 = tclk1 xc2 tclk2 tioa0 tioa1 timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 tcclks clki burst 1 selected clock
596 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 36.5.4 clock control the clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. see figure 36-4 . ? the clock can be enabled or disabled by the user with the clken and the clkdis commands in the control register. in capture mode it can be disabled by an rb load event if ldbdis is set to 1 in tc_cmr. in waveform mode, it can be disabled by an rc compare event if cpcdis is set to 1 in tc_cmr. when disabled, the start or the stop actions have no effect: only a clken command in the control register can re-enable the clock. when the clock is enabled, the clksta bit is set in the status register. ? the clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. the clock can be stopped by an rb load event in capture mode (ldbstop = 1 in tc_cmr) or a rc compare event in waveform mode (cpcstop = 1 in tc_cmr). the start and the stop commands have effect only if the clock is enabled. figure 36-4. clock control 36.5.5 tc operating modes each channel can independently operate in two different modes: ? capture mode provides measurement on signals. ? waveform mode provides wave generation. the tc operating mode is prog rammed with the wave bit in th e tc channel mode register. in capture mode, tioa and tiob are configured as inputs. in waveform mode, tioa is always configured to be an output and tiob is an output if it is not selected to be the external trigger. 36.5.6 trigger a trigger resets the counter and starts the counter clock. three types of triggers are common to both modes, and a fourth external trigger is available to each mode. the following triggers are common to both modes: qs r s r q clksta clken clkdis stop event disable event counter clock selected clock trigger
597 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? software trigger: each channel has a software trigger, available by setting swtrg in tc_ccr. ? sync: each channel has a synchronization si gnal sync. when asserted, this signal has the same effect as a software trigger. the sync signals of all channels are asserted simultaneously by writing tc_bcr (block control) with sync set. ? compare rc trigger: rc is implemented in each channel and can provide a trigger when the counter value matches the rc val ue if cpctrg is set in tc_cmr. the channel can also be configured to have an external trigger. in capture mode, the external trigger signal can be selected between tioa and tiob. in waveform mode, an external event can be programmed on one of the following signals: tiob, xc0, xc1 or xc2. this external event can then be programmed to perform a trigger by setting enetrg in tc_cmr. if an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. this means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. 36.5.7 capture operating mode this mode is entered by clearing the wave parameter in tc_cmr (channel mode register). capture mode allows the tc channel to perform measurements such as pulse timing, fre- quency, period, duty cycle and phase on tioa and tiob sig nals which are considered as inputs. figure 36-5 shows the configuration of the tc channel when programmed in capture mode. 36.5.8 capture registers a and b registers a and b (ra and rb) are used as capture registers. this means that they can be loaded with the counter value when a progr ammable event occurs on the signal tioa. the ldra parameter in tc_cmr defines the tioa edge for the loading of register a, and the ldrb parameter defines the tioa edge for the loading of register b. ra is loaded only if it has not been loaded since the last trigger or if rb has been loaded since the last loading of ra. rb is loaded only if ra has been loaded sinc e the last trigger or t he last loading of rb. loading ra or rb before the read of the last value loaded sets the overrun error flag (lovrs) in tc_sr (status register). in this case, the old value is overwritten. 36.5.9 trigger conditions in addition to the sync signal, the software trigger and the rc compare trigger, an external trig- ger can be defined. the abetrg bit in tc_cmr selects tioa or tiob input signal as an external trigger. the etrgedg parameter defines the ed ge (rising, falling or both) det ected to genera te an external trigger. if etrgedg = 0 (none), the external trigger is disabled.
598 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 36-5. capture mode timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 tcclks clki qs r s r q clksta clken clkdis burst tiob register c capture register a capture register b compare rc = 16-bit counter abetrg swtrg etrgedg cpctrg tc1_imr trig ldrbs ldras etrgs tc1_sr lovrs covfs sync 1 mtiob tioa mtioa ldra ldbstop if ra is not loaded or rb is loaded if ra is loaded ldbdis cpcs int edge detector edge detector ldrb edge detector clk ovf reset timer/counter channel
599 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 36.5.10 waveform operating mode waveform operating mode is entered by setting the wave parameter in tc_cmr (channel mode register). in waveform operating mode the tc channel generates 1 or 2 pwm signals with the same fre- quency and independently programmable duty cycles , or generates differe nt types of one-shot or repetitive pulses. in this mode, tioa is configured as an output and tiob is defined as an output if it is not used as an external event ( eevt parameter in tc_cmr). figure 36-6 shows the configuration of the tc channel when programmed in waveform operat- ing mode. 36.5.11 waveform selection depending on the wavsel parameter in tc_c mr (channel mode register), the behavior of tc_cv varies. with any selection, ra, rb and rc can all be used as compare registers. ra compare is used to control the tioa output, rb compare is used to control the tiob output (if correctly configured) and rc compare is used to control tioa and/or tiob outputs.
600 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 36-6. waveform mode tcclks clki qs r s r q clksta clken clkdis cpcdis burst tiob register a register b register c compare ra = compare rb = compare rc = cpcstop 16-bit counter eevt eevtedg sync swtrg enetrg wavsel tc1_imr trig acpc acpa aeevt aswtrg bcpc bcpb beevt bswtrg tioa mtioa tiob mtiob cpas covfs etrgs tc1_sr cpcs cpbs clk ovf reset output controller output controller int 1 edge detector timer/counter channel timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 wavsel
601 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 36.5.11.1 wavsel = 00 when wavsel = 00, the value of tc_cv is incr emented from 0 to 0x ffff. once 0xffff has been reached, the value of tc_cv is reset. incrementation of tc_cv starts again and the cycle continues. see figure 36-7 . an external event trigger or a software trigger can reset the value of tc_cv. it is important to note that the trigger may occur at any time. see figure 36-8 . rc compare cannot be programmed to generate a trigger in this configuration. at the same time, rc compare can stop the counter clock (cpcstop = 1 in tc_cmr) and/or disable the counter clock (cpcdis = 1 in tc_cmr). figure 36-7. wavsel= 00 without trigger counter value r c r b r a tiob tioa counter decremented by compare match with rc 0xffff waveform examples
602 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 36-8. wavsel= 00 with trigger 36.5.11.2 wavsel = 10 when wavsel = 10, the value of tc_cv is incremented from 0 to the value of rc, then auto- matically reset on a rc compare. once the value of tc_cv has been reset, it is then incremented and so on. see figure 36-9 . it is important to note that tc_cv can be reset at any time by an external event or a software trigger if both are programmed correctly. see figure 36-10 . in addition, rc compare can stop the counter clock (cpcstop = 1 in tc_cmr) and/or disable the counter clock (cpcdis = 1 in tc_cmr). figure 36-9. wavsel = 10 without trigger time counter value r c r b r a tiob tioa counter cleared by compare match with 0xffff 0xffff waveform examples counter cleared by trigger time counter value r c r b r a tiob tioa counter cleared by compare match with rc 0xffff waveform examples
603 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 36-10. wavsel = 10 with trigger 36.5.11.3 wavsel = 01 when wavsel = 01, the value of tc_cv is incremented from 0 to 0xffff. once 0xffff is reached, the value of tc_cv is decremented to 0, then re-incremented to 0xffff and so on. see figure 36-11 . a trigger such as an external event or a software trigger can modify tc_cv at any time. if a trig- ger occurs while tc_cv is incrementing, tc_cv then decrements. if a trigger is received while tc_cv is decrementing, tc_cv then increments. see figure 36-12 . rc compare cannot be programmed to generate a trigger in this configuration. at the same time, rc compare can stop the counter clock (cpcstop = 1) and/or disable the counter clock (cpcdis = 1). counter value tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples counter dec by trigger r c r b r a
604 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 36-11. wavsel = 01 without trigger figure 36-12. wavsel = 01 with trigger 36.5.11.4 wavsel = 11 when wavsel = 11, the value of tc_cv is incremented from 0 to rc. once rc is reached, the value of tc_cv is decremented to 0, then re-incremented to rc and so on. see figure 36-13 . a trigger such as an external event or a software trigger can modify tc_cv at any time. if a trig- ger occurs while tc_cv is incrementing, tc_cv then decrements. if a trigger is received while tc_cv is decrementing, tc_cv then increments. see figure 36-14 . rc compare can stop the counter clock (cpcstop = 1) and/or disable the counter clock (cpc- dis = 1). time counter value r c r b r a tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples time counter value tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples counter decremented by trigger counter incremented by trigger r c r b r a
605 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 36-13. wavsel = 11 without trigger figure 36-14. wavsel = 11 with trigger time counter value r c r b r a tiob tioa counter decremented by compare match with rc 0xffff waveform examples time counter value tiob tioa counter decremented by compare match with rc 0xffff waveform examples counter decremented by trigger counter incremented by trigger r c r b r a
606 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 36.5.12 external event/trigger conditions an external event can be programmed to be detected on one of the clock sources (xc0, xc1, xc2) or tiob. the external event selected can then be used as a trigger. the eevt parameter in tc_cmr selects the external tr igger. the eevtedg parameter defines the trigger edge for each of the possible external triggers (ris ing, falling or both). if eevtedg is cleared (none), no external event is defined. if tiob is defined as an external event signal (eevt = 0), tiob is no longer used as an output and the compare register b is not used to generate waveforms and subsequently no irqs. in this case the tc channel can only generate a waveform on tioa. when an external event is defined, it can be used as a trigger by setting bit enetrg in tc_cmr. as in capture mode, the sync signal and the softw are trigger are also available as triggers. rc compare can also be used as a trigger depending on the parameter wavsel. 36.5.13 output controller the output controller defines the output level changes on tioa and tiob following an event. tiob control is used only if tiob is defin ed as output (not as an external event). the following events control tioa and tiob: software trigger, external event and rc compare. ra compare controls tioa and rb compare controls tiob. each of these events can be pro- grammed to set, clear or toggle the output as defined in the corresponding parameter in tc_cmr.
607 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 36.6 timer counter (tc) user interface notes: 1. channel index ranges from 0 to 2. 2. read-only if wave = 0 table 36-4. register mapping offset (1) register name access reset 0x00 + channel * 0x40 + 0x00 channel control register tc_ccr write-only ? 0x00 + channel * 0x40 + 0x04 channel mode register tc_cmr read-write 0 0x00 + channel * 0x40 + 0x08 reserved 0x00 + channel * 0x40 + 0x0c reserved 0x00 + channel * 0x40 + 0x10 counter value tc_cv read-only 0 0x00 + channel * 0x40 + 0x14 register a tc_ra read-write (2) 0 0x00 + channel * 0x40 + 0x18 register b tc_rb read-write (2) 0 0x00 + channel * 0x40 + 0x1c register c tc_rc read-write 0 0x00 + channel * 0x40 + 0x20 status register tc_sr read-only 0 0x00 + channel * 0x40 + 0x24 interrupt enable register tc_ier write-only ? 0x00 + channel * 0x40 + 0x28 interrupt disable register tc_idr write-only ? 0x00 + channel * 0x40 + 0x2c interrupt mask register tc_imr read-only 0 0xc0 block control register tc_bcr write-only ? 0xc4 block mode register tc_bmr read-write 0 0xfc reserved ? ? ?
608 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 36.6.1 tc block control register register name: tc_bcr addresses: 0xfffa00c0 (0), 0xfffdc0c0 (1) access type: write-only ? sync: synchro command 0 = no effect. 1 = asserts the sync signal which generates a software trigger simultaneously for each of the channels. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????sync
609 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 36.6.2 tc block mode register register name: tc_bmr addresses: 0xfffa00c4 (0), 0xfffdc0c4 (1) access type: read-write ? tc0xc0s: external clock signal 0 selection ? tc1xc1s: external clock signal 1 selection ? tc2xc2s: external clock signal 2 selection 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? tc2xc2s tc1xc1s tc0xc0s tc0xc0s signal connected to xc0 00tclk0 0 1 none 10tioa1 11tioa2 tc1xc1s signal connected to xc1 00tclk1 0 1 none 10tioa0 11tioa2 tc2xc2s signal connected to xc2 00tclk2 0 1 none 10tioa0 11tioa1
610 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 36.6.3 tc channel control register register name: tc_ccrx [x=0..2] addresses: 0xfffa0000 (0)[0], 0xfffa0040 (0)[1], 0xfffa 0080 (0)[2], 0xfffdc000 (1)[0], 0xfffdc040 (1)[1], 0xfffdc080 (1)[2] access type: write-only ? clken: counter clock enable command 0 = no effect. 1 = enables the clock if clkdis is not 1. ? clkdis: counter clock disable command 0 = no effect. 1 = disables the clock. ? swtrg: software trigger command 0 = no effect. 1 = a software trigger is performed: the counter is reset and the clock is started. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????swtrgclkdisclken
611 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 36.6.4 tc channel mode register: capture mode register name: tc_cmrx [x=0..2] (wave = 0) addresses: 0xfffa0004 (0)[0], 0xfffa0044 (0)[1], 0xfffa 0084 (0)[2], 0xfffdc004 (1)[0], 0xfffdc044 (1)[1], 0xfffdc084 (1)[2] access type: read-write ? tcclks: clock selection ? clki: clock invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock. ? burst: burst signal selection ? ldbstop: counter clock stopped with rb loading 0 = counter clock is not stopped when rb loading occurs. 1 = counter clock is stopped when rb loading occurs. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? ? ldrb ldra 15 14 13 12 11 10 9 8 wave cpctrg ? ? ? abetrg etrgedg 76543210 ldbdis ldbstop burst clki tcclks tcclks clock selected 0 0 0 timer_clock1 0 0 1 timer_clock2 0 1 0 timer_clock3 0 1 1 timer_clock4 1 0 0 timer_clock5 101xc0 110xc1 111xc2 burst 0 0 the clock is not gated by an external signal. 0 1 xc0 is anded with the selected clock. 1 0 xc1 is anded with the selected clock. 1 1 xc2 is anded with the selected clock.
612 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? ldbdis: counter clock disable with rb loading 0 = counter clock is not disabl ed when rb loading occurs. 1 = counter clock is disabled when rb loading occurs. ? etrgedg: external trigger edge selection ? abetrg: tioa or tiob external trigger selection 0 = tiob is used as an external trigger. 1 = tioa is used as an external trigger. ? cpctrg: rc compare trigger enable 0 = rc compare has no effect on the counter and its clock. 1 = rc compare resets the counter and starts the counter clock. ?wave 0 = capture mode is enabled. 1 = capture mode is disabled (waveform mode is enabled). ? ldra: ra loading selection ? ldrb: rb loading selection etrgedg edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge ldra edge 0 0 none 0 1 rising edge of tioa 1 0 falling edge of tioa 1 1 each edge of tioa ldrb edge 0 0 none 0 1 rising edge of tioa 1 0 falling edge of tioa 1 1 each edge of tioa
613 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 36.6.5 tc channel mode register: waveform mode register name: tc_cmrx [x=0..2] (wave = 1) addresses: 0xfffa0004 (0)[0], 0xfffa0044 (0)[1], 0xfffa 0084 (0)[2], 0xfffdc004 (1)[0], 0xfffdc044 (1)[1], 0xfffdc084 (1)[2] access type: read-write ? tcclks: clock selection ? clki: clock invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock. ? burst: burst signal selection ? cpcstop: counter clock stopped with rc compare 0 = counter clock is not stopped when counter reaches rc. 1 = counter clock is stopped when counter reaches rc. 31 30 29 28 27 26 25 24 bswtrg beevt bcpc bcpb 23 22 21 20 19 18 17 16 aswtrg aeevt acpc acpa 15 14 13 12 11 10 9 8 wave wavsel enetrg eevt eevtedg 76543210 cpcdis cpcstop burst clki tcclks tcclks clock selected 0 0 0 timer_clock1 0 0 1 timer_clock2 0 1 0 timer_clock3 0 1 1 timer_clock4 1 0 0 timer_clock5 101xc0 110xc1 111xc2 burst 0 0 the clock is not gated by an external signal. 0 1 xc0 is anded with the selected clock. 1 0 xc1 is anded with the selected clock. 1 1 xc2 is anded with the selected clock.
614 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? cpcdis: counter clock disable with rc compare 0 = counter clock is not disabl ed when counter reaches rc. 1 = counter clock is disabled when counter reaches rc. ? eevtedg: external ev ent edge selection ? eevt: external event selection note: 1. if tiob is chosen as the external event signal, it is conf igured as an input and no longer generates waveforms and subse- quently no irqs . ? enetrg: external event trigger enable 0 = the external event has no effect on the counter and its clock. in this case, the selected external event only controls the tioa output. 1 = the external event resets the counter and starts the counter clock. ? wavsel: waveform selection ?wave 0 = waveform mode is disabled (capture mode is enabled). 1 = waveform mode is enabled. eevtedg edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge eevt signal selected as exte rnal event tiob direction 0 0 tiob input (1) 0 1 xc0 output 1 0 xc1 output 1 1 xc2 output wavsel effect 0 0 up mode without automatic trigger on rc compare 1 0 up mode with automatic trigger on rc compare 0 1 updown mode without automat ic trigger on rc compare 1 1 updown mode with automatic trigger on rc compare
615 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? acpa: ra compare effect on tioa ? acpc: rc compare effect on tioa ? aeevt: external event effect on tioa ? aswtrg: software trigger effect on tioa ? bcpb: rb compare effect on tiob acpa effect 0 0 none 0 1 set 1 0 clear 1 1 toggle acpc effect 0 0 none 0 1 set 1 0 clear 1 1 toggle aeevt effect 0 0 none 0 1 set 1 0 clear 11toggle aswtrg effect 0 0 none 0 1 set 1 0 clear 1 1 toggle bcpb effect 0 0 none 0 1 set 1 0 clear 11toggle
616 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? bcpc: rc compare effect on tiob ? beevt: external event effect on tiob ? bswtrg: software trigger effect on tiob bcpc effect 0 0 none 0 1 set 1 0 clear 1 1 toggle beevt effect 0 0 none 0 1 set 1 0 clear 1 1 toggle bswtrg effect 0 0 none 01set 1 0 clear 11toggle
617 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 36.6.6 tc counter value register register name: tc_cvx [x=0..2] addresses: 0xfffa0010 (0)[0], 0xfffa0050 (0)[1], 0xfffa 0090 (0)[2], 0xfffdc010 (1)[0], 0xfffdc050 (1)[1], 0xfffdc090 (1)[2] access type: read-only ? cv: counter value cv contains the counter value in real time. 36.6.7 tc register a register name: tc_rax [x=0..2] addresses: 0xfffa0014 (0)[0], 0xfffa0054 (0)[1], 0xfffa 0094 (0)[2], 0xfffdc014 (1)[0], 0xfffdc054 (1)[1], 0xfffdc094 (1)[2] access type: read-only if wave = 0, read-write if wave = 1 ? ra: register a ra contains the register a value in real time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cv 76543210 cv 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ra 76543210 ra
618 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 36.6.8 tc register b register name: tc_rbx [x=0..2] addresses: 0xfffa0018 (0)[0], 0xfffa0058 (0)[1], 0xfffa 0098 (0)[2], 0xfffdc018 (1)[0], 0xfffdc058 (1)[1], 0xfffdc098 (1)[2] access type: read-only if wave = 0, read-write if wave = 1 ? rb: register b rb contains the register b value in real time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rb 76543210 rb
619 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 36.6.9 tc register c register name: tc_rcx [x=0..2] addresses: 0xfffa001c (0)[0], 0xfffa005c (0)[1], 0xff fa009c (0)[2], 0xfffdc01c (1)[0], 0xfffdc05c (1)[1], 0xfffdc09c (1)[2] access type: read-write ? rc: register c rc contains the register c value in real time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rc 76543210 rc
620 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 36.6.10 tc status register register name: tc_srx [x=0..2] addresses: 0xfffa0020 (0)[0], 0xfffa0060 (0)[1], 0xfffa00 a0 (0)[2], 0xfffdc020 (1)[0], 0xfffdc060 (1)[1], 0xfffdc0a0 (1)[2] access type: read-only ? covfs: counter overflow status 0 = no counter overflow has occurred since the last read of the status register. 1 = a counter overflow has occurred since the last read of the status register. ? lovrs: load overrun status 0 = load overrun has not occurred since the last read of the status register or wave = 1. 1 = ra or rb have been loaded at least twice without any read of the corresponding register since the last read of the sta- tus register, if wave = 0. ? cpas: ra compare status 0 = ra compare has not occurred since the last read of the status register or wave = 0. 1 = ra compare has occurred since the last read of the status register, if wave = 1. ? cpbs: rb compare status 0 = rb compare has not occurred since the last read of the status register or wave = 0. 1 = rb compare has occurred since the last read of the status register, if wave = 1. ? cpcs: rc compare status 0 = rc compare has not occurred since the last read of the status register. 1 = rc compare has occurred since the last read of the status register. ? ldras: ra loading status 0 = ra load has not occurred si nce the last read of the status register or wave = 1. 1 = ra load has occurred since the last re ad of the status register, if wave = 0. ? ldrbs: rb loading status 0 = rb load has not occurred si nce the last read of the status register or wave = 1. 1 = rb load has occurred since the last re ad of the status register, if wave = 0. ? etrgs: external trigger status 0 = external trigger has not occurred since the last read of the status register. 1 = external trigger has occurred since the last read of the status register. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?????mtiobmtioaclksta 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
621 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? clksta: clock enabling status 0 = clock is disabled. 1 = clock is enabled. ? mtioa: tioa mirror 0 = tioa is low. if wave = 0, this mean s that tioa pin is low. if wave = 1, this means that tioa is driven low. 1 = tioa is high. if wave = 0, this mean s that tioa pin is high. if wave = 1, this means that ti oa is driven high. ? mtiob: tiob mirror 0 = tiob is low. if wave = 0, this mean s that tiob pin is low. if wave = 1, this means that tiob is driven low. 1 = tiob is high. if wave = 0, this mean s that tiob pin is high. if wave = 1, this means that ti ob is driven high.
622 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 36.6.11 tc interrupt enable register register name: tc_ierx [x=0..2] addresses: 0xfffa0024 (0)[0], 0xfffa0064 (0)[1], 0xfffa00 a4 (0)[2], 0xfffdc024 (1)[0], 0xfffdc064 (1)[1], 0xfffdc0a4 (1)[2] access type: write-only ? covfs: counter overflow 0 = no effect. 1 = enables the counter overflow interrupt. ? lovrs: load overrun 0 = no effect. 1 = enables the load overrun interrupt. ? cpas: ra compare 0 = no effect. 1 = enables the ra compare interrupt. ? cpbs: rb compare 0 = no effect. 1 = enables the rb compare interrupt. ? cpcs: rc compare 0 = no effect. 1 = enables the rc compare interrupt. ? ldras: ra loading 0 = no effect. 1 = enables the ra load interrupt. ? ldrbs: rb loading 0 = no effect. 1 = enables the rb load interrupt. ? etrgs: external trigger 0 = no effect. 1 = enables the external trigger interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
623 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 36.6.12 tc interrupt disable register register name: tc_idrx [x=0..2] addresses: 0xfffa0028 (0)[0], 0xfffa0068 (0)[1], 0xfffa00 a8 (0)[2], 0xfffdc028 (1)[0], 0xfffdc068 (1)[1], 0xfffdc0a8 (1)[2] access type: write-only ? covfs: counter overflow 0 = no effect. 1 = disables the counter overflow interrupt. ? lovrs: load overrun 0 = no effect. 1 = disables the load overru n interrupt (if wave = 0). ? cpas: ra compare 0 = no effect. 1 = disables the ra compare interrupt (if wave = 1). ? cpbs: rb compare 0 = no effect. 1 = disables the rb compare interrupt (if wave = 1). ? cpcs: rc compare 0 = no effect. 1 = disables the rc compare interrupt. ? ldras: ra loading 0 = no effect. 1 = disables the ra load interrupt (if wave = 0). ? ldrbs: rb loading 0 = no effect. 1 = disables the rb load interrupt (if wave = 0). ? etrgs: external trigger 0 = no effect. 1 = disables the external trigger interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
624 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 36.6.13 tc interrupt mask register register name: tc_imrx [x=0..2] addresses: 0xfffa002c (0)[0], 0xfffa006c (0)[1], 0xf ffa00ac (0)[2], 0xfffdc02c (1)[0], 0xfffdc06c (1)[1], 0xfffdc0ac (1)[2] access type: read-only ? covfs: counter overflow 0 = the counter overflow interrupt is disabled. 1 = the counter overflow interrupt is enabled. ? lovrs: load overrun 0 = the load overrun interrupt is disabled. 1 = the load overrun interrupt is enabled. ? cpas: ra compare 0 = the ra compare interrupt is disabled. 1 = the ra compare interrupt is enabled. ? cpbs: rb compare 0 = the rb compare interrupt is disabled. 1 = the rb compare interrupt is enabled. ? cpcs: rc compare 0 = the rc compare interrupt is disabled. 1 = the rc compare interrupt is enabled. ? ldras: ra loading 0 = the load ra interrupt is disabled. 1 = the load ra interrupt is enabled. ? ldrbs: rb loading 0 = the load rb interrupt is disabled. 1 = the load rb interrupt is enabled. ? etrgs: external trigger 0 = the external trigger interrupt is disabled. 1 = the external trigger interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
625 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 37. multimedia card interface (mci) 37.1 description the multimedia card interface (mci) supports the multimedia card (mmc) specification v3.11, the sdio specification v1.1 and the sd memory card specification v1.0. the mci includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead. the mci supports stream, block and multi-block data read and write, and is compatible with the peripheral dma controller (pdc) channels, minimi zing processor intervention for large buffer transfers. the mci operates at a rate of up to master cloc k divided by 2 and supports the interfacing of 2 slot(s). each slot may be used to interface with a multimediacard bus (up to 30 cards) or with a sd memory card. only one slot can be selected at a time (slots are multiplexed). a bit field in the sd card register performs this selection. the sd memory card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the multimedia card on a 7-pin interface (clock, command, one data, three power lines and one reserved for future use). the sd memory card interface also supports multimedia card operations. the main differences between sd and multimedia cards are the initialization process and the bus topology.
626 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 37.2 block diagram figure 37-1. block diagram note: 1. when several mci (x mci) are embedded in a product, mcck refers to mcix_ck, mccda to mcix_cda, mccdb to mcix_cdb,mcday to mcix_day, mcdby to mcix_dby. mci interface interrupt control pio pdc apb bridge pmc mck mci interrupt mcck (1) mccda (1) mcda0 (1) mcda1 (1) mcda2 (1) mcda3 (1) mccdb (1) mcdb0 (1) mcdb1 (1) mcdb2 (1) mcdb3 (1) apb
627 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 37.3 application block diagram figure 37-2. application block diagram 37.4 pin name list notes: 1. i: input, o: output, pp: push/pull, od: open drain. 2. when several mci (x mci) are embedded in a product, m cck refers to mcix_ck, mccda to mcix_cda, mccdb to mcix_cdb, mcday to mcix_day, mcdby to mcix_dby. 37.5 product dependencies 37.5.1 i/o lines the pins used for interfacing the multimedia cards or sd cards may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the peripheral functions to mci pins. 23456 17 mmc 23456 17 8 sdcard 9 physical layer mci interface application layer ex: file system, audio, security, etc. table 37-1. i/o lines description pin name (2) pin description type (1) comments mccda/mccdb command/response i/o/pp/od cmd of an mmc or sdcard/sdio mcck clock i/o clk of an mmc or sd card/sdio mcda0 - mcda3 data 0..3 of slot a i/o/pp dat0 of an mmc dat[0..3] of an sd card/sdio mcdb0 - mcdb3 data 0..3 of slot b i/o/pp dat0 of an mmc dat[0..3] of an sd card/sdio
628 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 37.5.2 power management the mci may be clocked through the power management controller (pmc), so the programmer must first configure the pmc to enable the mci clock. 37.5.3 interrupt the mci interface has an interrupt line connected to the advanced interrupt controller (aic). handling the mci interrupt requires programming the aic before configuring the mci. 37.6 bus topology figure 37-3. multimedia memory card bus topology the multimedia card communication is based on a 7- pin serial bus interface. it has three com- munication lines and four supply lines. notes: 1. i: input, o: output, pp : push/pull, od: open drain. 2. when several mci (x mci) are embedded in a product, mcck refers to mcix_ck, mccda to mcix_cda, mccdb to mcix_cdb, mcday to mcix_day, mcdby to mcix_dby. figure 37-4. mmc bus connections (one slot) note: when several mci (x mci) are embedded in a product, mcck refers to mcix_ck, mccda to mcix_cda mcday to mcix_day. table 37-2. bus topology pin number name type (1) description mci pin name (2) (slot z) 1 rsv nc not connected - 2 cmd i/o/pp/od command/response mccdz 3 vss1 s supply voltage ground vss 4 vdd s supply voltage vdd 5 clk i/o clock mcck 6 vss2 s supply voltage ground vss 7 dat[0] i/o/pp data 0 mcdz0 23456 17 mmc 23456 1 7 23456 1 7 23456 17 mccda mcda0 mcck mmc1 mmc2 mmc3 mci
629 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 37-5. sd memory card bus topology the sd memory card bus includes the signals listed in table 37-3 . notes: 1. i: input, o: output, pp: push pull, od: open drain. 2. when several mci (x mci) are embedded in a product, mcck refers to mcix_ck, mccda to mcix_cda, mccdb to mcix_cdb, mcday to mcix_day, mcdby to mcix_dby. figure 37-6. sd card bus connections with one slot note: when several mci (x mci) are embedded in a product, mcck refers to mcix_ck, mccda to mcix_cda mcday to mcix_day. table 37-3. sd memory card bus signals pin number name type (1) description mci pin name (2) (slot z) 1 cd/dat[3] i/o/pp card detect/ data line bit 3 mcdz3 2 cmd pp command/response mccdz 3 vss1 s supply voltage ground vss 4 vdd s supply voltage vdd 5 clk i/o clock mcck 6 vss2 s supply voltage ground vss 7 dat[0] i/o/pp data line bit 0 mcdz0 8 dat[1] i/o/pp data line bit 1 or interrupt mcdz1 9 dat[2] i/o/pp data line bit 2 mcdz2 23456 17 8 sd card 9 23456 17 mcda0 - mcda3 mccda mcck 8 sd card 9
630 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 37-7. sd card bus connections with two slots note: when several mci (x mci) are embedded in a product, mcck refers to mcix_ck,mccda to mcix_cda, mcday to mcix_day, mccdb to mcix_cdb, mcdby to mcix_dby. figure 37-8. mixing multimedia and sd memory cards with two slots note: when several mci (x mci) are embedded in a product, mcck refers to mcix_ck, mccda to mcix_cda, mcday to mcix_day, mccdb to mcix_cdb, mcdby to mcix_dby. when the mci is configured to operate with sd memory cards, the width of the data bus can be selected in the mci_sdcr register. clearing the sdcbus bit in this register means that the width is one bit; setting it means that the width is four bits. in the case of multimedia cards, only the data line 0 is used. the other data lines can be used as independent pios. 23456 17 mcda0 - mcda3 mccda mcck 8 sd card 1 9 23456 17 8 sd card 2 9 mcdb0 - mcdb3 mccdb 23456 1 7 23456 1 7 23456 17 mmc1 mmc2 mmc3 mcda0 mcck mccda 23456 17 8 sd card 9 mcdb0 - mcdb3 mccdb
631 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 37.7 multimedia card operations after a power-on reset, the cards are initialized by a special message-based multimedia card bus protocol. each message is represented by one of the following tokens: ? command: a command is a token that starts an operation. a command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). a command is transferred serially on the cmd line. ? response: a response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. a response is transferred serially on the cmd line. ? data: data can be transferred from the card to the host or vice versa. data is transferred via the data line. card addressing is implemented using a sess ion address assigned during the initialization phase by the bus controller to all currently connected cards. their unique cid number identifies individual cards. the structure of commands, resp onses and data blocks is descr ibed in the multimedia-card system specification. see also table 37-4 on page 632 . multimediacard bus data transfers are composed of these tokens. there are different types of operations. addressed operations always contain a command and a response token. in addition, some operations have a data token; the others transfer their infor- mation directly within the command or response structure. in this case, no data token is present in an operation. the bits on the dat and the cmd lines are transferred synchronous to the clock mci clock. two types of data transfer commands are defined: ? sequential commands: these commands initiate a continuous data stream. they are terminated only when a stop command follows on the cmd line. this mode reduces the command overhead to an absolute minimum. ? block-oriented commands: th ese commands send a data block succeeded by crc bits. both read and write operations allow either single or multiple block transmission. a multiple block transmission is terminated when a stop co mmand follows on the cm d line similarly to the sequential read or when a multiple block transmission has a pre-defined block count ( see ?data transfer operation? on page 634. ). the mci provides a set of registers to perform the entire range of multimedia card operations. 37.7.1 command - response operation after reset, the mci is disabled and becomes valid after setting the mcien bit in the mci_cr control register. the pwsen bit saves power by dividing the mci clock by 2 pwsdiv + 1 when the bus is inactive. the two bits, rdproof and wrproof in the mci mode register (mci_mr) allow stopping the mci clock during read or write access if the internal fifo is full. this will guarantee data integrity, not bandwidth. the command and the response of the card are clocked out with the rising edge of the mci clock. all the timings for multimedia card are defined in the multim ediacard system specification.
632 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary the two bus modes (open drain and push/pull) needed to process all the operations are defined in the mci command register. the mci_cmdr allows a command to be carried out. for example, to perform an all_send_cid command: the command all_send_cid and the fields and values for the mci_cmdr control register are described in table 37-4 and table 37-5 . note: bcr means broadcast command with response. the mci_argr contains the argument field of the command. to send a command, the user must perform the following steps: ? fill the argument regi ster (mci_argr) with the command argument. ? set the command register (mci_cmdr) (see table 37-5 ). the command is sent immediately after writing the command register. the status bit cmdrdy in the status register (mci_sr) is assert ed when the command is completed. if the command requires a response, it can be read in the mci response register (mci_rspr). the response size can be from 48 bits up to 136 bits depending on the command. the mci embeds an error detection to prevent any corrupted data during the transfer. the following flowchart shows how to send a command to the card and read the response if needed. in this example, the status register bits are polled but setting the appropriate bits in the interrupt enable register (mci_ier) allows using an interrupt method. host command n id cycles cid cmd s t content crc e z ****** z s t content z z z table 37-4. all_send_cid command description cmd index type argument resp abbreviation command description cmd2 bcr [31:0] stuff bits r2 all_send_cid asks all cards to send their cid numbers on the cmd line table 37-5. fields and values for mci_cmdr command register field value cmdnb (command number) 2 (cmd2) rsptyp (response type) 2 (r2: 136 bits response) spcmd (special command) 0 (not a special command) opcmd (open drain command) 1 maxlat (max latency for command to response) 0 (nid cycles ==> 5 cycles) trcmd (transfer command) 0 (no transfer) trdir (transfer direction) x (available only in transfer command) trtyp (transfer type) x (available only in transfer command) iospcmd (sdio special command) 0 (not a special command)
633 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 37-9. command/response functional flow diagram note: 1. if the command is send_op_cond, the crc error flag is always present (refer to r3 response in the multimedi a card specification). return ok return error (1) set the command argument mci_argr = argument (1) set the command mci_cmdr = command read mci_sr cmdrdy status error flags? read response if required ye s wait for command ready status flag check error bits in the status register (1) 0 1
634 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 37.7.2 data transfer operation the multimedia card allo ws several read/write operations (single block, multiple blocks, stream, etc.). these kind of transfers can be selected setting the transfer type (trtyp) field in the mci command register (mci_cmdr). these operations can be done using the features of the peripheral dma controller (pdc). if the pdcmode bit is set in mci_mr, then all reads and writes us e the pdc facilities. in all cases, the block length (blklen field) must be defined either in the mode register mci_mr, or in the block register mci_blkr. this field determines the size of the data block. enabling pdc force byte transf er (pdcfbyte bit in the mci_mr) allows the pdc to manage with internal byte transfers, so that transfer of blocks with a size different from modulo 4 can be supported. when pdc force byte transfer is di sabled, the pdc type of transfers are in words, otherwise the type of transfers are in bytes. consequent to mmc specification 3.1, two types of multiple block read (or write) transactions are defined (the host can use either one at any time): ? open-ended/infinite multiple block read (or write): the number of blocks for the read (or write) multiple block operation is not defined. the card will continuously transfer (o r program) data blocks until a stop transmission command is received. ? multiple block read (or write) with pre-defined block count (since version 3.1 and higher): the card will transfer (or prog ram) the requested number of data blocks and terminate the transaction. the stop command is not required at the end of this type of multiple block read (or write), unless terminated with an error. in order to start a multiple block read (or write) with pre-defined block count, the host must correctly program the mci block register (mci_blkr). otherwise the card will start an open-ended multiple block read. the bcnt field of the block register defines the number of blocks to transfer (from 1 to 65535 blocks). programming the value 0 in the bcnt field co rresponds to an infinite block transfer. 37.7.3 read operation the following flowchart shows how to read a single block with or without use of pdc facilities. in this example (see figure 37-10 ), a polling method is used to wait for the end of read. similarly, the user can configure the interrupt enable register (mci_ier) to trigger an interrupt at the end of read.
635 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 37-10. read functional flow diagram notes: 1. it is assumed that this co mmand has been correctly sent (see figure 37-9 ). 2. this field is also accessible in the mci block register (mci_blkr). read status register mci_sr send select/deselect_card command (1) to select the card send set_blocklen command (1) read with pdc reset the pdcmode bit mci_mr &= ~pdcmode set the block length (in bytes) mci_mr |= (blocklenght <<16) (2) set the block count (if necessary) mci_blkr |= (blockcount << 0) number of words to read = 0 ? poll the bit rxrdy = 0? read data = mci_rdr number of words to read = number of words to read -1 send read_single_block command (1) ye s set the pdcmode bit mci_mr |= pdcmode set the block length (in bytes) mci_mr |= (blocklength << 16) (2) set the block count (if necessary) mci_blkr |= (blockcount << 0) configure the pdc channel mci_rpr = data buffer address mci_rcr = blocklength/4 mci_ptcr = rxten send read_single_block command (1) read status register mci_sr poll the bit endrx = 0? ye s return return ye s no no no ye s no number of words to read = blocklength/4
636 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 37.7.4 write operation in write operation, the mci mode register (mc i_mr) is used to define the padding value when writing non-multiple block size. if the bit pdcpad v is 0, then 0x00 value is used when padding data, otherwise 0xff is used. if set, the bit pdcmode enables pdc transfer. the following flowchart shows how to write a singl e block with or without use of pdc facilities (see figure 37-11 ). polling or interrupt method can be used to wait for the en d of write according to the contents of the interrupt mask register (mci_imr).
637 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 37-11. write functional flow diagram notes: 1. it is assumed that this co mmand has been correctly sent (see figure 37-9 ). 2. this field is also accessible in the mci block register (mci_blkr). send select/deselect_card command (1) to select the card send set_blocklen command (1) write using pdc send write_single_block command (1) configure the pdc channel mci_tpr = data buffer address to write mci_tcr = blocklength/4 send write_single_block command (1) read status register mci_sr poll the bit notbusy= 0? yes no yes no read status register mci_sr number of words to write = 0 ? poll the bit txrdy = 0? mci_tdr = data to write number of words to write = number of words to write -1 yes return no yes no number of words to write = blocklength/4 mci_ptcr = txten reset the pdcmode bit mci_mr &= ~pdcmode set the block length (in bytes) mci_mr |= (blocklenght <<16) (2) set the block count (if necessary) mci_blkr |= (blockcount << 0) set the pdcmode bit mci_mr |= pdcmode set the block length (in bytes) mci_mr |= (blocklength << 16) (2) set the block count (if necessary) mci_blkr |= (blockcount << 0) return
638 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary the following flowchart, ( figure 37-12 ) shows how to manage a multiple write block transfer with the pdc. polling or interrupt method can be used to wait for the end of write according to the contents of the interrupt mask register (mci_imr). figure 37-12. multiple write functi onal flow diagram notes: 1. it is assumed that this command has been correctly sent (see figure 37-9 ). 2. this field is also accessible in the mci block register (mci_blkr). configure the pdc channel mci_tpr = data buffer address to write mci_tcr = blocklength/4 send write_multiple_block command (1) read status register mci_sr poll the bit blke = 0? ye s mci_ptcr = txten set the pdcmode bit mci_mr |= pdcmode set the block length (in bytes) mci_mr |= (blocklength << 16) (2) set the block count (if necessary) mci_blkr |= (blockcount << 0) no poll the bit notbusy = 0? ye s return no send stop_transmission command (1) send select/deselect_card command (1) to select the card send set_blocklen command (1)
639 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 37.8 sd/sdio card operations the multimedia card interface allows processing of sd memory (secure digital memory card) and sdio (sd input output) card commands. sd/sdio cards are based on the multi media card (mmc) format, but are physically slightly thicker and feature higher data transfer rates, a lock switch on the side to prevent accidental overwriting and security featur es. the physical form factor, pin assignment and data transfer protocol are forward-compatible with the multimedia card with some additions. sd slots can actually be used for more than flash memory ca rds. devices that support sdio can use small devices designed for the sd form factor, such as gps receivers, wi-fi or bluetooth adapters, modems, barcode readers, irda adapters, fm radio tuners, rfid readers, digital cameras and more. sd/sdio is covered by numerous patents and trademarks, and licensing is only available through the secure digital card association. the sd/sdio card communication is based on a 9-pin interface (clock, command, 4 x data and 3 x power lines). the communication protocol is defined as a part of this specification. the main difference between the sd/sdio card and t he multimedia card is the initialization process. the sd/sdio card register (mci _sdcr) allows selection of the card slot and the data bus width. the sd/sdio card bus allows dynamic configur ation of the number of data lines. after power up, by default, the sd/sdio card uses only dat0 for data transfer. after initialization, the host can change the bus width (number of active data lines). 37.8.1 sdio data transfer type sdio cards may transfer data in either a multi-byte (1 to 512 bytes) or an optional block format (1 to 511 blocks), while the sd memory cards are fixed in the block transfer mode. the trtyp field in the mci command register (mci_cmdr) allows to choose between sdio byte or sdio block transfer. the number of bytes/blocks to transfer is set through the bcnt field in the mci block register (mci_blkr). in sdio block mode, the field blkl en must be set to the data block size while this field is not used in sdio byte mode. an sdio card can have multiple i/o or combined i/o and memo ry (called combo card). within a multi-function sdio or a combo card, there are multiple devices (i/o and memory) that share access to the sd bus. in order to allow the sharing of access to the host among multiple devices, sdio and combo cards can implement the optional concept of suspend/resume (refer to the sdio specification for more details). to send a suspend or a resume command, the host must set the sdio special command field (iospcmd) in the mci command register. 37.8.2 sdio interrupts each function within an sdio or combo card may implement interrupts (refer to the sdio specification for more details). in order to allow the sdio card to interrupt the host, an interrupt function is added to a pin on the dat[1] line to signal the card?s interrupt to the host. an sdio interrupt on each slot can be enabled through the mci interrupt enable register. the sdio interrupt is sampled regardless of the currently selected slot.
640 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 37.9 multimedia card inte rface (mci) user interface note: 1. the response register can be read by n accesses at the same mci_rspr or at consecutive addresses (0x20 to 0x2c). n depends on the size of the response. table 37-6. register mapping offset register register name access reset 0x00 control register mci_cr write-only ? 0x04 mode register mci_mr read-write 0x0 0x08 data timeout register mci_dtor read-write 0x0 0x0c sd/sdio card register mci_sdcr read-write 0x0 0x10 argument register mci_argr read-write 0x0 0x14 command register mci_cmdr write-only ? 0x18 block register mci_blkr read-write 0x0 0x1c reserved ? ? ? 0x20 response register (1) mci_rspr read-only 0x0 0x24 response register (1) mci_rspr read-only 0x0 0x28 response register (1) mci_rspr read-only 0x0 0x2c response register (1) mci_rspr read-only 0x0 0x30 receive data register mci_rdr read-only 0x0 0x34 transmit data register mci_tdr write-only ? 0x38 - 0x3c reserved ? ? ? 0x40 status register mci_sr read-only 0xc0e5 0x44 interrupt enable register mci_ier write-only ? 0x48 interrupt disable register mci_idr write-only ? 0x4c interrupt mask register mci_imr read-only 0x0 0x50-0xfc reserved ? ? ? 0x100-0x124 reserved for the pdc ? ? ?
641 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 37.9.1 mci control register name: mci_cr address: 0xfffa8000 access type: write-only ? mcien: multi-media interface enable 0 = no effect. 1 = enables the multi-media interface if mcdis is 0. ? mcidis: multi-media interface disable 0 = no effect. 1 = disables the multi-media interface. ? pwsen: power save mode enable 0 = no effect. 1 = enables the power saving mode if pwsdis is 0. warning: before enabling this mode, the user must set a value different from 0 in the pwsdiv field (mode register mci_mr). ? pwsdis: power save mode disable 0 = no effect. 1 = disables the power saving mode. ? swrst: software reset 0 = no effect. 1 = resets the mci. a software triggered hardware reset of the mci interface is performed. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 swrst ? ? ? pwsdis pwsen mcidis mcien
642 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 37.9.2 mci mode register name: mci_mr address: 0xfffa8004 access type: read/write ? clkdiv: clock divider multimedia card interface clock (mcck or mci_ck) is master clock (mck) divided by (2*(clkdiv+1)). ? pwsdiv: power saving divider multimedia card interface clock is divided by 2 (pwsdiv) + 1 when entering power saving mode. warning: this value must be different from 0 before enabling the power save mode in the mci_cr (mci_pwsen bit). ? rdproof read proof enable enabling read proof allows to stop the mci clock during read acce ss if the internal fifo is full. this will guarantee data integrity, no t bandwidth. 0 = disables read proof. 1 = enables read proof. ? wrproof write proof enable enabling write proof allows to stop the mci clock during write ac cess if the internal fifo is full. this will guarantee data integrity, no t bandwidth. 0 = disables write proof. 1 = enables write proof. ? pdcfbyte: pdc force byte transfer enabling pdc force byte transfer allows the pdc to manage with internal byte transfers, so that transfer of blocks with a size different from modulo 4 can be supported. warning: blklen value depends on pdcfbyte. 0 = disables pdc force byte transfer. pdc type of transfer are in words. 1 = enables pdc force byte transfer. pdc type of transfer are in bytes. ? pdcpadv: pdc padding value 0 = 0x00 value is used when padding data in write transfer (not only pdc transfer). 1 = 0xff value is used when padding data in write transfer (not only pdc transfer). 31 30 29 28 27 26 25 24 blklen 23 22 21 20 19 18 17 16 blklen 15 14 13 12 11 10 9 8 pdcmode pdcpadv pdcfbyte wrproof rdproof pwsdiv 76543210 clkdiv
643 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? pdcmode: pdc-oriented mode 0 = disables pdc transfer 1 = enables pdc transfer. in this case, unre and ovre flags in the mci mode register (mci_sr) are deactivated after the pdc transfer has been completed. ? blklen: data block length this field determines the size of the data block. this field is also accessible in the mci block register (mci_blkr). bits 16 and 17 must be set to 0 if pdcfbyte is disabled. note: in sdio byte mode, blklen field is not used.
644 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 37.9.3 mci data timeout register name: mci_dtor address: 0xfffa8008 access type: read/write ? dtocyc: data timeout cycle number defines a number of master clock cycles with dtomul. ? dtomul: data timeout multiplier these fields determine the maximum number of master clock cycles that the mci waits between two data block transfers. it equals (dtocyc x multiplier). multiplier is defined by dtomul as shown in the following table: if the data time-out set by dtocyc and dtomul has been exceeded, the data time-out error flag (dtoe) in the mci status register (mci_sr) raises. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? dtomul dtocyc dtomul multiplier 0001 00116 010128 011256 1 0 0 1024 1 0 1 4096 1 1 0 65536 1 1 1 1048576
645 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 37.9.4 mci sdcard/sdio register name: mci_sdcr address: 0xfffa800c access type: read/write ? sdcsel: sdcard/sdio slot ? sdcbus: sdcard/sdio bus width 0 = 1-bit data bus 1 = 4-bit data bus 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 sdcbus????? sdcsel sdcsel sdcard/sdio slot 00 slot a is selected . 01 slot b selected 10 reserved 11 reserved
646 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 37.9.5 mci argument register name: mci_argr address: 0xfffa8010 access type: read/write ? arg: command argument 31 30 29 28 27 26 25 24 arg 23 22 21 20 19 18 17 16 arg 15 14 13 12 11 10 9 8 arg 76543210 arg
647 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 37.9.6 mci command register name: mci_cmdr address: 0xfffa8014 access type: write-only this register is write-protecte d while cmdrdy is 0 in mci_sr. if an interrupt command is sen t, this register is only write- able by an interrupt response (field spcmd). this means that the current command execution cannot be interrupted or modified. ? cmdnb: command number multimedia card bus command numbers are defined in the multimedia card specification. ? rsptyp: response type ? spcmd: special command 31 30 29 28 27 26 25 24 ?????? iospcmd 23 22 21 20 19 18 17 16 ? ? trtyp trdir trcmd 15 14 13 12 11 10 9 8 ? ? ? maxlat opdcmd spcmd 76543210 rsptyp cmdnb rsp response type 0 0 no response. 0 1 48-bit response. 1 0 136-bit response. 1 1 reserved. spcmd command 0 0 0 not a special cmd. 001 initialization cmd: 74 clock cycles for in itialization sequence. 010 synchronized cmd: wait for the end of the current data block transfer before sending the pending command. 011reserved. 100 interrupt command: corresponds to the interrupt mode (cmd40). 101 interrupt response: corresponds to the interrupt mode (cmd40).
648 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? opdcmd: open drain command 0 = push pull command 1 = open drain command ? maxlat: max latency for command to response 0 = 5-cycle max latency 1 = 64-cycle max latency ? trcmd: transfer command ? trdir: transfer direction 0 = write 1 = read ? trtyp: transfer type ? iospcmd: sdio special command trcmd transfer type 0 0 no data transfer 0 1 start data transfer 1 0 stop data transfer 11reserved trtyp transfer type 0 0 0 mmc/sdcard single block 0 0 1 mmc/sdcard multiple block 010mmc stream 0 1 1 reserved 1 0 0 sdio byte 101sdio block 1 1 0 reserved 1 1 1 reserved iospcmd sdio special command type 0 0 not a sdio special command 0 1 sdio suspend command 1 0 sdio resume command 11reserved
649 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 37.9.7 mci block register name: mci_blkr address: 0xfffa8018 access type: read/write ? bcnt: mmc/sdio block count - sdio byte count this field determines the number of data byte(s) or block(s) to transfer. the transfer data type and the authorized values for bcnt field are determined by the trtyp field in the mci command register (mci_cmdr): warning: in sdio byte and block modes, writing to the 7 last bi ts of bcnt field, is forbidden and may lead to unpredict- able results. ? blklen: data block length this field determines the size of the data block. this field is also accessible in the mci mode register (mci_mr). bits 16 and 17 must be set to 0 if pdcfbyte is disabled. note: in sdio byte mode, blklen field is not used. 31 30 29 28 27 26 25 24 blklen 23 22 21 20 19 18 17 16 blklen 15 14 13 12 11 10 9 8 bcnt 76543210 bcnt trtyp type of transfer bcnt authorized values 0 0 1 mmc/sdcard multiple block from 1 to 65535: value 0 corresponds to an infinite block transfer. 1 0 0 sdio byte from 1 to 512 bytes: value 0 corresponds to a 512-byte transfer. values from 0x200 to 0xffff are forbidden. 1 0 1 sdio block from 1 to 511 blocks: value 0 corresponds to an infinite block transfer. values from 0x200 to 0xffff are forbidden. other values - reserved.
650 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 37.9.8 mci response register name: mci_rspr address: 0xfffa8020 access type: read-only ? rsp: response note: 1. the response register can be read by n accesses at th e same mci_rspr or at consecutive addresses (0x20 to 0x2c). n depends on the size of the response. 31 30 29 28 27 26 25 24 rsp 23 22 21 20 19 18 17 16 rsp 15 14 13 12 11 10 9 8 rsp 76543210 rsp
651 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 37.9.9 mci receive data register name: mci_rdr address: 0xfffa8030 access type: read-only ? data: data to read 37.9.10 mci transmit data register name: mci_tdr address: 0xfffa8034 access type: write-only ? data: data to write 31 30 29 28 27 26 25 24 data 23 22 21 20 19 18 17 16 data 15 14 13 12 11 10 9 8 data 76543210 data 31 30 29 28 27 26 25 24 data 23 22 21 20 19 18 17 16 data 15 14 13 12 11 10 9 8 data 76543210 data
652 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 37.9.11 mci status register name: mci_sr address: 0xfffa8040 access type: read-only ? cmdrdy: command ready 0 = a command is in progress. 1 = the last command has been sent. cleared when writing in the mci_cmdr. ? rxrdy: receiver ready 0 = data has not yet been received since the last read of mci_rdr. 1 = data has been received since the last read of mci_rdr. ? txrdy: transmit ready 0= the last data written in mci_tdr has not yet been transferred in the shift register. 1= the last data written in mci_tdr has been transferred in the shift register. ? blke: data block ended this flag must be used only for write operations. 0 = a data block transfer is not yet finished. cleared when reading the mci_sr. 1 = a data block transfer has ended, including the crc16 status transmission. in pdc mode (pdcmode=1), the flag is set when the crc status of the last block has been transmitted (txbufe already set). otherwise (pdcmode=0), the flag is set for each transmitted crc status. refer to the mmc or sd sp ecification for more details concerning the crc status. ? dtip: data transfer in progress 0 = no data transfer in progress. 1 = the current data tran sfer is still in progress, including crc16 calculatio n. cleared at the end of the crc16 calculation. ? notbusy: mci not busy this flag must be used only for write operations. a block write operation uses a simple busy signalling of the write operat ion duration on the data (dat0) line: during a data transfer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling down the dat a 31 30 29 28 27 26 25 24 unreovre?????? 23 22 21 20 19 18 17 16 ? dtoe dcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 txbuferxbuff????sdioirqbsdioirqa 76543210 endtx endrx notbusy dtip blke txrdy rxrdy cmdrdy
653 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary line (dat0) to low. the card stops pulling down the data line as soon as at least one receive buffer for the defined data transfer block length becomes free. the notbusy flag allows to deal with these different states. 0 = the mci is not ready for new data transfer. cleared at the end of the card response. 1 = the mci is ready for new data transfer. set when the busy state on the data line has ended. this corresponds to a free internal data receive buffer of the card. refer to the mmc or sd specification for more details concerning the busy behavior. ? endrx: end of rx buffer 0 = the receive counter register has not reached 0 since the last write in mci_rcr or mci_rncr. 1 = the receive counter register has reached 0 since the last write in mci_rcr or mci_rncr. ? endtx: end of tx buffer 0 = the transmit counter register has not reached 0 since the last write in mci_tcr or mci_tncr. 1 = the transmit counter register has reached 0 since the last write in mci_tcr or mci_tncr. note: blke and notbusy flags can be used to check that the data has been successfully transmitted on the data lines and not only transferred from the pdc to the mci controller. ? rxbuff: rx buffer full 0 = mci_rcr or mci_rncr has a value other than 0. 1 = both mci_rcr and mci_rncr have a value of 0. ? txbufe: tx buffer empty 0 = mci_tcr or mci_tncr has a value other than 0. 1 = both mci_tcr and mci_tncr have a value of 0. note: blke and notbusy flags can be used to check that the data has been successfully transmitted on the data lines and not only transferred from the pdc to the mci controller. ? rinde: response index error 0 = no error. 1 = a mismatch is detected between the command index sent and the response index received. cleared when writing in the mci_cmdr. ? rdire: response direction error 0 = no error. 1 = the direction bit from card to host in the response has not been detected. ? rcrce: response crc error 0 = no error. 1 = a crc7 error has been detected in the response. cleared when writing in the mci_cmdr. ? rende: response end bit error 0 = no error. 1 = the end bit of the response has not been detected. cleared when writing in the mci_cmdr.
654 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? rtoe: response time-out error 0 = no error. 1 = the response time-out set by maxlat in the mci_cmdr has been exceeded. cleared when writing in the mci_cmdr. ? dcrce: data crc error 0 = no error. 1 = a crc16 error has been detected in the last data block. cleared by reading in the mci_sr register. ? dtoe: data time-out error 0 = no error. 1 = the data time-out set by dtocyc and dtomul in mci_dtor has been exceeded. cleared by reading in the mci_sr register. ? ovre: overrun 0 = no error. 1 = at least one 8-bit received data has been lost (not read). cleared when sending a new data transfer command. ? unre: underrun 0 = no error. 1 = at least one 8-bit data has been sent without valid inform ation (not written). cleared when sending a new data transfer command. ? sdioirqa: sdio interrupt for slot a 0 = no interrupt detected on sdio slot a. 1 = a sdio interrupt on slot a has reached. cleared when reading the mci_sr. ? sdioirqb: sdio interrupt for slot b 0 = no interrupt detected on sdio slot b. 1 = a sdio interrupt on slot b has reached. cleared when reading the mci_sr. ? rxbuff: rx buffer full 0 = mci_rcr or mci_rncr has a value other than 0. 1 = both mci_rcr and mci_rncr have a value of 0. ? txbufe: tx buffer empty 0 = mci_tcr or mci_tncr has a value other than 0. 1 = both mci_tcr and mci_tncr have a value of 0.
655 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 37.9.12 mci interrupt enable register name: mci_ier address: 0xfffa8044 access type: write-only ? cmdrdy: command ready interrupt enable ? rxrdy: receiver ready interrupt enable ? txrdy: transmit ready interrupt enable ? blke: data block ended interrupt enable ? dtip: data transfer in progress interrupt enable ? notbusy: data not busy interrupt enable ? endrx: end of receive buffer interrupt enable ? endtx: end of transmit buffer interrupt enable ? sdioirqa: sdio interrupt for slot a interrupt enable ? sdioirqb: sdio interrupt for slot b interrupt enable ? rxbuff: receive buffer full interrupt enable ? txbufe: transmit buffer empty interrupt enable ? rinde: response index error interrupt enable ? rdire: response direction error interrupt enable ? rcrce: response crc error interrupt enable ? rende: response end bit error interrupt enable ? rtoe: response time-out error interrupt enable ? dcrce: data crc error interrupt enable ? dtoe: data time-out error interrupt enable 31 30 29 28 27 26 25 24 unreovre?????? 23 22 21 20 19 18 17 16 ? dtoe dcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 txbuferxbuff????sdioirqbsdioirqa 76543210 endtx endrx notbusy dtip blke txrdy rxrdy cmdrdy
656 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? ovre: overrun interrupt enable ? unre: underrun interrupt enable 0 = no effect. 1 = enables the corresponding interrupt.
657 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 37.9.13 mci interrupt disable register name: mci_idr address: 0xfffa8048 access type: write-only ? cmdrdy: command ready interrupt disable ? rxrdy: receiver ready interrupt disable ? txrdy: transmit ready interrupt disable ? blke: data block ended interrupt disable ? dtip: data transfer in progress interrupt disable ? notbusy: data not busy interrupt disable ? endrx: end of receive buffer interrupt disable ? endtx: end of transmit buffer interrupt disable ? sdioirqa: sdio interrupt for slot a interrupt disable ? sdioirqb: sdio interrupt for slot b interrupt disable ? rxbuff: receive buffer full interrupt disable ? txbufe: transmit buffer empty interrupt disable ? rinde: response index error interrupt disable ? rdire: response direction error interrupt disable ? rcrce: response crc error interrupt disable ? rende: response end bit error interrupt disable ? rtoe: response time-out error interrupt disable ? dcrce: data crc error interrupt disable ? dtoe: data time-out error interrupt disable 31 30 29 28 27 26 25 24 unreovre?????? 23 22 21 20 19 18 17 16 ? dtoe dcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 txbuferxbuff????sdioirqbsdioirqa 76543210 endtx endrx notbusy dtip blke txrdy rxrdy cmdrdy
658 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? ovre: overrun interrupt disable ? unre: underrun interrupt disable 0 = no effect. 1 = disables the corresponding interrupt.
659 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 37.9.14 mci interrupt mask register name: mci_imr address: 0xfffa804c access type: read-only ? cmdrdy: command ready interrupt mask ? rxrdy: receiver ready interrupt mask ? txrdy: transmit ready interrupt mask ? blke: data block ended interrupt mask ? dtip: data transfer in progress interrupt mask ? notbusy: data not busy interrupt mask ? endrx: end of receive buffer interrupt mask ? endtx: end of transmit buffer interrupt mask ? sdioirqa: sdio interrupt for slot a interrupt mask ? sdioirqb: sdio interrupt for slot b interrupt mask ? rxbuff: receive buffer full interrupt mask ? txbufe: transmit buffer empty interrupt mask ? rinde: response index error interrupt mask ? rdire: response direction error interrupt mask ? rcrce: response crc error interrupt mask ? rende: response end bit error interrupt mask ? rtoe: response time-out error interrupt mask ? dcrce: data crc error interrupt mask ? dtoe: data time-out error interrupt mask 31 30 29 28 27 26 25 24 unreovre?????? 23 22 21 20 19 18 17 16 ? dtoe dcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 txbuferxbuff????sdioirqbsdioirqa 76543210 endtx endrx notbusy dtip blke txrdy rxrdy cmdrdy
660 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? ovre: overrun interrupt mask ? unre: underrun interrupt mask 0 = the corresponding interrupt is not enabled. 1 = the corresponding interrupt is enabled.
661 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38. ethernet mac 10/100 (emac) 38.1 description the emac module implements a 10/100 ethernet mac compatible with the ieee 802.3 stan- dard using an address checker, statistics and co ntrol registers, receive and transmit blocks, and a dma interface. the address checker recognizes four specific 48-bit addresses and contains a 64-bit hash regis- ter for matching multicast and unicast addresses. it can recognize the broadcast address of all ones, copy all frames, and act on an external address match signal. the statistics register block contains register s for counting various ty pes of event associated with transmit and receive operations. these register s, along with the status words stored in the receive buffer list, enable software to generate network management statistics compatible with ieee 802.3. 38.2 block diagram figure 38-1. emac block diagram apb slave register interface dma interface address checker statistics registers control registers ethernet receive ethernet transmit mdio mii/rmii rx fifo tx fifo ahb master
662 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.3 functional description the macb has several clock domains: ? system bus clock (ahb and apb): dma and register blocks ? transmit clock: transmit block ? receive clock: receive and address checker blocks the only system constraint is 160 mhz for the system bus clock, above which mdc would toggle at above 2.5 mhz. the system bus clock must run at least as fast as the receive clock and transmit clock (25 mhz at 100 mbps, and 2.5 mhz at 10 mbps). figure 38-1 illustrates the different blocks of the emac module. the control registers drive the mdio interface, setup up dma activity, start frame transmission and select modes of operation such as full- or half-duplex. the receive block checks for valid preamble, fcs, alignment and length, and presents received frames to the address checking block and dma interface. the transmit block takes data from the dma interface, adds preamble and, if necessary, pad and fcs, and transmits data according to the csma/cd (carrier sense multiple access with col- lision detect) protocol. the start of transmission is deferred if crs (carrier sense) is active. if col (collision) becomes active during transmission, a jam se quence is asserted and the transmission is retried after a random back off. crs and col have no effect in full duplex mode. the dma block connects to external memory thro ugh its ahb bus interface. it contains receive and transmit fifos for buffering frame data. it loads the transmit fifo and empties the receive fifo using ahb bus master operations. receive da ta is not sent to memory until the address checking logic has determined that the frame should be copied. receive or transmit frames are stored in one or more buffers. receive buffers have a fixed length of 128 bytes. transmit buffers range in length between 0 and 2047 bytes, and up to 128 buffers are permitted per frame. the dma block manages the transmit and receive framebuffer queues. these queues can hold mul- tiple frames. 38.3.1 clock synchronization module in the emac requires that the bus clock (hclk) runs at the speed of the macb_tx/rx_clk at least, which is 25 mhz at 100 mbps, and 2.5 mhz at 10 mbps. 38.3.2 memory interface frame data is transferred to and from the emac through the dma interface. all transfers are 32- bit words and may be single accesses or bursts of 2, 3 or 4 words. burst accesses do not cross sixteen-byte boundaries. bursts of 4 words are the default data transfer; single accesses or bursts of less than four words may be used to transfer data at the beginning or the end of a buffer. the dma controller performs six types of operation on the bus. in order of priority, these are: 1. receive buffer manager write 2. receive buffer manager read 3. transmit data dma read
663 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 4. receive data dma write 5. transmit buffer manager read 6. transmit buffer manager write 38.3.2.1 fifo the fifo depths are 1 28 bytes for receive and 1 28 bytes for transmit and are a function of the system clock speed, memory latency and network speed. data is typically transferred into and out of the fifos in bursts of four words. for receive, a bus request is asserted when the fifo contains f our words and has space for 28 more. for transmit, a bus request is generated when there is space for four words, or when there is space for 27 words if the next transfer is to be only one or two words. thus the bus latency must be less than the time it takes to load the fifo and transmit or receive three words (112 bytes) of data. at 100 mbit/s, it takes 8960 ns to transmit or receive 112 bytes of data. in addition, six master clock cycles should be allowed for data to be loaded from the bus and to propagate through the fifos. for a 133 mhz master clock this takes 45 ns, making the bus latency requirement 8915 ns. 38.3.2.2 receive buffers received frames, including crc/fc s optionally, are written to receive buffers stored in mem- ory. each receive buffer is 128 bytes long. the start location for each receive buffer is stored in memory in a list of receive buffer descriptors at a location pointed to by the receive buffer queue pointer register. the receive buffer start location is a word address. for the first buffer of a frame, the start location can be offset by up to three bytes depending on the value written to bits 14 and 15 of the network configuration register. if the start location of the buffer is offset the available length of the first buffer of a frame is reduced by the corresponding number of bytes. each list entry consists of two words, the first being the address of the receive buffer and the second being the receive status. if the length of a receive frame exceeds the buffer length, the status word for the used buffer is written with zer oes except for the ?start of frame? bit and the offset bits, if appropriate. bit zero of the address field is written to one to show the buffer has been used. the receive buffer manager then reads the location of the next receive buffer and fills that with receive frame data. the final buff er descriptor status word contains the complete frame status. refer to table 38-1 for details of the receive buffer descriptor list. table 38-1. receive buffer descriptor entry bit function word 0 31:2 address of beginning of buffer 1 wrap - marks last descriptor in receive buffer descriptor list. 0 ownership - needs to be zero for the emac to write data to the receive buffer. the emac sets this to one once it has successfully written a frame to memory. software has to clear this bit before the buffer can be used again. word 1 31 global all ones broadcast address detected 30 multicast hash match
664 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary to receive frames, the buffer descriptors must be initialized by writing an appropriate address to bits 31 to 2 in the first word of each list entry. bit zero must be written with zero. bit one is the wrap bit and indicates the last entry in the list. the start location of the receive buffer descriptor list must be written to the receive buffer queue pointer register before setting the receive enable bit in the network control register to enable receive. as soon as the receive block starts writing received frame data to the receive fifo, the receive buffer manager reads the first receive buffer location pointed to by the receive buffer queue pointer register. if the filter block then indicates that the frame should be copied to memory, the receive data dma operation starts writing data into the receive buffer. if an error occurs, the buffer is recov- ered. if the current buffer pointer has its wrap bit set or is the 1024 th descriptor, the next receive buffer location is read from the beginning of the receive descriptor list. otherwise, the next receive buffer location is read from the next word in memory. there is an 11-bit counter to count out the 2048 word locations of a maximum length, receive buffer descriptor list. this is added with the valu e originally written to the receive buffer queue pointer register to produce a pointer into the list. a read of the receive buffer queue pointer reg- ister returns the pointer value, which is the queue entry currently being accessed. the counter is reset after receive status is written to a descript or that has its wrap bit set or rolls over to zero after 1024 descriptors have been accessed. the value written to the receive buffer pointer regis- 29 unicast hash match 28 external address match 27 reserved for future use 26 specific address register 1 match 25 specific address register 2 match 24 specific address register 3 match 23 specific address register 4 match 22 type id match 21 vlan tag detected (i.e., type id of 0x8100) 20 priority tag detected (i.e., type id of 0x8100 and null vlan identifier) 19:17 vlan priority (only valid if bit 21 is set) 16 concatenation format indicator (cfi) bit (only valid if bit 21 is set) 15 end of frame - when set the buffer contains the end of a frame. if end of frame is no t set, then the only other valid status are bits 12, 13 and 14. 14 start of frame - when set the buffer contains the start of a frame. if both bits 15 a nd 14 are set, then the buffer contains a whole frame. 13:12 receive buffer offset - indicates the number of bytes by which the data in the first buffer is offset from the word address. updated with the current values of the network configuration register. if jum bo frame mode is enabled through bit 3 of the network configuration register, then bits 13: 12 of the receive buffer descriptor entry are used to indicate bits 13:12 of the frame length. 11:0 length of frame including fcs (if selected). bits 13:12 are also used if jumbo frame mode is selected. table 38-1. receive buffer descrip tor entry (continued) bit function
665 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ter may be any word-aligned address, provided that there are at least 2048 word locations available between the pointer and the top of the memory. section 3.6 of the amba 2.0 specification states that bursts should not cross 1k boundaries. as receive buffer manager writes are bursts of two words, to ensure that this does not occur, it is best to write the pointer register with the least three significant bits set to zero. as receive buffers are used, the receive buffer manager sets bit zero of the first word of the descriptor to indicate used . if a receive error is detected the receive buffer currently being written is recovered. previ- ous buffers are not recovered. software should search through the used bits in the buffer descriptors to find out how many frames have been received. it should be checking the start-of- frame and end-of-frame bits, and not rely on the value returned by the receive buffer queue pointer register which changes contin uously as more buffers are used. for crc errored frames, excessive length frames or length field mismatched frames, all of which are counted in the statistics registers, it is possible that a frame fragment might be stored in a sequence of receive buffers. software can detect this by looking for start of frame bit set in a buffer following a buffer with no end of frame bit set. for a properly working ethernet system, there should be no excessively long frames or frames greater than 128 bytes with crc/ fcs errors. collision fragments are less than 128 bytes long. therefore, it is a rare occurrence to find a frame fragment in a receive buffer. if bit zero is set when the receive buffer manager reads the location of the receive buffer, then the buffer has already been used and cannot be used again until software has processed the frame and cleared bit zero. in this case, the dma block sets the buffer not available bit in the receive status register and triggers an interrupt. if bit zero is set when the receive buffer manager reads the location of the receive buffer and a frame is being received, the frame is discarded and the receive resource error statistics register is incremented. a receive overrun condition occurs when bus was not granted in time or because hresp was not ok (bus error). in a receive overrun conditi on, the receive overrun interrupt is asserted and the buffer currently being written is recovered. the next frame received with an address that is recognized reuses the buffer. if bit 17 of the network configuration register is set, the fcs of received frames shall not be cop- ied to memory. the frame length indicated in the receive status field shall be reduced by four bytes in this case. 38.3.2.3 transmit buffer frames to be transmitted are stored in one or more transmit buffers. transmit buffers can be between 0 and 2047 bytes long, so it is possible to transmit frames longer than the maximum length specified in ieee standard 802.3. zero length buffers are allowed. the maximum number of buffers permitted for each transmit frame is 128. the start location for each transmit buffer is stored in memory in a list of transmit buffer descrip- tors at a location pointed to by the transmit buffer queue pointer register. each list entry consists of two words, the first being the byte address of the transmit buffer and the second containing the transmit control and status. frames can be transmitted with or without automatic crc gen- eration. if crc is automatically generated, pad is also automatically generated to take frames to a minimum length of 64 bytes. table 38-2 on page 666 defines an entry in the transmit buffer descriptor list. to transmit frames, the buffer descriptors must be initialized by writing an appro- priate byte address to bits 31 to 0 in the first word of each list entry. the second transmit buffer
666 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary descriptor is initialized with control information that indicates the length of the buffer, whether or not it is to be transmitted wit h crc and whether the bu ffer is the last bu ffer in the frame. after transmission, the control bits are written back to the second word of the first buffer along with the ?used? bit and other status information. bit 31 is the ?used? bit which must be zero when the control word is read if transmission is to happen. it is written to one when a frame has been transmitted. bits 27, 28 and 29 indicate various transmit error conditions. bit 30 is the ?wrap? bit which can be set for any buffer within a frame. if no wrap bit is encountered after 1024 descrip- tors, the queue pointer rolls over to the start in a similar fashion to the receive queue. the transmit buffer queue pointer register must not be written while transmit is active. if a new value is written to the transmit buffer queue pointer register, the queue pointer resets itself to point to the beginning of the new queue. if transmit is disabled by writing to bit 3 of the network control, the transmit buffer queue pointer register resets to point to the beginning of the transmit queue. note that disabling receive does not have the same effect on the receive queue pointer. once the transmit queue is init ialized, transmit is activate d by writing to bit 9, the transmit start bit of the network control register. transmit is halted when a buffer descriptor with its used bit set is read, or if a transmit error occurs, or by writ ing to the transmit halt bit of the network control register. (transmission is suspended if a pause frame is received while the pause enable bit is set in the network configuration register.) rewrit ing the start bit while transmission is active is allowed. transmission control is implemented with a tx_go variable which is readable in the transmit sta- tus register at bit location 3. the tx_go variable is reset when: ? transmit is disabled ? a buffer descriptor with its ownership bit set is read ? a new value is written to the transmit buffer queue pointer register ? bit 10, tx_halt, of the network control register is written ? there is a transmit error such as too many retries or a transmit underrun. to set tx_go, write to bit 9, tx_start, of the network control register. transmit halt does not take effect until any ongoing transmit finishes. if a collision occurs du ring transmission of a multi-buf- fer frame, transmission automatically restarts from the first buffer of the frame. if a ?used? bit is read midway through transmission of a multi-buffer frame, this is treated as a transmit error. transmission stops, tx_er is asserted and the fcs is bad. if transmission stops due to a transmit error, the transmit queue pointer resets to point to the beginning of the transmit queue. software needs to re-initialize the transmit queue after a trans- mit error. if transmission stops due to a ?used? bit being read at the start of the frame, the transmission queue pointer is not reset and transmit starts from the same transmit buffer descriptor when the transmit start bit is written table 38-2. transmit buffer descriptor entry bit function word 0 31:0 byte address of buffer word 1
667 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.3.3 transmit block this block transmits frames in accordance wi th the ethernet ieee 802.3 csma/cd protocol. frame assembly starts by adding preamble and the start frame delimiter. data is taken from the transmit fifo a word at a time. data is transmi tted least significant nibble first. if necessary, padding is added to increase the frame length to 60 bytes. crc is calculated as a 32-bit polyno- mial. this is inverted and appended to the end of the frame, taking the frame length to a minimum of 64 bytes. if the no crc bit is set in the second word of the last buffer descriptor of a transmit frame, neither pad nor crc are appended. in full-duplex mode, frames are transmitted immediately. back-to-back frames are transmitted at least 96 bit times apart to guarantee the interframe gap. in half-duplex mode, the transmitter checks carrier sense. if asserted, it waits for it to de-assert and then starts transmission afte r the interframe gap of 96 bit times. if the collision signal is asserted during transmission, the transmitter transmits a jam sequence of 32 bits taken from the data register and then retry transmission after the back off time has elapsed. the back-off time is based on an xor of the 10 least significant bits of the data coming from the transmit fifo and a 10-bit pseudo random number generator. the number of bits used depends on the number of collisions seen . after the first collisi on, 1 bit is used, afte r the second 2, and so on up to 10. above 10, all 10 bits are used. an error is indicated and no further attempts are made if 16 attempts cause collisions. if transmit dma underruns, bad crc is automa tically appended using the same mechanism as jam insertion and the tx_er signal is asserted. for a properly configured system, this should never happen. if the back pressure bit is set in the network control register in half duplex mode, the transmit block transmits 64 bits of data, which can consist of 16 nibbles of 1011 or in bit-rate mode 64 1s, 31 used. needs to be zero for the emac to read data from the tran smit buffer. the emac sets this to one for the first buffer of a frame once it has been successfully transmitted. software has to clear this bit before the buffer can be used again. note: this bit is only set for the first buffer in a frame unlike receive where all buffers have the used bit set once used. 30 wrap. marks last descriptor in transmit buffer descriptor list. 29 retry limit exceeded, transmit error detected 28 transmit underrun, occurs either when hresp is not ok (bus error) or the transmit data could not be fetched in time or when buffers are exhausted in mid frame. 27 buffers exhausted in mid frame 26:17 reserved 16 no crc. when set, no crc is appended to the current frame. this bit only needs to be set for the last buffer of a frame. 15 last buffer. when set, this bit indicates the last buffer in the current frame has been reached. 14:11 reserved 10:0 length of buffer table 38-2. transmit buffer descriptor entry bit function
668 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary whenever it sees an incoming frame to force a collision. this provides a way of implementing flow control in half-duplex mode. 38.3.4 pause frame support the start of an 802.3 pause frame is as follows: the network configuration register contains a receive pause enable bit (13). if a valid pause frame is received, the pause time register is updated with the frame?s pause time, regardless of its current contents and regardless of the state of the configuration register bit 13. an interrupt (12) is triggered when a pause frame is received, assuming it is enabled in the interrupt mask register. if bit 13 is set in the network configuration register and the value of the pause time reg- ister is non-zero, no new frame is transmitted until the pause time register has decremented to zero. the loading of a new pause time, and hence the pausing of transmission, only occurs when the emac is configured for full-duplex operation. if the emac is configured for half-duplex, there is no transmission pause, but the pause frame received interrupt is st ill triggered. a valid pause frame is defined as having a destin ation address that matches either the address stored in specific address register 1 or matches 0x0180c2000001 and has the mac control frame type id of 0x8808 and the pause opcode of 0x0001. pause frames that have fcs or other errors are treated as invalid and are discarded. valid pause frames received increment the pause frame received statistic register. the pause time register decrements every 512 bit times (i.e., 128 rx_clks in nibble mode) once transmission has stopped. for test purposes, the register decrements every rx_clk cycle once transmission has stopped if bit 12 (retry test) is set in the network configuration register. if the pause enable bit (13) is not set in the network configuration register, then the decrementing occurs regardless of whether transmission has stopped or not. an interrupt (13) is asserted whenever the pause time register decrements to zero (assuming it is enabled in the inte rrupt mask register). 38.3.5 receive block the receive block checks for valid preamble, fcs, alignment and length, presents received frames to the dma block and stores the frames destination address for use by the address checking block. if, during frame reception, the frame is found to be too long or rx_er is asserted, a bad frame indication is sent to the dma bl ock. the dma block then ceases sending data to memory. at the end of frame reception, the receive block indicates to the dma block whether the frame is good or bad. the dma block recovers the current receive buffer if the frame was bad. the receive block signals the register block to increment the alignment error, the crc (fcs) error, the short frame, long frame, jabber error, the receive symbol error statistics and the length field mismatch statistics. the enable bit for jumbo frames in the network configuration register allows the emac to receive jumbo frames of up to 10240 bytes in size. this operation does not form part of the ieee802.3 table 38-3. start of an 802.3 pause frame destination address source address type (mac control frame) pause opcode pause time 0x0180c2000001 6 bytes 0x8808 0x0001 2 bytes
669 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary specification and is disabled by default. when ju mbo frames are enabled, frames received with a frame size greater than 10240 bytes are discarded. 38.3.6 address checking block the address checking (or filter) block indicates to the dma block which receive frames should be copied to memory. whether a frame is copied depends on what is enabled in the network configuration register, the state of the external match pin, the contents of the specific address and hash registers and the frame?s destination add ress. in this implementation of the emac, the frame?s source address is not checked. provided that bit 18 of the network configuration regis- ter is not set, a frame is not copied to memory if the emac is transmitting in half duplex mode at the time a destination address is received. if bit 18 of the network configuration register is set, frames can be received while transmitting in half-duplex mode. ethernet frames are transmitted a byte at a time, least significant bit first. the first six bytes (48 bits) of an ethernet frame make up the destination address. the first bit of the destination address, the lsb of the first byte of the frame, is the group/individual bit: this is one for multicast addresses and zero for unicast. the all ones address is the broadcast address, and a special case of multicast. the emac supports recognition of four specific addresses. each specific address requires two registers, specific address register bottom and specific address register top. specific address register bottom stores the first four bytes of the destination address and specific address register top contains the last two bytes. the addresses st ored can be specific, group, local or universal. the destination address of received frames is compared against the data stored in the specific address registers once they have been activated. the addresses are deactivated at reset or when their corresponding specific a ddress register bottom is written. they are activated when specific address register top is written. if a receive frame address ma tches an active address, the frame is copied to memory. the following example illustrates the use of the address match registers for a mac address of 21:43:65:87:a9:cb. preamble 55 sfd d5 da (octet0 - lsb) 21 da(octet 1) 43 da(octet 2) 65 da(octet 3) 87 da(octet 4) a9 da (octet5 - msb) cb sa (lsb) 00 sa 00 sa 00 sa 00 sa 00
670 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary sa (msb) 43 sa (lsb) 21 the sequence above shows the beginning of an et hernet frame. byte order of transmission is from top to bottom as shown. for a successful match to specific address 1, the following address matching registers must be set up: ? base address + 0x98 0x87654321 (bottom) ? base address + 0x9c 0x0000cba9 (top) and for a successful match to the type id register, the following should be set up: ? base address + 0xb8 0x00004321 38.3.7 broadcast address the broadcast address of 0xffffffffffff is recogni zed if the ?no broadcast? bit in the net- work configuration register is zero. 38.3.8 hash addressing the hash address register is 64 bits long and ta kes up two locations in the memory map. the least significant bits are stored in hash register bottom and the most significant bits in hash reg- ister top. the unicast hash enable and the multicast hash enab le bits in the network configuration register enable the reception of hash matched frames. the destination address is reduced to a 6-bit index into the 64-bit hash register using the following hash function. the hash function is an exclusive or of every sixth bit of the destination address. hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] da[0] represents the least significant bit of the first byte received, that is , the multicast/unicast indicator, and da[47] represents the most significant bit of the last byte received. if the hash index points to a bit that is set in the hash register, then the frame is matched accord- ing to whether the frame is multicast or unicast. a multicast match is signalled if the multicast hash enable bit is set. da[0] is 1 and the hash index points to a bit set in the hash register. a unicast match is signalled if the unicast hash enable bit is set. da[0] is 0 and the hash index points to a bit set in the hash register. to receive all multicast frames, the hash register should be set with all ones and the multicast hash enable bit should be set in the network configuration register.
671 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.3.9 copy all frames (or promiscuous mode) if the copy all frames bit is set in the network configuration register, then all non-errored frames are copied to memory. for example, frames that are too long, too short, or have fcs errors or rx_er asserted during reception are discarded and all others are received. frames with fcs errors are copied to memory if bit 19 in the network configuration register is set. 38.3.10 type id checking the contents of the type_id register are compared against the length/type id of received frames (i.e., bytes 13 and 14). bit 22 in the receive buffer descriptor status is set if there is a match. the reset state of this register is zero which is unlikely to match the length/type id of any valid ether- net frame. note: a type id match does not affect whether a frame is copied to memory. 38.3.11 vlan support an ethernet encoded 802.1q vlan tag looks like this: the vlan tag is inserted at the 13 th byte of the frame, adding an extra four bytes to the frame. if the vid (vlan identifier) is null (0x000), this indicates a priority-tagged frame. the mac can support frame lengths up to 1536 bytes, 18 byte s more than the original ethernet maximum frame length of 1518 bytes. this is achieved by setting bit 8 in the network configuration register. the following bits in the receive buffer descrip tor status word give information about vlan tagged frames: ? bit 21 set if receive frame is vlan tagged (i.e. type id of 0x8100) ? bit 20 set if receive frame is priority tagged (i.e. type id of 0x8100 and null vid). (if bit 20 is set bit 21 is set also.) ? bit 19, 18 and 17 set to priority if bit 21 is set ? bit 16 set to cfi if bit 21 is set 38.3.12 wake-on-lan support the receive block supports wake-on-lan by det ecting the following events on incoming receive frames: ? magic packet ? arp request to the device ip address ? specific address 1 filter match ? multicast hash filter match if one of these events occurs wake-on-lan detection is indicated by asserting the wol output pin for 64 rx_clk cycles. these events can be individually enabled through bits[19:16] of the wake-on-lan register. also, for wake-on-lan detection to occur, receive enable must be set in the network control register, however a receive buffer does not have to be available. wol asser- tion due to arp request, specific address 1 or multicast filter events occurs even if the frame is errored. for magic packet events, the frame must be correctly formed and error free. table 38-4. 802.1q vlan tag tpid (tag protocol identifier) 16 bi ts tci (tag control information) 16 bits 0x8100 first 3 bits priority, then cfi bit, last 12 bits vid
672 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary a magic packet event is detected if all of the following are true: ? magic packet events are enabled through bit 16 of the wake-on-lan register ? the frame?s destination address matches specific address 1 ? the frame is correctly formed with no errors ? the frame contains at least 6 bytes of 0xff for synchronization ? there are 16 repetitions of the contents of specific address 1 register immediately following the synchronization an arp request event is detected if all of the following are true: ? arp request events are enabled through bit 17 of the wake-on-lan register ? broadcasts are allowed by bit 5 in the network configuration register ? the frame has a broadcast destination address (bytes 1 to 6) ? the frame has a type id field of 0x0806 (bytes 13 and 14) ? the frame has an arp operation field of 0x0001 (bytes 21 and 22) ? the least significant 16 bits of the frame? s arp target protocol address (bytes 41 and 42) match the value programmed in bits[15:0] of the wake-on-lan register the decoding of the arp fields adjusts automatically if a vlan tag is detected within the frame. the reserved value of 0x0000 for the wake-on-lan target address value does not cause an arp request event, even if matched by the frame. a specific address 1 filter match event occurs if all of the following are true: ? specific address 1 events are enabled through bit 18 of the wake-on-lan register ? the frame?s destination address matches the value programmed in the specific address 1 registers a multicast filter match event occurs if all of the following are true: ? multicast hash events are enabled through bit 19 of the wake-on-lan register ? multicast hash filtering is enabled through bit 6 of the network configuration register ? the frame?s destination address matches against the multicast hash filter ? the frame?s destination address is not a broadcast 38.3.13 phy maintenance the register emac_man enables the emac to communicate with a phy by means of the mdio interface. it is used during auto-negotiation to ensure that the emac and the phy are config- ured for the same speed and duplex configuration. the phy maintenance register is implemented as a shift register. writing to the register starts a shift operation which is signalled as complete when bit two is set in the network status register (about 2000 mck cycles later when bit ten is set to zero, and bit eleven is set to one in the net- work configuration register). an interrupt is generated as this bit is set. during this time, the msb of the register is output on the mdio pin and the lsb updated from the mdio pin with each mdc cycle. this causes transmission of a phy management frame on mdio. reading during the shift operation returns the current contents of the shift register. at the end of management operation, the bits have shifted back to their original locations. for a read opera- tion, the data bits are updated with data read from the phy. it is important to write the correct values to the register to ensure a valid phy management frame is produced.
673 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary the mdio interface can read ieee 802.3 clause 45 phys as well as clause 22 phys. to read clause 45 phys, bits[31:28] should be written as 0x0011. for a description of mdc generation, see the network configuration register in the ?network control register? on page 679 . 38.3.14 media independent interface the ethernet mac is capable of interfacing to both rmii and mii interfaces. the rmii bit in the emac_usrio register controls the interface that is selected. when this bit is set, the rmii inter- face is selected, else the mii interface is selected. the mii and rmii interface are capable of both 10mb/s and 100mb/s data rates as described in the ieee 802.3u standard. the signals used by the mii and rmii interfaces are described in table 38-5 . the intent of the rmii is to provide a reduced pin count alternative to the ieee 802.3u mii. it uses 2 bits for transmit (etx0 and etx1) and tw o bits for receive (erx0 and erx1). there is a transmit enable (etxen), a receive error (e rxer), a carrier sense (ecrs_dv), and a 50 mhz reference clock (etxck_erefck) for 100mb/s data rate. 38.3.14.1 rmii transmit and receive operation the same signals are used internally for both the rmii and the mii operations. the rmii maps these signals in a more pin-efficient manner. the transmit and receive bits are converted from a 4-bit parallel format to a 2-bit parallel scheme that is clocked at twice the rate. the carrier sense and data valid signals are combined into the ecrsdv signal. this signal contains information on carrier sense, fifo status, and validity of t he data. transmit error bit (etxer) and collision detect (ecol) are not used in rmii mode. table 38-5. pin configuration pin name mii rmii etxck_erefck etxck: transmit clock erefck: reference clock ecrs ecrs: carrier sense ecol ecol: collision detect erxdv erxdv: data valid ecrsdv: carrier sense/data valid erx0 - erx3 erx0 - erx3: 4-bit receiv e data erx0 - erx1: 2-bit receive data erxer erxer: receive erro r erxer: receive error erxck erxck: receive clock etxen etxen: transmit enable etxen: transmit enable etx0-etx3 etx0 - etx3: 4-bi t transmit data etx0 - etx1: 2-bit transmit data etxer etxer: transmit error
674 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.4 programming interface 38.4.1 initialization 38.4.1.1 configuration initialization of the emac configuration (e.g., loop-back mode, frequency ratios) must be done while the transmit and receive circ uits are disabled. see the description of the network control register and network configuration register earlier in this document. to change loop-back mode, the following sequence of operations must be followed: 1. write to network control register to disable transmit and receive circuits. 2. write to network control register to change loop-back mode. 3. write to network control register to re-enable transmit or receive circuits. note: these writes to network control register cannot be combined in any way. 38.4.1.2 receive buffer list receive data is written to areas of data (i.e., buffers) in system memory. these buffers are listed in another data structure that also resides in main memory. this data structure (receive buffer queue) is a sequence of descriptor entries as defined in ?receive buffer descriptor entry? on page 663 . it points to this data structure. figure 38-2. receive buffer list to create the list of buffers: 1. allocate a number ( n ) of buffers of 128 bytes in system memory. 2. allocate an area 2 n words for the receive buffer descriptor entry in system memory and create n entries in this list. mark all entries in th is list as owned by emac, i.e., bit 0 of word 0 set to 0. 3. if less than 1024 buffers are defined, the last descriptor must be marked with the wrap bit (bit 1 in word 0 set to 1). 4. write address of receive buffer descriptor entry to emac register receive_buffer queue pointer. 5. the receive circuits can then be enabled by writing to the address recognition registers and then to the network control register. receive buffer queue pointer (mac register) receive buffer 0 receive buffer 1 receive buffer n receive buffer descriptor list (in memory) (in memory)
675 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.4.1.3 transmit buffer list transmit data is read from areas of data (the buffers) in system memory these buffers are listed in another data structure that also resides in main memory. this data structure (transmit buffer queue) is a sequence of descriptor entries (as defined in table 38-2 on page 666 ) that points to this data structure. to create this list of buffers: 1. allocate a number ( n ) of buffers of between 1 and 2047 bytes of data to be transmitted in system memory. up to 128 buffers per frame are allowed. 2. allocate an area 2 n words for the transmit buffer descriptor entry in system memory and create n entries in this list. mark all entries in this list as owned by emac, i.e. bit 31 of word 1 set to 0. 3. if fewer than 1024 buffers are defined, the last descriptor must be marked with the wrap bit ? bit 30 in word 1 set to 1. 4. write address of transmit buffer descriptor entry to emac register transmit_buffer queue pointer. 5. the transmit circuits can then be enabled by writing to the network control register. 38.4.1.4 address matching the emac register-pair hash address and the four specific address register-pairs must be writ- ten with the required values. each register-pair comprises a bottom register and top register, with the bottom register being written first. the addre ss matching is disabled for a particular reg- ister-pair after the bottom-register has been written and re-enabled when the top register is written. see ?address checking block? on page 669. for details of address matching. each reg- ister-pair may be written at any time, regardless of whether the receive circuits are enabled or disabled. 38.4.1.5 interrupts there are 15 interrupt conditions that are detected within the emac. these are ored to make a single interrupt. depending on the overall system design, this may be passed through a further level of interrupt collection (int errupt controller). on receipt of the interrupt signal, the cpu enters the interrupt handler (refer to the aic programmer datasheet). to ascertain which inter- rupt has been generated, read the interrupt status register. note that this register clears itself when read. at reset, all interrupts are disabled. to enable an interrupt, write to interrupt enable register with the pertinent interrupt bit set to 1. to disable an interrupt, write to interrupt disable register with the pertinent interrupt bit set to 1. to check whether an interrupt is enabled or dis- abled, read interrupt mask register: if the bit is set to 1, the interrupt is disabled. 38.4.1.6 transmitting frames to set up a frame for transmission: 1. enable transmit in the network control register. 2. allocate an area of system memory for transmit data. this does not have to be contigu- ous, varying byte lengths can be used as long as they conclude on byte borders. 3. set-up the transmit buffer list. 4. set the network control register to enable transmission and enable interrupts. 5. write data for transmission into these buffers. 6. write the address to transmit buffer descriptor queue pointer. 7. write control and length to word one of the transmit buffer descriptor entry.
676 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 8. write to the transmit start bit in the network control register. 38.4.1.7 receiving frames when a frame is received and the receive circuits are enabled, the emac checks the address and, in the following cases, the frame is written to system memory: ? if it matches one of the four specific address registers. ? if it matches the hash address function. ? if it is a broadcast address (0xf fffffffffff) and broadcasts are allowed. ? if the emac is configured to copy all frames. the register receive buffer queue pointer points to the next entry (see table 38-1 on page 663 ) and the emac uses this as the address in system memory to write the frame to. once the frame has been completely and successfully received an d written to system memory, the emac then updates the receive buffer descriptor entry with the reason for the address match and marks the area as being owned by software. once this is complete an interrupt re ceive complete is set. software is then responsible for handling the data in the buffer and then releasing the buffer by writing the ownership bit back to 0. if the emac is unable to write the data at a rate to match the incoming frame, then an interrupt receive overrun is set. if there is no receive buffer available, i.e., the next buffer is still owned by software, the interrupt receive buffer not avail able is set. if the frame is not successfully received, a statistic register is incremented and the frame is discarded without informing software.
677 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5 ethernet mac 10/100 (e mac) user interface table 38-6. register mapping offset register name access reset 0x00 network control register emac_ncr read-write 0 0x04 network configuration register emac_ncfg read-write 0x800 0x08 network status register emac_nsr read-only - 0x0c reserved 0x10 reserved 0x14 transmit status regist er emac_tsr read-write 0x0000_0000 0x18 receive buffer queue pointer register emac_rbqp read-write 0x0000_0000 0x1c transmit buffer queue pointer register emac_tbqp read-write 0x0000_0000 0x20 receive status register emac_rsr read-write 0x0000_0000 0x24 interrupt status regist er emac_isr read-write 0x0000_0000 0x28 interrupt enable register emac_ier write-only - 0x2c interrupt disable register emac_idr write-only - 0x30 interrupt mask register emac_imr read-only 0x0000_7fff 0x34 phy maintenance register emac_man read-write 0x0000_0000 0x38 pause time register em ac_ptr read-write 0x0000_0000 0x3c pause frames received regi ster emac_pfr read-write 0x0000_0000 0x40 frames transmitted ok regi ster emac_fto read-write 0x0000_0000 0x44 single collision frames register emac_scf read-write 0x0000_0000 0x48 multiple collision frames register emac_mcf read-write 0x0000_0000 0x4c frames received ok register emac_fro read-write 0x0000_0000 0x50 frame check sequence errors r egister emac_fcse read-write 0x0000_0000 0x54 alignment errors regist er emac_ale read-write 0x0000_0000 0x58 deferred transmission frames register emac_dtf read-write 0x0000_0000 0x5c late collisions register emac_lcol read-write 0x0000_0000 0x60 excessive collisions register emac_ecol read-write 0x0000_0000 0x64 transmit underrun errors re gister emac_tund read-write 0x0000_0000 0x68 carrier sense errors register emac_cse read-write 0x0000_0000 0x6c receive resource errors r egister emac_rre read-write 0x0000_0000 0x70 receive overrun errors register emac_rov read-write 0x0000_0000 0x74 receive symbol errors register emac_rse read-write 0x0000_0000 0x78 excessive length errors register emac_ele read-write 0x0000_0000 0x7c receive jabbers register emac_rja read-write 0x0000_0000 0x80 undersize frames register emac_usf read-write 0x0000_0000 0x84 sqe test errors register emac_ste read-write 0x0000_0000 0x88 received length field mismatch register emac_rle read-write 0x0000_0000
678 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 0x90 hash register bottom [31:0] register emac_hrb read-write 0x0000_0000 0x94 hash register top [63:32] register emac_hrt read-write 0x0000_0000 0x98 specific address 1 bottom re gister emac_sa1b read-write 0x0000_0000 0x9c specific address 1 top regi ster emac_sa1t read-write 0x0000_0000 0xa0 specific address 2 bottom re gister emac_sa2b read-write 0x0000_0000 0xa4 specific address 2 top register emac_sa2t read-write 0x0000_0000 0xa8 specific address 3 bottom register emac_sa3b read-write 0x0000_0000 0xac specific address 3 top register emac_sa3t read-write 0x0000_0000 0xb0 specific address 4 bottom register emac_sa4b read-write 0x0000_0000 0xb4 specific address 4 top regi ster emac_sa4t read-write 0x0000_0000 0xb8 type id checking register emac_tid read-write 0x0000_0000 0xc0 user input/output register emac_usrio read-write 0x0000_0000 0xc4 wake on lan register emac_wol read-write 0x0000_0000 0xc8 - 0xfc reserved ? ? ? table 38-6. register mapping (continued) offset register name access reset
679 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.1 network control register register name: emac_ncr address: 0xfffc4000 access type: read-write ? lb: loopback asserts the loopback signal to the phy. ? llb: loopback local connects txd to rxd , tx_en to rx_dv , forces full duplex and drives rx_clk and tx_clk with pclk divided by 4. rx_clk and tx_clk may glitch as the emac is switched into and out of internal loop back. it is important that receive and transmit circuits have already been disabled when ma king the switch into and out of internal loop back. ? re: receive enable when set, enables the emac to receive data. when reset, frame reception stops immediately and the receive fifo is cleared. the receive queue pointer register is unaffected. ? te: transmit enable when set, enables the ethernet transmitter to send data. when reset transmission, stops immediately, the transmit fifo and control registers are cleared and the transmit queue pointer register resets to point to the start of the transmit descrip- tor list. ? mpe: management port enable set to one to enable the management port. when zero, forces mdio to high impedance state and mdc low. ? clrstat: clear statistics registers this bit is write only. writing a one clears the statistics registers. ? incstat: increment statistics registers this bit is write only. writing a one increments all the statistics registers by one for test purposes. ? westat: write enable for statistics registers setting this bit to one makes the statistics regi sters writable for functional test purposes. ? bp: back pressure if set in half duplex mode, forces collisions on all received frames. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????thalttstartbp 76543210 westat incstat clrstat mpe te re llb lb
680 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? tstart: start transmission writing one to this bit starts transmission. ? thalt: transmit halt writing one to this bit halts transmission as soon as any ongoing frame transmission ends.
681 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.2 network configuration register register name: emac_ncfg address: 0xfffc4004 access type: read-write ? spd: speed set to 1 to indicate 100 mbit/s operation, 0 for 10 mbit/s. the value of this pin is reflected on the speed pin. ? fd: full duplex if set to 1, the transmit block ignores the state of collision and carr ier sense and allows receiv e while transmitting. also co n- trols the half_duplex pin. ? caf: copy all frames when set to 1, all valid frames are received. ? jframe: jumbo frames set to one to enable jumbo frames of up to 10240 bytes to be accepted. ? nbc: no broadcast when set to 1, frames addressed to the broadcast address of all ones are not received. ? mti: multicast hash enable when set, multicast frames are received when the 6-bit hash functi on of the destination address points to a bit that is set in the hash register. ? uni: unicast hash enable when set, unicast frames are received when the 6-bit hash function of the destination address points to a bit that is set in the hash register. ? big: receive 1536 bytes frames setting this bit means the emac receives frames up to 1536 bytes in length. normally, the emac would reject any frame above 1518 bytes. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????irxfcsefrhddrfcsrlce 15 14 13 12 11 10 9 8 rbof pae rty clk ? big 76543210 uni mti nbc caf jframe ? fd spd
682 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? clk: mdc clock divider set according to system clock speed. this determines by what number system clock is divided to generate mdc. for con- formance with 802.3, mdc must not exceed 2.5mhz (mdc is only active during mdio read and write operations). ? rty: retry test must be set to zero for normal operation. if set to one, the back off between collisions is always one slot time. setting this bit to one helps testing the too many retries condition. also used in the pause frame tests to reduce the pause counters decrement time from 512 bit times, to every rx_clk cycle. ?pae: pause enable when set, transmission pauses when a valid pause frame is received. ? rbof: receive buffer offset indicates the number of bytes by which the received data is offset from the start of the first receive buffer. ? rlce: receive length field checking enable when set, frames with measured lengths shorter than their length fields are di scarded. frames containing a type id in bytes 13 and 14 ? length/type id = 0600 ? are not be counted as length errors. ? drfcs: discard receive fcs when set, the fcs field of received frames are not be copied to memory. ? efrhd: enable frames to be received in half-duplex mode wh ile transmitting. ? irxfcs: ignore rx fcs when set, frames with fcs/crc errors are not rejected and no fcs error statistics are counted. for normal operation, this bit must be set to 0. clk mdc 00 mck divided by 8 (mck up to 20 mhz) 01 mck divided by 16 (mck up to 40 mhz) 10 mck divided by 32 (mck up to 80 mhz) 11 mck divided by 64 (mck up to 160 mhz) rbof offset 00 no offset from start of receive buffer 01 one-byte offset from start of receive buffer 10 two-byte offset from start of receive buffer 11 three-byte offset from start of receive buffer
683 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.3 network status register register name: emac_nsr address: 0xfffc4008 access type: read-only ?mdio returns status of the mdio_in pin. use the phy main tenance register for reading managed frames rather than this bit. ?idle 0 = the phy logic is running. 1 = the phy management logic is idle (i.e., has completed). 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????idlemdio?
684 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.4 transmit status register register name: emac_tsr address: 0xfffc4014 access type: read-write this register, when read, provides details of the status of a tr ansmit. once read, individual bits may be cleared by writing 1 to them. it is not possible to set a bit to 1 by writing to the register. ? ubr: used bit read set when a transmit buffer descriptor is read with its used bit set. cleared by writing a one to this bit. ? col: collision occurred set by the assertion of collision. cle ared by writing a one to this bit. ? rle: retry limit exceeded cleared by writing a one to this bit. ? tgo: transmit go if high transmit is active. ? bex: buffers exhausted mid frame if the buffers run out during transmission of a frame, then transmission stops, fcs shall be bad and tx_er asserted. cleared by writing a one to this bit. ? comp: transmit complete set when a frame has been transmitted. cleared by writing a one to this bit. ? und: transmit underrun set when transmit dma was not able to read data from memory, either because the bus was not granted in time, because a not ok hresp(bus error) was returned or because a used bit was read midway through frame transmission. if this occurs, the transmitter forces bad crc. cleared by writing a one to this bit. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? und comp bex tgo rle col ubr
685 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.5 receive buffer queue pointer register register name: emac_rbqp address: 0xfffc4018 access type: read-write this register points to the entry in the receive buffer queue (des criptor list) currently being used. it is written with the st art location of the receive buffer descriptor list. the lower order bits increment as buffers are used up and wrap to their origina l values after either 1024 buffers or when the wrap bit of the entry is set. reading this register returns the location of the descriptor cu rrently being accessed. this value increments as buffers are used. software should not use this register for determining where to remove received frames from the queue as it con- stantly changes as new frames are received. software should instead work its way through the buffer descriptor queue checking the used bits. receive buffer writes also comprise bursts of two words and, as with transmit buffer reads, it is recommended that bit 2 is always written with zero to prevent a burst crossing a 1k bo undary, in violation of section 3.6 of the amba specification. ? addr: receive buffer queue pointer address written with the address of the start of the receive queue, reads as a pointer to the current buffer being used. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr ? ?
686 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.6 transmit buffer queue pointer register register name: emac_tbqp address: 0xfffc401c access type: read-write this register points to the entry in the transmit buffer queue (descriptor list) currently being used. it is written with the s tart location of the transmit buffer descriptor list. the lower order bits increment as buffers are used up and wrap to their origin al values after either 1024 buffers or when the wrap bit of the entry is set. this register can only be written when bit 3 in the transmit status register is low. as transmit buffer reads consist of bursts of two words, it is recommended that bit 2 is always written with zero to prevent a burst crossing a 1k boundary, in violation of section 3.6 of the amba specification. ? addr: transmit buffer queue pointer address written with the address of the start of the transmit queue, reads as a pointer to the first buffer of the frame being transmit - ted or about to be transmitted. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr ? ?
687 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.7 receive status register register name: emac_rsr address: 0xfffc4020 access type: read-write this register, when read, provides details of the status of a re ceive. once read, individual bits may be cleared by writing 1 to them. it is not possible to set a bit to 1 by writing to the register. ? bna: buffer not available an attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. the dma rereads the pointer each time a new frame starts un til a valid pointer is found. this bit is set at each attempt that fails even if it has not had a successful pointer read since it has been cleared. cleared by writing a one to this bit. ? rec: frame received one or more frames have been received and placed in memory. cleared by writing a one to this bit. ? ovr: receive overrun the dma block was unable to store the receive frame to me mory, either because the bus was not granted in time or because a not ok hresp(bus error) was returned. the buffer is recovered if this happens. cleared by writing a one to this bit. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????ovrrecbna
688 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.8 interrupt status register register name: emac_isr address: 0xfffc4024 access type: read-write ? mfd: management frame done the phy maintenance register has completed its operation. cleared on read. ? rcomp: rece ive complete a frame has been stored in memory. cleared on read. ? rxubr: receive used bit read set when a receive buffer descriptor is read with its used bit set. cleared on read. ? txubr: transmit used bit read set when a transmit buffer descriptor is read with its used bit set. cleared on read. ? tund: ethernet transmit buffer underrun the transmit dma did not fetch frame data in time for it to be transmitted or hresp returned not ok. also set if a used bit is read mid-frame or when a new transmit queue pointer is written. cleared on read. ? rle: retry limit exceeded cleared on read. ? txerr: transmit error transmit buffers exhausted in mid-frame - transmit error. cleared on read. ? tcomp: transmit complete set when a frame has been transmitted. cleared on read. ? rovr: receive overrun set when the receive overrun status bit gets set. cleared on read. ? hresp: hresp not ok set when the dma block sees a bus error . cleared on read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? wol ptz pfr hresp rovr ? ? 76543210 tcomp txerr rle tund txubr rxubr rcomp mfd
689 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? pfr: pause frame received indicates a valid pause has been received. cleared on a read. ? ptz: pause time zero set when the pause time register, 0x38 decrements to zero. cleared on a read. ? wol: wake on lan set when a wol event has been triggered (this flag can be set even if the emac is not clocked). cleared on a read.
690 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.9 interrupt enable register register name: emac_ier address: 0xfffc4028 access type: write-only ? mfd: management frame sent enable management done interrupt. ? rcomp: rece ive complete enable receive co mplete interrupt. ? rxubr: receive used bit read enable receive used bit read interrupt. ? txubr: transmit used bit read enable transmit used bit read interrupt. ? tund: ethernet transmit buffer underrun enable transmit underrun interrupt. ? rle: retry limit exceeded enable retry limit exceeded interrupt. ? txerr enable transmit buffers exhausted in mid-frame interrupt. ? tcomp: transmit complete enable transmit co mplete interrupt. ? rovr: receive overrun enable receive overrun interrupt. ? hresp: hresp not ok enable hresp not ok interrupt. ? pfr: pause frame received enable pause frame received interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? wol ptz pfr hresp rovr ? ? 76543210 tcomp txerr rle tund txubr rxubr rcomp mfd
691 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? ptz: pause time zero enable pause time zero interrupt. ? wol: wake on lan enable wake on lan interrupt.
692 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.10 interrupt disable register register name: emac_idr address: 0xfffc402c access type: write-only ? mfd: management frame sent disable management done interrupt. ? rcomp: rece ive complete disable receive comp lete interrupt. ? rxubr: receive used bit read disable receive used bit read interrupt. ? txubr: transmit used bit read disable transmit used bit read interrupt. ? tund: ethernet transmit buffer underrun disable transmit underrun interrupt. ? rle: retry limit exceeded disable retry limit exceeded interrupt. ? txerr disable transmit buffers exhausted in mid-frame interrupt. ? tcomp: transmit complete disable transmit complete interrupt. ? rovr: receive overrun disable receive overrun interrupt. ? hresp: hresp not ok disable hresp not ok interrupt. ? pfr: pause frame received disable pause frame received interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? wol ptz pfr hresp rovr ? ? 76543210 tcomp txerr rle tund txubr rxubr rcomp mfd
693 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? ptz: pause time zero disable pause time zero interrupt. ? wol: wake on lan disable wake on lan interrupt.
694 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.11 interrupt mask register register name: emac_imr address: 0xfffc4030 access type: read-only ? mfd: management frame sent management done interrupt masked. ? rcomp: rece ive complete receive complete interrupt masked. ? rxubr: receive used bit read receive used bit read interrupt masked. ? txubr: transmit used bit read transmit used bit read interrupt masked. ? tund: ethernet transmit buffer underrun transmit underrun interrupt masked. ? rle: retry limit exceeded retry limit exceeded interrupt masked. ? txerr transmit buffers exhausted in mid-frame interrupt masked. ? tcomp: transmit complete transmit complete interrupt masked. ? rovr: receive overrun receive overrun interrupt masked. ? hresp: hresp not ok hresp not ok interrupt masked. ? pfr: pause frame received pause frame received interrupt masked. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? wol ptz pfr hresp rovr ? ? 76543210 tcomp txerr rle tund txubr rxubr rcomp mfd
695 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? ptz: pause time zero pause time zero interrupt masked. ? wol: wake on lan wake on lan interrupt masked.
696 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.12 phy maintenance register register name: emac_man address: 0xfffc4034 access type: read-write ?data for a write operation this is written with the data to be written to the phy. after a read operation this contains the data read from the phy. ?code: must be written to 10. reads as written. ? rega: register address specifies the register in the phy to access. ? phya: phy address ? rw: read-write 10 is read; 01 is write. any other va lue is an invalid ph y management frame ? sof: start of frame must be written 01 for a valid frame. 31 30 29 28 27 26 25 24 sof rw phya 23 22 21 20 19 18 17 16 phya rega code 15 14 13 12 11 10 9 8 data 76543210 data
697 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.13 pause time register register name: emac_ptr address: 0xfffc4038 access type: read-write ? ptime: pause time stores the current value of the pause time register which is decremented every 512 bit times. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ptime 76543210 ptime
698 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.14 hash register bottom register name: emac_hrb address: 0xfffc4090 access type: read-write ? addr: bits 31:0 of the hash address register. see ?hash addressing? on page 670 . 38.5.15 hash register top register name: emac_hrt address: 0xfffc4094 access type: read-write ? addr: bits 63:32 of the hash address register. see ?hash addressing? on page 670 . 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr
699 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.16 specific address 1 bottom register register name: emac_sa1b address: 0xfffc4098 access type: read-write ? addr least significant bits of the destination address. bit zero indicates whether the address is multicast or unicast and corre- sponds to the least significant bit of the first byte received. 38.5.17 specific address 1 top register register name: emac_sa1t address: 0xfffc409c access type: read-write ? addr the most significant bits of the destination address, that is bits 47 to 32. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 addr 76543210 addr
700 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.18 specific address 2 bottom register register name: emac_sa2b address: 0xfffc40a0 access type: read-write ? addr least significant bits of the destination address. bit zero indicates whether the address is multicast or unicast and corre- sponds to the least significant bit of the first byte received. 38.5.19 specific address 2 top register register name: emac_sa2t address: 0xfffc40a4 access type: read-write ? addr the most significant bits of the destination address, that is bits 47 to 32. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 addr 76543210 addr
701 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.20 specific address 3 bottom register register name: emac_sa3b address: 0xfffc40a8 access type: read-write ? addr least significant bits of the destination address. bit zero indicates whether the address is multicast or unicast and corre- sponds to the least significant bit of the first byte received. 38.5.21 specific address 3 top register register name: emac_sa3t address: 0xfffc40ac access type: read-write ? addr the most significant bits of the destination address, that is bits 47 to 32. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 addr 76543210 addr
702 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.22 specific address 4 bottom register register name: emac_sa4b address: 0xfffc40b0 access type: read-write ? addr least significant bits of the destination address. bit zero indicates whether the address is multicast or unicast and corre- sponds to the least significant bit of the first byte received. 38.5.23 specific address 4 top register register name: emac_sa4t address: 0xfffc40b4 access type: read-write ? addr the most significant bits of the destination address, that is bits 47 to 32. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 addr 76543210 addr
703 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.24 type id checking register register name: emac_tid address: 0xfffc40b8 access type: read-write ? tid: type id checking for use in comparisons with rece ived frames typeid/length field. 38.5.25 user input/output register register name: emac_usrio address: 0xfffc40c0 access type: read-write ?rmii when set, this bit enables the rmii operation mode. when reset, it selects the mii mode. ?clken when set, this bit enables the transceiver input clock. setting this bit to 0 reduces power consumption when the treasurer is not used. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 tid 76543210 tid 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????clkenrmii
704 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.26 wake-on-lan register register name: emac_wol address: 0xfffc40c4 access type: read-write ? ip: arp request ip address written to define the least significant 16 bits of the target ip address that is matched to generate a wake-on-lan event. a value of zero does not generate an event, even if this is matched by the received frame. ? mag: magic packet event enable when set, magic packet events causes the wol output to be asserted. ? arp: arp request event enable when set, arp request events causes the wol output to be asserted. ? sa1: specific address register 1 event enable when set, specific address 1 events causes the wol output to be asserted. ? mti: multicast hash event enable when set, multicast ha sh events causes the wol output to be asserted. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????mtisa1arpmag 15 14 13 12 11 10 9 8 ip 76543210 ip
705 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.27 emac statistic registers these registers reset to zero on a read and stick at all ones when they count to their maximum value. they should be read frequently enough to prevent loss of data. the receive statis tics registers are only incremented when the receive enable bit is set in the network control register. to write to these registers, bit 7 must be set in the network control register. the sta tis- tics register block contains the following registers. 38.5.27.1 pause frames received register register name: emac_pfr address: 0xfffc403c access type: read-write ? frok: pause frames received ok a 16-bit register counting the number of good pause frames received. a good frame has a length of 64 to 1518 (1536 if bit 8 set in network configuration register) and has no fcs, alignment or receive symbol errors. 38.5.27.2 frames transmitted ok register register name: emac_fto address: 0xfffc4040 access type: read-write ? ftok: frames transmitted ok a 24-bit register counting the number of frames successfully transmitted, i.e., no underrun and not too many retries. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 frok 76543210 frok 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ftok 15 14 13 12 11 10 9 8 ftok 76543210 ftok
706 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.27.3 single collis ion frames register register name: emac_scf address: 0xfffc4044 access type: read-write ? scf: single collision frames a 16-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e., no underrun. 38.5.27.4 multicollision frames register register name: emac_mcf address: 0xfffc4048 access type: read-write ? mcf: multicollision frames a 16-bit register counting th e number of frames experiencing between two an d fifteen collisions prio r to being successfully transmitted, i.e., no underrun and not too many retries. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 scf 76543210 scf 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 mcf 76543210 mcf
707 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.27.5 frames received ok register register name: emac_fro address: 0xfffc404c access type: read-write ? frok: frames received ok a 24-bit register counting the number of good frames receiv ed, i.e., address recognized and successfully copied to mem- ory. a good frame is of length 64 to 1518 bytes (1536 if bit 8 set in network configuration register) and has no fcs, alignment or receive symbol errors. 38.5.27.6 frames check sequence errors register register name: emac_fcse address: 0xfffc4050 access type: read-write ? fcse: frame check sequence errors an 8-bit register counting frames that are an integral number of bytes, have bad crc and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register). this register is also incremented if a symbol error is detecte d and the frame is of valid length and has an integral number of bytes. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 frok 15 14 13 12 11 10 9 8 frok 76543210 frok 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 fcse
708 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.27.7 alignment errors register register name: emac_ale address: 0xfffc4054 access type: read-write ? ale: alignment errors an 8-bit register counting frames that are not an integral number of bytes long and have bad crc when their length is trun- cated to an integral number of bytes and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register). this register is also incremented if a symbol erro r is detected and the frame is of valid length and does not have an integral number of bytes. 38.5.27.8 deferred transmission frames register register name: emac_dtf address: 0xfffc4058 access type: read-write ? dtf: deferred transmission frames a 16-bit register counting the number of frames experiencing defer ral due to carrier sense being active on their first attempt at transmission. frames invo lved in any collision are not c ounted nor are fr ames that experienced a transmit underrun. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ale 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 dtf 76543210 dtf
709 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.27.9 late collisions register register name: emac_lcol address: 0xfffc405c access type: read-write ? lcol: late collisions an 8-bit register counting the number of frames that experience a collis ion after the slot time (512 bits) has expired. a late collision is counted twice; i.e., both as a collision and a late collision. 38.5.27.10 excessive collisions register register name: emac_ecol address: 0xfffc4060 access type: read-write ? excol: excessive collisions an 8-bit register counting the number of frames that faile d to be transmitted because t hey experienced 16 collisions. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 lcol 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 excol
710 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.27.11 transmit underrun errors register register name: emac_tund address: 0xfffc4064 access type: read-write ? tund: transmit underruns an 8-bit register counting the number of frames not transmitte d due to a transmit dma underrun. if this register is incre- mented, then no other statistics register is incremented. 38.5.27.12 carrier sense errors register register name: emac_cse address: 0xfffc4068 access type: read-write ? cse: carrier sense errors an 8-bit register counting the number of frames transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after bein g asserted in a transmit frame without collis ion (no underrun). on ly incremented in half-duplex mode. the only effect of a carrier sense error is to increment this register. the behavior of the other statistics registers is unaffected by the detection of a carrier sense error. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 tund 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 cse
711 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.27.13 receive reso urce errors register register name: emac_rre address: 0xfffc406c access type: read-write ? rre: receive resource errors a 16-bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available. 38.5.27.14 receive overrun errors register register name: emac_rov address: 0xfffc4070 access type: read-write ? rovr: receive overrun an 8-bit register counting the number of frames that are address recognized but were not copied to memory due to a receive dma overrun. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rre 76543210 rre 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rovr
712 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.27.15 receive symbol errors register register name: emac_rse address: 0xfffc4074 access type: read-write ? rse: receive symbol errors an 8-bit register counting the number of frames that had rx_er asserted during reception. receive symbol errors are also counted as an fcs or alignment error if the frame is between 64 and 1518 bytes in length (1536 if bit 8 is set in the network configuration register). if the frame is larger, it is recorded as a jabber error. 38.5.27.16 excessive length errors register register name: emac_ele address: 0xfffc4078 access type: read-write ? exl: excessive length errors an 8-bit register counting the number of frames received e xceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length but do not have either a crc error, an alignm ent error nor a rece ive symbol error. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rse 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 exl
713 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.27.17 receive jabbers register register name: emac_rja address: 0xfffc407c access type: read-write ? rjb: receive jabbers an 8-bit register counting the number of frames received e xceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length and have ei ther a crc error, an alignment er ror or a receiv e symbol error. 38.5.27.18 undersize frames register register name: emac_usf address: 0xfffc4080 access type: read-write ? usf: undersize frames an 8-bit register counting the number of frames received less than 64 bytes in length but do not have either a crc error, an alignment error or a receive symbol error. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rjb 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 usf
714 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 38.5.27.19 sqe test errors register register name: emac_ste address: 0xfffc4084 access type: read-write ? sqer: sqe test errors an 8-bit register counting the number of frames where col was not asserted within 96 bit times (an interframe gap) of tx_en being deasserted in half duplex mode. 38.5.27.20 received length field mismatch register register name: emac_rle address: 0xfffc4088 access type: read-write ? rlfm: receive length field mismatch an 8-bit register counting the number of frames received that have a measured length shorter than that extracted from its length field. checking is enabled through bit 16 of the netw ork configuration register. frames containing a type id in bytes 13 and 14 (i.e., length/type id 0x0600) are not counted as length field errors, neither are excessive length frames. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 sqer 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rlfm
715 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 39. usb device port (udp) 39.1 description the usb device port (udp) is compliant with the universal serial bus (usb) v2.0 full-speed device specification. each endpoint can be configured in one of several usb transfer types. it can be associated with one or two banks of a dual-port ram used to store the current data payload. if two banks are used, one dpr bank is read or written by the proc essor, while the other is read or written by the usb device peripheral. this feature is mandator y for isochronous endpoints. thus the device maintains the maximum bandwidth (1m bytes/s) by working with endpoints with two banks of dpr. note: 1. the dual-bank function provides two banks for an endpoint. this feature is used for ping-pong mode. suspend and resume are automatically detected by the usb device, which notifies the proces- sor by raising an interrupt. depending on the product, an external signal can be used to send a wake up to the usb host controller. table 39-1. usb endpoint description endpoint number mn emonic dual-bank (1) max. endpoint size endpoint type 0 ep0 no 64 control/bulk/interrupt 1 ep1 yes 64 bulk/iso/interrupt 2 ep2 yes 64 bulk/iso/interrupt 3 ep3 no 64 control/bulk/interrupt 4 ep4 yes 512 bulk/iso/interrupt 5 ep5 yes 512 bulk/iso/interrupt
716 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 39.2 block diagram figure 39-1. block diagram access to the udp is via the apb bus interface. read and write to the data fi fo are done by reading and writing 8-bit values to apb registers. the udp peripheral requires two clocks: one peripheral clock used by the master clock domain (mck) and a 48 mhz clock (udpck) used by the 12 mhz domain. a usb 2.0 full-speed pad is embedded and controlled by the serial interface engine (sie). the signal external_resume is optional. it allows the udp peripheral to wake up once in system mode. the host is then notified that the device asks for a resume. this optional feature must be also negotiated with the host during the enumeration. 39.3 product dependencies for further details on the usb device hardware implementation, see the specific product prop- erties document. the usb physical transceiver is integrated into the product. the bidirectional differential signals dp and dm are available from the product boundary. one i/o line may be used by the application to check that vbus is still available from the host. self-powered devices may use this entry to be notified that the host has been powered off. in this case, the pullup on dp must be disabled in order to prevent feeding current to the host. the application should disconnect the transceiver, then remove the pullup. 39.3.1 i/o lines dp and dm are not controlled by any pio controllers. the embedded usb physical transceiver is controlled by the usb device peripheral. atmel bridge 12 mhz suspend/resume logic w r a p p e r w r a p p e r u s e r i n t e r f a c e serial interface engine sie mck master clock domain dual port ram fifo udpck recovered 12 mhz domain udp_int usb device embedded usb transceiver dp dm external_resume apb to mcu bus txoen eopn txd rxdm rxd rxdp
717 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary to reserve an i/o line to check vbus, the program mer must first program the pio controller to assign this i/o in input pio mode. 39.3.2 power management the usb device peripheral requires a 48 mhz cl ock. this clock must be generated by a pll with an accuracy of 0.25%. thus, the usb device receives two clocks from the power management controller (pmc): the master clock, mck, used to drive the peripheral user interface, and the udpck, used to inter- face with the bus usb signals (recovered 12 mhz domain). warning: the udp peripheral clock in the power management controller (pmc) must be enabled before any read/write operations to the udp registers including the udp_txcv register. 39.3.3 interrupt the usb device interface has an interrupt line co nnected to the advanced interrupt controller (aic). handling the usb device interrupt requires programming the aic before configuring the udp.
718 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 39.4 typical connection figure 39-2. board schematic to interface device peripheral 39.4.1 usb device transceiver the usb device transceiver is embedded in the product. a few discrete components are required as follows: ? the application detects all device states as def ined in chapter 9 of the usb specification; ?vbus monitoring ? to reduce power consumption the host is disconnected ? for line termination. 39.4.2 vbus monitoring vbus monitoring is required to detect host connection. vbus monitoring is done using a stan- dard pio with internal pullup disabled. when the host is switched off, it should be considered as a disconnect, the pullup must be disabled in order to prevent powering the host through the pull- up resistor. when the host is disconnected and the transceiver is enabled, then ddp and ddm are floating. this may lead to over consumption. a solution is to enable the integrated pulldown by disabling the transceiver (txvdis = 1) and then remove the pullup (puon = 0). a termination serial resistor must be connected to dp and dm. the resistor value is defined in the electrical specification of the product (r ext ). r ext r ext ddm ddp pio 27 k 47 k type b connector 1 2 34 5v bus monitoring
719 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 39.5 functional description 39.5.1 usb v2.0 full-speed introduction the usb v2.0 full-speed provides communication services between host and attached usb devices. each device is offered with a collection of communication flows (pipes) associated with each endpoint. software on the host communicates with a usb device through a set of commu- nication flows. figure 39-3. example of usb v2.0 full-speed communication control the control transfer endpoint ep0 is always used when a us b device is first configured (usb v. 2.0 specifications). 39.5.1.1 usb v2.0 full-speed transfer types a communication flow is carried over one of f our transfer types defined by the usb device. ep0 usb host v2.0 software client 1 software client 2 data flow: bulk out transfer data flow: bulk in transfer data flow: control transfer data flow: control transfer ep1 ep2 usb device 2.0 block 1 usb device 2.0 block 2 ep5 ep4 ep0 data flow: isochronous in transfer data flow: isochronous out transfer usb device endpoint configuration requires that in the first instance control transfer must be ep0. table 39-2. usb communication flow transfer direction bandwidth supported endpoint size error detection retrying control bidirectional not guaranteed 8, 16, 32, 64 yes automatic isochronous unidirectional guaranteed 512 yes no interrupt unidirectional not guaranteed 64 yes yes bulk unidirectional not guaranteed 8, 16, 32, 64 yes yes
720 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 39.5.1.2 usb bus transactions each transfer results in one or more transactions over the usb bus. there are three kinds of transactions flowing acro ss the bus in packets: 1. setup transaction 2. data in transaction 3. data out transaction 39.5.1.3 usb transfer event definitions as indicated below, transfers are sequential events carried out on the usb bus. notes: 1. control transfer must use endpoints with no ping-pong attributes. 2. isochronous transfers must use endpoints with ping-pong attributes. 3. control transfers can be aborted using a stall handshake. a status transaction is a special type of host-to- device transaction used only in a control transfer. the control transfer must be performed using endpoints with no ping-pong attributes. according to the control sequence (read or write), the usb device sends or receives a status transaction. table 39-3. usb transfer events control transfers (1) (3) ? setup transaction > data in transactions > status out transaction ? setup transaction > data out transactions > status in transaction ? setup transaction > status in transaction interrupt in transfer (device toward host) ? data in transaction > data in transaction interrupt out transfer (host toward device) ? data out transaction > data out transaction isochronous in transfer (2) (device toward host) ? data in transaction > data in transaction isochronous out transfer (2) (host toward device) ? data out transaction > data out transaction bulk in transfer (device toward host) ? data in transaction > data in transaction bulk out transfer (host toward device) ? data out transaction > data out transaction
721 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 39-4. control read and write sequences notes: 1. during the status in stage, the host waits for a zero length packet (data in transaction with no data) from the device using data1 pid. refer to chapter 8 of the universal serial bus specifi- cation, rev. 2.0, for more information on the protocol layer. 2. during the status out stage, the host emits a zero length packet to the device (data out transaction with no data). 39.5.2 handling transactions with usb v2.0 device peripheral 39.5.2.1 setup transaction setup is a special type of host-to-device transaction used during control transfers. control trans- fers must be performed using endpoints with no ping-pong attributes. a setup transaction needs to be handled as soon as possible by the firmware. it is used to transmit requests from the host to the device. these requests are then handled by the usb device and may require more argu- ments. the arguments are sent to the device by a data out transaction which follows the setup transaction. these requests may also return data. the data is carried out to the host by the next data in transaction which follows the setup transaction. a status transaction ends the control transfer. when a setup transfer is received by the usb endpoint: ? the usb device automatically acknowledges the setup packet ? rxsetup is set in the udp_csrx register ? an endpoint interrupt is generated while the rxsetup is not cleared. this interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint. thus, firmware must det ect the rxsetup polling the udp_csrx or catching an interrupt, read the setup packet in the fifo , then clear the rxsetup. rxsetup cannot be clear ed before the setup packet has been read in the fifo. otherwise, the usb device would accept the next data out transfer and overwrite the setup packet in the fifo. control read setup tx data out tx data out tx data stage control write setup stage setup stage setup tx setup tx no data control data in tx data in tx status stage status stage status in tx status out tx status in tx data stage setup stage status stage
722 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 39-5. setup transaction followed by a data out transaction 39.5.2.2 data in transaction data in transactions are used in control, is ochronous, bulk and interrupt transfers and conduct the transfer of data from the device to the host. data in transactions in isochronous transfer must be done using endpoints with ping-pong attributes. 39.5.2.3 using endpoints without ping-pong attributes to perform a data in transaction using a non ping-pong endpoint: 1. the application checks if it is possible to write in the fifo by polling txpktrdy in the endpoint?s udp_csrx regist er (txpktrdy must be cleared). 2. the application writes the first packet of data to be sent in the endpoint?s fifo, writing zero or more byte values in the endpoint?s udp_fdrx register, 3. the application notifies the usb peripheral it has finished by setting the txpktrdy in the endpoint?s udp_csrx register. 4. the application is notified that the endpoint?s fifo has been released by the usb device when txcomp in the endpoint?s udp_csrx register has been set. then an interrupt for the corresponding endpoint is pending while txcomp is set. 5. the microcontroller writes the second packet of data to be sent in the endpoint?s fifo, writing zero or more byte values in the endpoint?s udp_fdrx register, 6. the microcontroller notifi es the usb peripheral it has finished by setting the txpk- trdy in the endpoint?s udp_csrx register. 7. the application clears the txcomp in the endpoint?s udp_csrx. after the last packet has been sent, the application must clear txcomp once this has been set. txcomp is set by the usb device when it has received an ack pid signal for the data in packet. an interrupt is pending while txcomp is set. warning: tx_comp must be cleared after tx_pktrdy has been set. note: refer to chapter 8 of the universal serial bus specification, rev 2.0, for more information on the data in protocol layer. rx_data_bko (udp_csrx) ack pid data out data out pid nak pid ack pid data setup setup pid usb bus packets rxsetup flag set by usb device cleared by firmware set by usb device peripheral fifo (dpr) content data setup data xx xx out interrupt pending setup received setup handled by firmware data out received data out data out pid
723 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 39-6. data in transfer for non ping-pong endpoint 39.5.2.4 using endpoints with ping-pong attribute the use of an endpoint with ping-pong attributes is necessary during isochronous transfer. this also allows handling the maximum bandwidth defined in the usb specification during bulk trans- fer. to be able to guarantee a constant or the maximum bandwidth, the microcontroller must prepare the next data payload to be sent while the current one is being sent by the usb device. thus two banks of memory are used. while one is available for the microcontroller, the other one is locked by the usb device. figure 39-7. bank swapping data in transfer for ping-pong endpoints usb bus packets data in 2 data in nak ack data in 1 fifo (dpr) content data in 2 load in progress data in 1 cleared by firmware dpr access by the firmware payload in fifo txcomp flag (udp_csrx) txpktrdy flag (udp_csrx) pid data in data in pid pid pid pid ack pid prevous data in tx microcontroller load data in fifo data is sent on usb bus interrupt pending interrupt pending set by the firmware set by the firmware cleared by firmware cleared by hw cleared by hw dpr access by the hardware usb device usb bus read write read and write at the same time 1 st data payload 2 nd data payload 3 rd data payload 3 rd data payload 2 nd data payload 1 st data payload data in packet data in packet data in packet microcontroller endpoint 1 bank 0 endpoint 1 bank 1 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 1
724 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary when using a ping-pong endpoint, the following procedures are required to perform data in transactions: 1. the microcontroller checks if it is possible to write in the fifo by polling txpktrdy to be cleared in the endpoint?s udp_csrx register. 2. the microcontroller writes the first data payload to be sent in the fifo (bank 0), writing zero or more byte values in the endpoint?s udp_fdrx register. 3. the microcontroller notifies the usb peripheral it has finished writing in bank 0 of the fifo by setting the txpktrdy in the endpoint?s udp_csrx register. 4. without waiting for txpktrdy to be cleare d, the microcontrolle r writes the second data payload to be sent in the fifo (bank 1), writing zero or more byte values in the endpoint?s udp_fdrx register. 5. the microcontroller is notified that the first bank has been released by the usb device when txcomp in the endpoint?s udp_csrx register is set. an interrupt is pending while txcomp is being set. 6. once the microcontroller has received txco mp for the first bank, it notifies the usb device that it has prepared the second bank to be sent, raising txpktrdy in the end- point?s udp_csrx register. 7. at this step, bank 0 is available and the microcontroller can prepare a third data pay- load to be sent . figure 39-8. data in transfer for ping-pong endpoint warning: there is software critical path due to the fact that once the second bank is filled, the driver has to wait for tx_comp to set tx_pktrdy. if the delay between receiving tx_comp is set and tx_pktrdy is set too long, some data in packets may be nacked, reducing the bandwidth. warning: tx_comp must be cleared after tx_pktrdy has been set. data in data in read by usb device read by usb device bank 1 bank 0 fifo (dpr) txcomp flag (udp_csrx) interrupt cleared by firmware set by usb device txpktrdy flag (udp_mcsrx) ack pid data in pid ack pid set by firmware, data payload written in fifo bank 1 cleared by usb device, data payload fully transmitted data in pid usb bus packets set by usb device set by firmware, data payload written in fifo bank 0 written by fifo (dpr) microcontroller written by microcontroller written by microcontroller microcontroller load data in bank 0 microcontroller load data in bank 1 usb device send bank 0 microcontroller load data in bank 0 usb device send bank 1 interrupt pending
725 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 39.5.2.5 data out transaction data out transactions are used in control, isochronous, bulk and interru pt transfers and con- duct the transfer of data from the host to the device. data out transactions in isochronous transfers must be done using endpoints with ping-pong attributes. 39.5.2.6 data out transaction without ping-pong attributes to perform a data out transaction, using a non ping-pong endpoint: 1. the host generates a data out packet. 2. this packet is received by the usb device endpoint. while the fifo associated to this endpoint is being used by the microcontroller, a nak pid is returned to the host. once the fifo is available, data are written to the fifo by the usb device and an ack is automatically carried out to the host. 3. the microcontroller is notifie d that the usb device has re ceived a data payload polling rx_data_bk0 in the endpoint?s udp_csrx register. an interrupt is pending for this endpoint while rx_data_bk0 is set. 4. the number of bytes available in the fi fo is made available by reading rxbytecnt in the endpoint?s udp_csrx register. 5. the microcontroller carries out data received from the endpoint?s memory to its mem- ory. data received is available by reading the endpoint?s udp_fdrx register. 6. the microcontroller notifies the usb device that it has finished the transfer by clearing rx_data_bk0 in the endpoint?s udp_csrx register. 7. a new data out packet can be accepted by the usb device. figure 39-9. data out transfer for non ping-pong endpoints an interrupt is pending while the flag rx_dat a_bk0 is set. memory transfer between the usb device, the fifo and microcontroller memory can not be done after rx_data_bk0 has been cleared. otherwise, the usb device would acce pt the next data out transfer and overwrite the current data out packet in the fifo. ack pid data out nak pid pid pid pid pid data out2 ack data out data out 1 usb bus packets rx_data_bk0 set by usb device cleared by firmware, data payload written in fifo fifo (dpr) content written by usb device microcontroller read data out 1 data out 1 data out 2 host resends the next data payload microcontroller transfers data host sends data payload data out2 data out2 host sends the next data payload written by usb device (udp_csrx) interrupt pending
726 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 39.5.2.7 using endpoints with ping-pong attributes during isochronous transfer, using an endpoint wit h ping-pong attributes is obligatory. to be able to guarantee a constant bandwidth, the micr ocontroller must read the previous data pay- load sent by the host, while the current data payload is received by the usb device. thus two banks of memory are used. while one is available for the microcontroller, the other one is locked by the usb device. figure 39-10. bank swapping in data out transfers for ping-pong endpoints when using a ping-pong endpoint, the following procedures are required to perform data out transactions: 1. the host generates a data out packet. 2. this packet is received by the usb device endpoint. it is written in the endpoint?s fifo bank 0. 3. the usb device sends an ack pid packet to the host. the host can immediately send a second data out packet. it is accepted by the device and copied to fifo bank 1. 4. the microcontroller is notifi ed that the usb device has re ceived a data payload, polling rx_data_bk0 in the endpoint?s udp_csrx register. an interrupt is pending for this endpoint while rx_data_bk0 is set. 5. the number of bytes available in the fi fo is made available by reading rxbytecnt in the endpoint?s udp_csrx register. 6. the microcontroller transfers out data received from the endpoint?s memory to the microcontroller?s memory. data received is made available by reading the endpoint?s udp_fdrx register. 7. the microcontroller notifies the usb peripheral device that it has finished the transfer by clearing rx_data_bk0 in the endpoint?s udp_csrx register. 8. a third data out packet can be accepted by the usb peripheral device and copied in the fifo bank 0. 9. if a second data out packet has been received, the microcontroller is notified by the flag rx_data_bk1 set in the endpoint?s udp_csrx register. an interrupt is pending for this endpoint while rx_data_bk1 is set. usb device usb bus read write write and read at the same time 1 st data payload 2 nd data payload 3 rd data payload 3 rd data payload 2 nd data payload 1 st data payload data in packet data in packet data in packet microcontroller endpoint 1 bank 0 endpoint 1 bank 1 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 1
727 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 10. the microcontroller transfers out data received from the endpoint?s memory to the microcontroller?s memory. data received is available by reading the endpoint?s udp_fdrx register. 11. the microcontroller notifies the usb device it has finished the transfer by clearing rx_data_bk1 in the endpoint?s udp_csrx register. 12. a fourth data out packet can be accepted by the usb device and copied in the fifo bank 0. figure 39-11. data out transfer for ping-pong endpoint note: an interrupt is pending while the rx_data_bk0 or rx_data_bk1 flag is set. warning : when rx_data_bk0 and rx_data_bk1 are both set, there is no way to determine which one to clear first. thus the software must keep an internal counter to be sure to clear alter- natively rx_data_bk0 then rx_data_bk1. th is situation may occur when the software application is busy elsewhere and the two banks are filled by the usb host. once the application comes back to the usb driver, the two flags are set. 39.5.2.8 stall handshake a stall handshake can be used in one of two distinct occasions. (for more information on the stall handshake, refer to chapter 8 of the universal serial bus specification, rev 2.0. ) ? a functional stall is used when the halt feature associated with the endpoint is set. (refer to chapter 9 of the universal serial bus sp ecification, rev 2.0, for more information on the halt feature.) ? to abort the current request, a protocol stall is used, but uniquely with control transfer. the following procedure generates a stall packet: a p data out pid ack data out 3 data out data out 2 data out data out 1 pid data out 3 data out 1 data out1 data out 2 data out 2 pid pid pid ack cleared by firmware usb bus packets rx_data_bk0 flag rx_data_bk1 flag set by usb device, data payload written in fifo endpoint bank 1 fifo (dpr) bank 0 bank 1 write by usb device write in progress read by microcontroller read by microcontroller set by usb device, data payload written in fifo endpoint bank 0 host sends first data payload microcontroller reads data 1 in bank 0, host sends second data payload microcontroller reads data2 in bank 1, host sends third data payload cleared by firmware write by usb device fifo (dpr) (udp_csrx) (udp_csrx) interrupt pending interrupt pending
728 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 1. the microcontroller sets the forcestall flag in the udp_csrx endpoint?s register. 2. the host receives the stall packet. 3. the microcontroller is notif ied that the device has sent the stall by polling the stallsent to be set. an endpoint interrup t is pending while stallsent is set. the microcontroller must clear stallsent to clear the interrupt. when a setup transaction is received after a stall handshake, stallsent must be cleared in order to prevent interrupts due to stallsent being set. figure 39-12. stall handshake (data in transfer) figure 39-13. stall handshake (data out transfer) data in stall pid pid usb bus packets cleared by firmware set by firmware forcestall stallsent set by usb device cleared by firmware interrupt pending data out pid stall pid data out usb bus packets cleared by firmware set by firmware forcestall stallsent set by usb device interrupt pending
729 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 39.5.2.9 transmit data cancellation some endpoints have dual-banks whereas some endpoints have only one bank. the procedure to cancel transmission data held in these banks is described below. to see the organization of dual-bank availablity refer to table 39-1 ?usb endpoint description? . 39.5.2.10 endpoints without dual-banks there are two poss ibilities: in one case, txpktrdy fiel d in udp_csr has already been set. in the other instance, txpktrdy is not set. ? txpktrdy is not set: ? reset the endpoint to clear the fifo (pointers). (see, section 39.6.9 ?udp reset endpoint register? .) ? txpktrdy has already been set: ? clear txpktrdy so that no packet is ready to be sent ? reset the endpoint to clear the fifo (pointers). (see, section 39.6.9 ?udp reset endpoint register? .) 39.5.2.11 endpoints with dual-banks there are two poss ibilities: in one case, txpktrdy fiel d in udp_csr has already been set. in the other instance, txpktrdy is not set. ? txpktrdy is not set: ? reset the endpoint to clear the fifo (pointers). (see, section 39.6.9 ?udp reset endpoint register? .) ? txpktrdy has already been set: ? clear txpktrdy and read it ba ck until actually read at 0. ? set txpktrdy and read it ba ck until actually read at 1. ? clear txpktrdy so that no packet is ready to be sent. ? reset the endpoint to clear the fifo (pointers). (see, section 39.6.9 ?udp reset endpoint register? .)
730 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 39.5.3 controlling device states a usb device has several possible states. refer to chapter 9 of the universal serial bus speci- fication, rev 2.0 . figure 39-14. usb device state diagram movement from one state to another depends on the usb bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). after a period of bus inactivity, the us b device enters suspend mode. accepting sus- pend/resume requests from the usb host is mandatory. constraints in suspend mode are very strict for bus-powered applications; devices may not consume more than 500 a on the usb bus. while in suspend mode, the host may wake up a de vice by sending a resume signal (bus activ- ity) or a usb device may send a wake up request to the host, e.g., waking up a pc by moving a usb mouse. the wake up feature is not mandatory for all devices and must be negotiated with the host. attached suspended suspended suspended suspended hub reset or deconfigured hub configured bus inactive bus activity bus inactive bus activity bus inactive bus activity bus inactive bus activity reset reset address assigned device deconfigured device configured powered default address configured power interruption
731 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 39.5.3.1 not powered state self powered devices can detect 5v vbus using a pio as described in the typical connection section. when the device is not connected to a host, device power consumption can be reduced by disabling mck for the ud p, disabling udpck and disabl ing the transceiver. ddp and ddm lines are pulled down by 330 k resistors. 39.5.3.2 entering attached state when no device is connected, the usb dp and dm signals are tied to gnd by 15 k pull-down resistors integrated in the hub downstream ports. when a device is attached to a hub down- stream port, the device connects a 1.5 k pull-up resistor on dp. the usb bus line goes into idle state, dp is pulled up by the device 1.5 k resistor to 3.3v and dm is pulled down by the 15 k resistor of the host. to enable integrated pullup, the puon bit in the udp_txvc register must be set. warning : to write to the udp_txvc register, mck clock must be enabled on the udp. this is done in the power management controller. after pullup connection, the device enters the powered state. in this state, the udpck and mck must be enabled in the power management controller. the transceiver can remain disabled. 39.5.3.3 from powered state to default state after its connection to a usb host, the usb device waits for an end-of-bus reset. the unmaskable flag endbusres is set in the register udp_isr and an interrupt is triggered. once the endbusres interrupt has been triggered, the device enters default state. in this state, the udp software must: ? enable the default endpoint, setting the epeds flag in the udp_csr[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 to the udp_ier register. the enumeration then begins by a control transfer. ? configure the interrupt mask register which has been reset by the usb reset detection ? enable the transceiver clearing the txvdis flag in the udp_txvc register. in this state udpck and mck must be enabled. warning : each time an endbusres interrupt is triggered, the interrupt mask register and udp_csr registers have been reset. 39.5.3.4 from default state to address state after a set address standard device request, the usb host peripheral enters the address state. warning : before the device enters in address state, it must achieve the status in transaction of the control transfer, i.e., the udp device sets its new address once the txcomp flag in the udp_csr[0] register has been received and cleared. to move to address state, the driver software sets the fadden flag in the udp_glb_stat register, sets its new address, and sets the fen bit in the udp_faddr register. 39.5.3.5 from address state to configured state once a valid set configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. this is done by setting the epeds and eptype fields in the udp_csrx regist ers and, optionally, en abling corr esponding interrupts in the udp_ier register.
732 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 39.5.3.6 entering in suspend state when a suspend (no bus activity on the usb bus) is detected, the rxsusp signal in the udp_isr register is set. this triggers an interrupt if the co rresponding bit is set in the udp_imr register.this flag is cleared by writing to the udp_icr register. then the device enters suspend mode. in this state bus powered devices must drain less than 500ua from the 5v vbus. as an exam- ple, the microcontroller switches to slow clock, disables the pl l and main osc illator, and goes into idle mode. it may also switch off other devices on the board. the usb device peripheral clocks can be s witched off. resume event is asynchronously detected. mck and udpck can be switched off in the power management controller and the usb transceiver can be disabled by setting the txvdis field in the udp_txvc register. warning : read, write operations to the udp registers are allowed only if mck is enabled for the udp peripheral. switching off mck for the udp peripheral must be one of the last operations after writing to the udp_txvc and acknowledging the rxsusp. 39.5.3.7 receiving a host resume in suspend mode, a resume event on the usb bus line is detected asynchronously, transceiver and clocks are disabled (however the pullup shall not be removed). once the resume is detected on the bus, the wakeup signal in the udp_isr is set. it may gen- erate an interrupt if the corresponding bit in the udp_imr register is set. this interrupt may be used to wake up the core, enable pll a nd main oscillators and configure clocks. warning : read, write operations to the udp registers are allowed only if mck is enabled for the udp peripheral. mck for the udp must be enabled before clea ring the wakeup bit in the udp_icr register and clearing txvdis in the udp_txvc register. 39.5.3.8 sending a device remote wakeup in suspend state it is possible to wake up the host sending an external resume. ? the device must wait at least 5 ms after being entered in suspend before sending an external resume. ? the device has 10 ms from the moment it starts to drain current and it forces a k state to resume the host. ? the device must force a k state from 1 to 15 ms to resume the host to force a k state to the bus (dm at 3.3v and dp tied to gnd), it is possible to use a transistor to connect a pullup on dm. the k state is obt ained by disabling the pullup on dp and enabling the pullup on dm. this should be under the control of the application.
733 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 39-15. board schematic to drive a k state 3v3 pio 1.5 k 0: force wake up (k state) 1: normal mode dm
734 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 39.6 usb device port (udp) user interface warning: the udp peripheral clock in the power management controller (pmc) must be enabled before any read/write operations to the udp registers, including the udp_txvc register. notes: 1. reset values are not defined for udp_isr. 2. see warning above the ?register mapping? on this page. table 39-4. register mapping offset register name access reset 0x000 frame number register udp_frm_num read-only 0x0000_0000 0x004 global state register udp_glb_stat read-write 0x0000_0000 0x008 function address register udp_faddr read-write 0x0000_0100 0x00c reserved ? ? ? 0x010 interrupt enable register udp_ier write-only 0x014 interrupt disable register udp_idr write-only 0x018 interrupt mask register udp_imr read-only 0x0000_1200 0x01c interrupt status register udp_isr read-only ? (1) 0x020 interrupt clear register udp_icr write-only 0x024 reserved ? ? ? 0x028 reset endpoint register udp_rst_ep read-write 0x0000_0000 0x02c reserved ? ? ? 0x030 + 0x4 * ( ept_num - 1 ) endpoint control and status register udp_csr read-write 0x0000_0000 0x050 + 0x4 * ( ept_num - 1 ) endpoint fifo data register udp_fdr read-write 0x0000_0000 0x070 reserved ? ? ? 0x074 transceiver control register udp_txvc (2) read-write 0x0000_0100 0x078 - 0xfc reserved ? ? ?
735 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 39.6.1 udp frame number register register name: udp_frm_num address: 0xfffa4000 access type: read-only ? frm_num[10:0]: frame number as defined in the packet field formats this 11-bit value is incremented by the host on a per fr ame basis. this value is updated at each start of frame. value updated at the sof_eop (start of frame end of packet). ? frm_err: frame error this bit is set at sof_eop when the sof packet is received containing an error. this bit is reset upon receipt of sof_pid. ? frm_ok: frame ok this bit is set at sof_eop when the sof packet is received without any error. this bit is reset upon receipt of sof_pid (packet identification). in the interrupt status register, the sof interrupt is updated upon receiving sof_pid. this bit is set without waiting for eop. note: in the 8-bit register interfac e, frm_ok is bit 4 of frm_num_h and frm_err is bit 3 of frm_num_l. 31 30 29 28 27 26 25 24 --- --- --- --- --- --- --- --- 23 22 21 20 19 18 17 16 ??????frm_okfrm_err 15 14 13 12 11 10 9 8 ????? frm_num 76543210 frm_num
736 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 39.6.2 udp global state register register name: udp_glb_stat address: 0xfffa4004 access type: read-write this register is used to get and set the device state as specified in chapter 9 of the usb serial bus specification, rev.2.0 . ? fadden: function address enable read: 0 = device is not in address state. 1 = device is in address state. write: 0 = no effect, only a reset can bring back a device to the default state. 1 = sets device in address state. this occurs after a successful set address request. beforehand, the udp_faddr regis- ter must have been initialized with set address parameters. set address must complete the status stage before setting fadden. refer to chapter 9 of the universal serial bus specification, rev. 2.0 for more details. ? confg: configured read: 0 = device is not in configured state. 1 = device is in configured state. write: 0 = sets device in a non configured state 1 = sets device in configured state. the device is set in configured state when it is in address st ate and receives a successful set configuration request. refer to chapter 9 of the universal serial bus specification, rev. 2.0 for more details. ? rsminpr: resume interrupt request read: 0 = no effect. 1 = the pin ?send_resume? is set to one. a send resume request has been detected and the device can send a remote wake up. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ?? 76543210 ????rsminpr ?confgfadden
737 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 39.6.3 udp function address register register name: udp_faddr address: 0xfffa4008 access type: read-write ? fadd[6:0]: function address value the function address value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence. refer to the universal serial bus specification, rev. 2.0 for more information. after power up or reset, the function address value is set to 0. ? fen: function enable read: 0 = function endpoint disabled. 1 = function endpoint enabled. write: 0 = disables function endpoint. 1 = default value. the function enable bit (fen) allows the microcontroller to enable or disable the function endpoints. the microcontroller sets this bit after receipt of a reset from the host. once this bit is set, the usb device is able to accept and transfer data packets from and to the host. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ?fen 76543210 ?fadd
738 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 39.6.4 udp interrupt enable register register name: udp_ier address: 0xfffa4010 access type: write-only ? ep0int: enable endpoint 0 interrupt ? ep1int: enable endpoint 1 interrupt ? ep2int: enable endpoint 2interrupt ? ep3int: enable endpoint 3 interrupt ? ep4int: enable endpoint 4 interrupt ? ep5int: enable endpoint 5 interrupt 0 = no effect. 1 = enables corresponding endpoint interrupt. ? rxsusp: enable udp suspend interrupt 0 = no effect. 1 = enables udp suspend interrupt. ? rxrsm: enable udp resume interrupt 0 = no effect. 1 = enables udp resume interrupt. ? extrsm: enable external resume interrupt 0 = no effect. 1 = enables external resume interrupt. ? sofint: enable start of frame interrupt 0 = no effect. 1 = enables start of frame interrupt. ? wakeup: enable udp bus wakeup interrupt 0 = no effect. 1 = enables usb bus interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup ? sofint extrsm rxrsm rxsusp 76543210 ep5int ep4int ep3int ep2int ep1int ep0int
739 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 39.6.5 udp interrupt disable register register name: udp_idr address: 0xfffa4014 access type: write-only ? ep0int: disable endpoint 0 interrupt ? ep1int: disable endpoint 1 interrupt ? ep2int: disable endpoint 2 interrupt ? ep3int: disable endpoint 3 interrupt ? ep4int: disable endpoint 4 interrupt ? ep5int: disable endpoint 5 interrupt 0 = no effect. 1 = disables corresponding endpoint interrupt. ? rxsusp: disable udp suspend interrupt 0 = no effect. 1 = disables udp suspend interrupt. ? rxrsm: disable udp resume interrupt 0 = no effect. 1 = disables udp resume interrupt. ? extrsm: disable external resume interrupt 0 = no effect. 1 = disables external resume interrupt. ? sofint: disable start of frame interrupt 0 = no effect. 1 = disables start of frame interrupt ? wakeup: disable usb bus interrupt 0 = no effect. 1 = disables usb bus wakeup interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup ? sofint extrsm rxrsm rxsusp 76543210 ep5int ep4int ep3int ep2int ep1int ep0int
740 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 39.6.6 udp interrupt mask register register name: udp_imr address: 0xfffa4018 access type: read-only ? ep0int: mask endpoint 0 interrupt ? ep1int: mask endpoint 1 interrupt ? ep2int: mask endpoint 2 interrupt ? ep3int: mask endpoint 3 interrupt ? ep4int: mask endpoint 4 interrupt ? ep5int: mask endpoint 5 interrupt 0 = corresponding endpoint interrupt is disabled. 1 = corresponding endpoint interrupt is enabled. ? rxsusp: mask udp suspend interrupt 0 = udp suspend interrupt is disabled. 1 = udp suspend interrupt is enabled. ? rxrsm: mask udp resume interrupt. 0 = udp resume interrupt is disabled. 1 = udp resume interrupt is enabled. ? extrsm: mask external resume interrupt 0 = udp external resume interrupt is disabled. 1 = udp external resume interrupt is enabled. ? sofint: mask start of frame interrupt 0 = start of frame interrupt is disabled. 1 = start of frame interrupt is enabled. ? bit12: udp_imr bit 12 bit 12 of udp_imr cannot be masked and is always read at 1. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup bit12 sofint extrsm rxrsm rxsusp 76543210 ep5int ep4int ep3int ep2int ep1int ep0int
741 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? wakeup: usb bus wakeup interrupt 0 = usb bus wakeup interrupt is disabled. 1 = usb bus wakeup interrupt is enabled. note: when the usb block is in suspend mode, the application may po wer down the usb logic. in this case, any usb host resume request that is made must be taken into account and, thus, the reset value of th e rxrsm bit of the register udp_imr is enabled.
742 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 39.6.7 udp interrupt status register register name: udp_isr address: 0xfffa401c access type: read-only ? ep0int: endpoint 0 interrupt status ? ep1int: endpoint 1 interrupt status ? ep2int: endpoint 2 interrupt status ? ep3int: endpoint 3 interrupt status ? ep4int: endpoint 4 interrupt status ? ep5int: endpoint 5 interrupt status 0 = no endpoint0 interrupt pending. 1 = endpoint0 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading udp_csr0: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 ep0int is a sticky bit. interrupt remains valid until ep0int is cleared by writing in the corresponding udp_csr0 bit. ? rxsusp: udp suspend interrupt status 0 = no udp suspend interrupt pending. 1 = udp suspend interrupt has been raised. the usb device sets this bit when it detects no ac tivity for 3ms. the usb device enters suspend mode. ? rxrsm: udp resume interrupt status 0 = no udp resume interrupt pending. 1 =udp resume interrupt has been raised. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup endbusres sofint extrsm rxrsm rxsusp 76543210 ep5int ep4int ep3int ep2int ep1int ep0int
743 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary the usb device sets this bit when a udp resume signal is detected at its port. after reset, the state of this bit is undefined, the application must clear this bit by setting the rxrsm flag in the udp_icr register. ? extrsm: udp external resume interrupt status 0 = no udp external resume interrupt pending. 1 = udp external resume interrupt has been raised. ? sofint: start of frame interrupt status 0 = no start of frame interrupt pending. 1 = start of frame interrupt has been raised. this interrupt is raised each time a sof token has been detected. it can be used as a synchronization signal by using isochronous endpoints. ? endbusres: end of bus reset interrupt status 0 = no end of bus reset interrupt pending. 1 = end of bus reset interrupt has been raised. this interrupt is raised at the end of a udp reset sequence. the usb device must prepare to receive requests on the end- point 0. the host starts the enumeration, then performs the configuration. ? wakeup: udp resume interrupt status 0 = no wakeup interrupt pending. 1 = a wakeup interrupt (usb host sent a resume or reset) occurred since the last clear. after reset the state of this bit is undefined, the application must clear this bit by setting the wakeup flag in the udp_icr register .
744 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 39.6.8 udp interrupt clear register register name: udp_icr address: 0xfffa4020 access type: write-only ? rxsusp: clear udp suspend interrupt 0 = no effect. 1 = clears udp suspend interrupt. ? rxrsm: clear udp resume interrupt 0 = no effect. 1 = clears udp resume interrupt. ? extrsm: clear udp exte rnal resume interrupt 0 = no effect. 1 = clears udp external resume interrupt. ? sofint: clear start of frame interrupt 0 = no effect. 1 = clears start of frame interrupt. ? endbusres: clear end of bus reset interrupt 0 = no effect. 1 = clears end of bus reset interrupt. ? wakeup: clear wakeup interrupt 0 = no effect. 1 = clears wakeup interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup endbusres sofint extrsm rxrsm rxsusp 76543210 ????????
745 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 39.6.9 udp reset en dpoint register register name: udp_rst_ep address: 0xfffa4028 access type: read-write ? ep0: reset endpoint 0 ? ep1: reset endpoint 1 ? ep2: reset endpoint 2 ? ep3: reset endpoint 3 ? ep4: reset endpoint 4 ? ep5: reset endpoint 5 this flag is used to reset the fifo associated with the endpoint and the bit rxbytecount in the register udp_csrx.it also resets the data toggle to data0. it is useful after removing a halt c ondition on a bulk endpoint. refer to chapter 5.8.5 in the usb serial bus specification, rev.2.0 . warning: this flag must be cleared at the end of the reset. it does not clear udp_csrx flags. 0 = no reset. 1 = forces the corresponding endpoint fif0 pointers to 0, therefore rxbytecnt fi eld is read at 0 in udp_csrx register. reseting the endpoint is a two-step operation: 1. set the corresponding epx field. 2. clear the corresponding epx field. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ?? 76543210 ep5 ep4 ep3 ep2 ep1 ep0
746 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 39.6.10 udp endpoint control and status register register name: udp_csrx [x = 0..5] address: 0xfffa402c access type: read-write warning : due to synchronization between mck and udpck, the soft ware application must wait for the end of the write operation before executing an other write by pollin g the bits which must be set/cleared. //! clear flags of udp udp_csr register and waits for synchronization #define udp_ep_clr_flag(pinterface, endpoint, flags) { \ pinterface->udp_csr[endpoint] &= ~(flags); \ while ( (pinterface->udp_csr[endpoint] & (flags)) == (flags) ); \ } //! set flags of udp udp_csr register and waits for synchronization #define udp_ep_set_flag(pinterface, endpoint, flags) { \ pinterface->udp_csr[endpoint] |= (flags); \ while ( (pinterface->udp_csr[endpoint] & (flags)) != (flags) ); \ } note: in a preemptive environment, set or clear the flag and wait for a time of 1 udpck clock cycle and 1peripheral clock cycle. how- ever, rx_data_blk0, txpktrdy, rx_data_bk1 require wait ti mes of 3 udpck clock cycles and 3 peripheral clock cycles before accessing dpr. ? txcomp: generates an in packet with data previously written in the dpr this flag generates an interr upt while it is set to one. write (cleared by the firmware): 0 = clear the flag, clear the interrupt. 1 = no effect. read (set by the usb peripheral): 0 = data in transaction has not been acknowledged by the host. 1 = data in transaction is achieved, acknowledged by the host. after having issued a data in transaction setting txpktrdy, the device firmware waits for txcomp to be sure that the host has acknowledged the transaction. 31 30 29 28 27 26 25 24 ????? r xbytecnt 23 22 21 20 19 18 17 16 rxbytecnt 15 14 13 12 11 10 9 8 epeds ? ? ? dtgle eptype 76543210 dir rx_data_ bk1 force stall txpktrdy stallsent isoerror rxsetup rx_data_ bk0 txcomp
747 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? rx_data_bk0: receive data bank 0 this flag generates an interr upt while it is set to one. write (cleared by the firmware): 0 = notify usb peripheral device that data have been read in the fifo's bank 0. 1 = to leave the read value unchanged. read (set by the usb peripheral): 0 = no data packet has been received in the fifo's bank 0. 1 = a data packet has been received, it has been stored in the fifo's bank 0. when the device firmware has polled this bit or has been interr upted by this signal, it must transfer data from the fifo to the microcontroller memory. the nu mber of bytes received is av ailable in rxbytcent field. bank 0 fifo values are read through the udp_fdrx register. once a transfer is done, the device firmware must release bank 0 to the usb peripheral device by clearing rx_data_bk0. after setting or clearing this bit, a wait time of 3 udpck clock cycles and 3 peripheral cl ock cycles is required before accessing dpr. ? rxsetup: received setup this flag generates an interr upt while it is set to one. read: 0 = no setup packet available. 1 = a setup data packet has been sent by the host and is available in the fifo. write: 0 = device firmware notifies the usb peripheral device that it has read the setup data in the fifo. 1 = no effect. this flag is used to notify the usb device firmware that a valid setup data packet has been sent by the host and success- fully received by the usb device. the usb device firmware may transfer setup data from the fifo by reading the udp_fdrx register to the microcontroller memory. once a transfer has been done, rxsetup must be cleared by the device firmware. ensuing data out transaction is not accepted while rxsetup is set. ? stallsent: stall sent (control, bulk interrupt endpoints)/isoerror (isochronous endpoints) this flag generates an interr upt while it is set to one. stallsent: this ends a stall handshake. read: 0 = the host has not acknowledged a stall. 1 = host has acknowledged the stall. write: 0 = resets the stallsent flag, clears the interrupt. 1 = no effect. this is mandatory for the device firmware to clear this flag. otherwise the interrupt remains.
748 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary refer to chapters 8.4.5 and 9.4.5 of the universal serial bus s pecification, rev. 2.0 for more information on the stall handshake. isoerror: a crc error has been detected in an isochronous transfer. read: 0 = no error in the prev ious isochronous transfer. 1 = crc error has been detected, data available in the fifo are corrupted. write: 0 = resets the isoerror flag, clears the interrupt. 1 = no effect. ? txpktrdy: transmit packet ready this flag is cleared by the usb device. this flag is set by the usb device firmware. read: 0 = there is no data to send. 1 = the data is waiting to be sent upon reception of token in. write: 0 = can be used in the procedure to cancel transmission data. (see, section 39.5.2.9 ?transmit data cancellation? on page 729 ) 1 = a new data payload has been written in the fifo by the firmware and is ready to be sent. this flag is used to generate a data in transaction (device to host). device firmware checks that it can write a data payload in the fifo, checking that txpktrdy is cl eared. transfer to the fi fo is done by writing in the udp_fdrx register. once the data payload has been transferred to the fifo, the firmwar e notifies the usb device setting txpktrdy to one. usb bus transactions can start. txcomp is set once the data payload has been received by the host. after setting or clearing this bit, a wait time of 3 udpck clock cycles and 3 peripheral cl ock cycles is required before accessing dpr. ? forcestall: force stall (used by control, bulk and isochronous endpoints) read: 0 = normal state. 1 = stall state. write: 0 = return to normal state. 1 = send stall to the host. refer to chapters 8.4.5 and 9.4.5 of the universal serial bus s pecification, rev. 2.0 for more information on the stall handshake. control endpoints: during the data stage and status stage, this bit indicates that the microcontroller cannot complete the request. bulk and interrupt endpoints: this bit notifies the host that the endpoint is halted.
749 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary the host acknowledges the stall, device fi rmware is notified by the stallsent flag. ? rx_data_bk1: receive data bank 1 (only used by endpoints with ping-pong attributes) this flag generates an interr upt while it is set to one. write (cleared by the firmware): 0 = notifies usb device that data have been read in the fifo?s bank 1. 1 = to leave the read value unchanged. read (set by the usb peripheral): 0 = no data packet has been received in the fifo's bank 1. 1 = a data packet has been received, it has been stored in fifo's bank 1. when the device firmware has polled this bit or has been interr upted by this signal, it must transfer data from the fifo to microcontroller memory. the number of bytes received is available in rxbytecnt field. bank 1 fifo values are read through udp_fdrx register. once a transfer is done, the device firmware must release bank 1 to the usb device by clear- ing rx_data_bk1. after setting or clearing this bit, a wait time of 3 udpck clock cycles and 3 peripheral cl ock cycles is required before accessing dpr. ? dir: transfer direction (only available for control endpoints) read-write 0 = allows data out transactio ns in the control data stage. 1 = enables data in transactions in the control data stage. refer to chapter 8.5.3 of the universal serial bus specification, rev. 2.0 for more information on the control data stage. this bit must be set before udp_csrx/rxsetup is cleared at the end of the setup stage. according to the request sent in the setup data packet, the data stage is either a device to host (dir = 1) or host to device (dir = 0) data transfer. it is not necessary to check this bit to reve rse direction for the status stage. ? eptype[2:0]: endpoint type ? dtgle: data toggle read-only 0 = identifies data0 packet. 1 = identifies data1 packet. read-write 000 control 001 isochronous out 101 isochronous in 010 bulk out 110 bulk in 011 interrupt out 111 interrupt in
750 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary refer to chapter 8 of the universal serial bus specification, rev. 2.0 for more information on data0, data1 packet definitions. ? epeds: endpoint enable disable read: 0 = endpoint disabled. 1 = endpoint enabled. write: 0 = disables endpoint. 1 = enables endpoint. control endpoints are always enabled. reading or writing this field has no effect on control endpoints. note: after reset, all endpoints are configured as control endpoints (zero). ? rxbytecnt[10:0]: number of bytes available in the fifo read-only when the host sends a data packet to the device, the usb device stores the data in the fifo and notifies the microcontrol- ler. the microcontroller can lo ad the data from t he fifo by reading rxbytecent by tes in the udp_fdrx register.
751 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 39.6.11 udp fifo data register register name: udp_fdrx [x = 0..5] address: 0xfffa404c access type: read-write ? fifo_data[7:0]: fifo data value the microcontroller can push or pop values in the fifo through this register. rxbytecnt in the corresponding udp_csrx re gister is the number of bytes to be read from the fifo (sent by the host). the maximum number of bytes to write is fixed by the max packet size in the standard endpoint descriptor. it can not be more than the physical memory size associated to the endpoint. refer to the universal serial bus specification, rev. 2.0 for more information. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ?? 76543210 fifo_data
752 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 39.6.12 udp transceiver control register register name: udp_txvc address: 0xfffa4074 access type: read-write warning: the udp peripheral clock in the power management controller (pmc) must be enabled before any read/write operations to the udp registers including the udp_txvc register. ? txvdis: transceiver disable when udp is disabled, power consumption can be reduced significantly by disab ling the embedded transceiver. this can be done by setting txvdis field. to enable the transceiver, txvdis must be cleared. ? puon: pullup on 0: the 1.5k integrated pullup on dp is disconnected. 1: the 1.5 k integrated pullup on dp is connected. note : if the usb pullup is not connected on dp, the user shou ld not write in any udp register other than the udp_txvc register. this is because if dp and dm are floating at 0, or pulled down, then se0 is received by the device with the conse- quence of a usb reset. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? puon txvdis 76543210 ?????? ??
753 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 40. usb host port (uhp) 40.1 description the usb host port (uhp) interfaces the usb with the host application. it handles open hci protocol (open host controller interface) as well as usb v2.0 full-speed and low-speed protocols. the usb host port integrates a root hub and transceivers on downstream ports. it provides sev- eral high-speed half-duplex serial communication ports at a baud rate of 12 mbit/s. up to 127 usb devices (printer, camera, mouse, keyboard , disk, etc.) and the usb hub can be connected to the usb host in the usb ?tiered star? topology. the usb host port controller is fully complia nt with the openhci spec ification. the usb host port user interface (registers description) can be found in the open hci rev 1.0 specification available on http://h18000.www1.hp.com/productinfo/development/openhci.html . the standard ohci usb stack driver can be easily ported to at mel?s architecture in t he same way all existing class drivers run without hardware specialization. this means that all standard class devices are automatically detected and available to the user application. as an example, integrating an hid (human interface device) class driver provides a plug & play feature for all usb keyboards and mouses. 40.2 block diagram figure 40-1. block diagram access to the usb host operational registers is achieved through the ahb bus slave interface. the openhci host controller initia lizes master dma transfers th rough the asb bus master inter- face as follows: ? fetches endpoint descriptors and transfer descriptors ? access to endpoint data from system memory port s/m port s/m usb transceiver usb transceiver dp dm dp dm embedded usb v2.0 full-speed transceiver root hub and host sie list processor block fifo 64 x 8 hci slave block ohci registers ohci root hub registers ahb ed & td regsisters control hci master block data uhp_int mck uhpck ahb slave master
754 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? access to the hc communication area ? write status and retire transfer descriptor memory access errors (abort, misalignment) lead to an ?unrecoverableerror? indicated by the corresponding flag in the host controller operational registers. the usb root hub is integrated in the usb host. several usb downstream ports are available. the number of downstream ports can be determined by the software driver reading the root hub?s operational registers. device connection is automatically detected by the usb host port logic. usb physical transceivers are integrated in the product and driven by the root hub?s ports. over current protection on ports can be activated by the usb host controller. atmel?s standard product does not dedicate pads to external over current protection. 40.3 product dependencies 40.3.1 i/o lines dps and dms are not controlled by any pio controllers. the embedded usb physical transceiv- ers are controlled by the usb host controller. 40.3.2 power management the usb host controller requires a 48 mhz clock. this clock must be generated by a pll with a correct accuracy of 0.25%. thus the usb device peripheral receives two clocks from the power management controller (pmc): the master clock mck used to drive the peripheral user interface (mck domain) and the uhpclk 48 mhz clock used to interface with the bus usb signals (recovered 12 mhz domain). 40.3.3 interrupt the usb host interface has an interrupt line connected to the advanced interrupt controller (aic). handling usb host interrupts requires programming the aic before configuring the uhp. 40.4 functional description please refer to the open host controller interface specification for usb release 1.0.a. 40.4.1 host controller interface there are two communication channels between the host controller and the host controller driver. the first channel uses a set of operatio nal registers located on the usb host controller. the host controller is the target for all co mmunications on this channel. the operational regis- ters contain control, status and list pointer registers. they are mapped in the memory mapped area. within the operational register set there is a pointer to a location in the processor address space named the host controller communication area (hcca). the hcca is the second com- munication channel. the host controller is the master for all communication on this channel. the hcca contains the head pointers to the interrupt endpoint descrip tor lists, the head pointer to the done queue and status information associated with start-of-frame processing. the basic building blocks for communication across the interface are endpoint descriptors (ed, 4 double words) and transfer descriptors (td, 4 or 8 double words). the host controller assigns
755 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary an endpoint descriptor to each endpoint in the system. a queue of transfer descriptors is linked to the endpoint descriptor for the specific endpoint. figure 40-2. usb host communication channels 40.4.2 host controller driver figure 40-3. usb host drivers operational registers mode hcca status event frame int ratio control bulk host controller communications area interrupt 0 interrupt 1 interrupt 2 interrupt 31 done . . . . . . open hci shared ram device register in memory space device enumeration = transfer descriptor = endpoint descriptor . . . host controller hardware hub driver host controller driver usb driver mini driver class driver class driver user application kernel drivers user space hardware
756 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary usb handling is done through several layers as follows: ? host controller hardware and serial engine: transmits and receives usb data on the bus. ? host controller driver: drives the host controller hardware and handles the usb protocol. ? usb bus driver and hub driver: handles usb commands and enumeration. offers a hardware independent interface. ? mini driver: handles device specific commands. ? class driver: handles standard devices. this acts as a generic driver for a class of devices, for example the hid driver. 40.5 typical connection figure 40-4. board schematic to interface uhp device controller a termination serial resistor must be connected to hdp and hdm. the resistor value is defined in the electrical specification of the product (r ext ). r ext hdma or hdmb hdpa or hdpb 10nf 100nf 10 f 5v 0.20a type a connector r ext
757 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 41. image sensor interface (isi) 41.1 overview the image sensor interface (isi) connects a cmos-type image sensor to the processor and provides image capture in various formats. it does data conversion, if necessary, before the stor- age in memory through dma. the isi supports color cmos image sensor and grayscale image sensors with a reduced set of functionalities. in grayscale mode, the data stream is stored in memory without any processing and so is not compatible with th e lcd controller. internal fifos on the preview and codec paths are used to store the incoming data. the rgb output on the preview path is compatible with the lcd controller. this module outputs the data in rgb format (lcd compatible) and has scaling capabilities to make it compliant to the lcd display resolution (see table 41-3 on page 760 ). several input formats such as preprocessed rgb or ycbcr are supported through the data bus interface. it supports two modes of synchronization: 1. the hardware with isi_vsync and isi_hsync signals 2. the international telecommunication union recommendation itu-r bt.656-4 start-of- active-video (sav) and end-of-active-video (eav) synchronization sequence. using eav/sav for synchronizatio n reduces the pin count (isi _vsync, isi_hsync not used). the polarity of the synchronization pulse is programmable to comply with the sensor signals. figure 41-1. isi connection example table 41-1. i/o description signal dir description isi_vsync in vertical synchronization isi_hsync in horizontal synchronization isi_data[11..0] in sensor pixel data isi_mck out master clock provided to the image sensor isi_pck in pixel clock provided by the image sensor image sensor image sensor interface data[11..0] isi_data[11..0] clk isi_mck pclk isi_pck vsync hsync isi_vsync isi_hsync
758 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 41.2 block diagram figure 41-2. image sensor interface block diagram 41.3 functional description the image sensor interface (isi) supports di rect connection to the itu-r bt. 601/656 8-bit mode compliant sensors and up to 12-bit grayscale sensors. it receives the image data stream from the image sensor on the 12-bit data bus. this module receives up to 12 bits for data, the ho rizontal and vertical sy nchronizations and the pixel clock. the reduced pin count alternative for synchronization is supported for sensors that embed sav (start of active vide o) and eav (end of active video) delimiters in the data stream. the image sensor interface interrupt line is gene rally connected to the advanced interrupt con- troller and can trigger an interrupt at the beginning of each frame and at the end of a dma frame transfer. if the sav/eav synchroniz ation is used, an in terrupt can be trigge red on each delimiter event. for 8-bit color sensors, the data stream received can be in several possible formats: ycbcr 4:2:2, rgb 8:8:8, rgb 5:6:5 and may be processed before the storage in memory. the data stream may be sent on both preview path and codec path if the bit codec_on in the isi_cr1 is one. to optimize the bandwidth, the codec path should be enabled only when a capture is required. in grayscale mode, the input data stream is stored in memory without any processing. the 12-bit data, which represent the grayscale level for the pixel, is stored in memory one or two pixels per word, depending on the gs_mode bit in the isi_cr2 register. the data is stored via the pre- view path without any treatment (scaling, color conversion,?). the size of the sensor must be programmed in the fields im_vsize and im_hsize in the isi_cr2 register.the programming of the preview path register (isi_psize) is not necessary. the codec datapath is not available when grayscale image is selected. a frame rate counter allows users to capture all frames or 1 out of every 2 to 8 frames. timing signals interface ccir-656 embedded timing decoder(sav/eav) pixel sampling module clipping + color conversion ycc to rgb 2-d image scaler pixel formatter rx direct display fifo core video arbiter camera ahb master interface apb interface camera interrupt controller config registers clipping + color conversion rgb to ycc rx direct capture fifo scatter mode support packed formatter frame rate ycbcr 4:2:2 8:8:8 5:6:5 rgb cmos sensor pixel input up to 12 bit hsync/len vsync/fen cmos sensor pixel clock input pixel clock domain ahb clock domain apb clock domain from rx buffers camera interrupt request line codec_on ahb bus apb bus
759 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 41.3.1 data timing the two data timings using hori zontal and vertical synchroni zation and eav/sav sequence syn- chronization are shown in figure 41-3 and figure 41-4 . in the vsync/hsync synchronization, the valid da ta is captured with the active edge of the pixel clock (isi_pck), after sfd lines of vertical blanking and sld pixel clock periods delay pro- grammed in the control register. the itu-rbt.656-4 defines the functional timing for an 8-bit wide interface. there are two timing reference signals, one at the beginning of each video data block sav (0xff000080) and one at the end of each video data block eav(0xff00009d). only data sent between eav and sav is capt ured. horizontal blanking and vert ical blanking are ignored. use of the sav and eav synchronization eliminates the isi_vsync and isi_hsync signals from the interface, thereby reducing the pin count. in order to retrieve both frame and line synchronization properly, at least one line of vertical blanking is mandatory. figure 41-3. hsync and vsync synchronization figure 41-4. sav and eav sequence synchronization isi_vsync isi_hsync isi_pck frame 1 line ycby crycb y crycby cr data[7..0] isii_pck cr y cb y cr y y cr y cb ff 00 data[7..0] ff 00 00 80 y cb y 00 9d sav eav active video
760 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 41.3.2 data ordering the rgb color space format is required for viewing images on a display screen preview, and the ycbcr color space format is required for encoding. all the sensors do not output the ycbcr or rgb components in the same order. the isi allows the user to program the same component order as the sensor, reducing software treatments to restore the right format. table 41-2. data ordering in ycbcr mode mode byte 0 byte 1 byte 2 byte 3 default cb(i) y(i) cr(i) y(i+1) mode1 cr(i) y(i) cb(i) y(i+1) mode2 y(i) cb(i) y(i+1) cr(i) mode3 y(i) cr(i) y(i+1) cb(i) table 41-3. rgb format in default mode, rgb_cfg = 00, no swap mode byte d7 d6 d5 d4 d3 d2 d1 d0 rgb 8:8:8 byte 0 r7(i) r6(i) r5(i) r4(i) r3(i) r2(i) r1(i) r0(i) byte 1 g7(i) g6(i) g5(i) g4(i) g3(i) g2(i) g1(i) g0(i) byte 2 b7(i) b6(i) b5(i) b4 (i) b3(i) b2(i) b1(i) b0(i) byte 3 r7(i+1) r6(i+1) r5(i+1) r4(i +1) r3(i+1) r2(i+1) r1(i+1) r0(i+1) rgb 5:6:5 byte 0 r4(i) r3(i) r2(i) r1(i) r0(i) g5(i) g4(i) g3(i) byte 1 g2(i) g1(i) g0(i) b4(i) b3(i) b2(i) b1(i) b0(i) byte 2 r4(i+1) r3(i+1) r2(i+1) r1(i+1) r0(i+1) g5(i+1) g4(i+1) g3(i+1) byte 3 g2(i+1) g1(i+1) g0(i+1) b4(i+1) b3(i+1) b2(i+1) b1(i+1) b0(i+1) table 41-4. rgb format, rgb_cfg = 10 (mode 2), no swap mode byte d7 d6 d5 d4 d3 d2 d1 d0 rgb 5:6:5 byte 0 g2(i) g1(i) g0(i) r4(i) r3(i) r2(i) r1(i) r0(i) byte 1 b4(i) b3(i) b2(i) b1 (i) b0(i) g5(i) g4(i) g3(i) byte 2 g2(i+1) g1(i+1) g0(i+1) r4(i+1) r3(i+1) r2(i+1) r1(i+1) r0(i+1) byte 3 b4(i+1) b3(i+1) b2(i+1) b1(i+1) b0(i+1) g5(i+1) g4(i+1) g3(i+1)
761 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary the rgb 5:6:5 input format is processed to be displayed as rgb 5:5:5 format, compliant with the 16-bit mode of the lcd controller. 41.3.3 clocks the sensor master clock (isi_mck) can be generated either by the advanced power manage- ment controller (apmc) through a programmable clock output or by an external oscillator connected to the sensor. none of the sensors embeds a power management controller, so providing the clock by the apmc is a simple and efficient way to control power consumption of the system. care must be taken when programming the system clock. the isi has two clock domains, the system bus clock and the pixel clock provided by sensor. the two clock domains are not syn- chronized, but the system clock must be faster than pixel clock. table 41-5. rgb format in default mode, rgb_cfg = 00, swap activated mode byte d7 d6 d5 d4 d3 d2 d1 d0 rgb 8:8:8 byte 0 r0(i) r1(i) r2(i) r3(i) r4(i) r5(i) r6(i) r7(i) byte 1 g0(i) g1(i) g2(i) g3(i) g4(i) g5(i) g6(i) g7(i) byte 2 b0(i) b1(i) b2(i) b3 (i) b4(i) b5(i) b6(i) b7(i) byte 3 r0(i+1) r1(i+1) r2(i+1) r3(i +1) r4(i+1) r5(i+1) r6(i+1) r7(i+1) rgb 5:6:5 byte 0 g3(i) g4(i) g5(i) r0(i) r1(i) r2(i) r3(i) r4(i) byte 1 b0(i) b1(i) b2(i) b3 (i) b4(i) g0(i) g1(i) g2(i) byte 2 g3(i+1) g4(i+1) g5(i+1) r0(i+1) r1(i+1) r2(i+1) r3(i+1) r4(i+1) byte 3 b0(i+1) b1(i+1) b2(i+1) b3(i+1) b4(i+1) g0(i+1) g1(i+1) g2(i+1)
762 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 41.3.4 preview path 41.3.4.1 scaling, deci mation (subsampling) this module resizes captured 8-bit color sensor images to fit the lcd display format. the resize module performs only downscaling. the same ra tio is applied for both horizontal and vertical resize, then a fractional decimation algorithm is applied. the decimation factor is a multiple of 1/16 and values 0 to 15 are forbidden. example: input 1280*1024 output=640*480 hratio = 1280/640 =2 vratio = 1024/480 =2.1333 the decimation factor is 2 so 32/16. table 41-6. decimation factor dec value 0->15 16 17 18 19 ... 124 125 126 127 dec factor x 1 1.063 1.125 1.188 ... 7.750 7.813 7.875 7.938 table 41-7. decimation and scaler offset values input output 352*288 640*480 800*600 1280*1024 1600*1200 2048*1536 vga 640*480 fna1620324051 qvga 320*240 f1632406480102 cif 352*288 f162633566685 qcif 176*144 f 16 53 66 113 133 170
763 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 41-5. resize examples 41.3.4.2 color space conversion this module converts ycrcb or yuv pixels to rg b color space. clipping is performed to ensure that the samples value do not exceed the allowable range. the conversion matrix is defined below and is fully programmable: example of programmable value to convert ycrcb to rgb: an example of programmable value to convert from yuv to rgb: 1280 1024 480 640 32/16 decimation 1280 1024 288 352 56/16 decimation r g b c 0 0 c 1 c 0 c 2 ? c 3 ? c 0 c 4 0 yy off ? c b c boff ? c r c roff ? = r 1,164 y 16 ? () ? 1,596 c r 128 ? () ? + = g 1,164 y 16 ? () 0,813 c r 128 ? () ? ? 0,392 c b 128 ? () ? ? ? = b 1,164 y 16 ? () ? 2,107 c b 128 ? () ? + = ? ? ? ? ? ry 1,596 v ? + = gy 0,394 u ? ? 0,436 v ? ? = by 2,032 u ? + = ? ? ? ? ?
764 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 41.3.4.3 memory interface preview datapath contains a data formatter that converts 8:8:8 pixel to rgb 5:5:5 format compli- ant with 16-bit format of the lcd controller. in general, when converting from a color channel with more bits to one with fewer bits, formatter module discards the lower-order bits. example: converting from rgb 8:8:8 to rgb 5:6:5, it discards the three lsbs from the red and blue chan- nels, and two lsbs from the green channel. when grayscale mode is enabled, two memory format are supported. one mode supports 2 pixels per word, and the other mode supports 1 pixel per word. 41.3.4.4 fifo and dma features both preview and codec datapaths contain fifos, asynchronous buffers that are used to safely transfer formatted pixels from pixel clock domain to ahb clock domain. a video arbiter is used to manage fifo thresholds and triggers a relevant dma request through the ahb master inter- face. thus, depending on fifo state, a specified length burst is asserted. regarding ahb master interface, it supports scatter dma mode through linked list operation. this mode of oper- ation improves flexibility of image buffer location and allows the user to allocate two or more frame buffers. the destination frame buffers are defined by a series of frame buffer descriptors (fbd). each fbd controls the transfer of one entire frame and then optionally loads a further fbd to switch the dma operation at another frame buffer address. the fbd is defined by a series of two words. the first one defines the current frame buffer address, and the second defines the next fbd memory location. this dm a transfer mode is only available for preview datapath and is configured in the isi_ppfbd register that indicates the memory location of the first fbd. the primary fbd is programmed into the camera interface controller. the data to be transferred described by an fbd requires several burst access. in the example below, the use of 2 ping- pong frame buffers is described. 41.3.4.5 example the first fbd, stored at address 0x30000, defines the location of the first frame buffer. destination address: frame buffer id0 0x02a000 next fbd address: 0x30010 second fbd, stored at address 0x30010, defines the location of the second frame buffer. destination address: frame buffer id1 0x3a000 transfer width: 32 bit next fbd address: 0x30000, wrapping to first fbd. using this technique, several frame buffers can be configured through the linked list. figure 41-6 illustrates a typical three frame bu ffer application. frame n is ma pped to frame buffer 0, frame n+1 is mapped to frame buffer 1, frame n+2 is mapped to frame buffer 2, further frames wrap. a codec request occurs, and the full-size 4:2:2 encoded frame is stored in a dedicated memory space. table 41-8. grayscale memory mapping configuration for 12-bit data gs_mode data[31:24] data[23:16] data[15:8] data[7:0] 0 p_0[11:4] p_0[3:0], 0000 p_1[11:4] p_1[3:0], 0000 1 p_0[11:4] p_0[3:0], 0000 0 0
765 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 41-6. three frame buffers application and memory mapping 41.3.5 codec path 41.3.5.1 color space conversion depending on user selection, this module can be bypassed so that input ycrcb stream is directly connected to the format converter module. if the rgb input stream is selected, this mod- ule converts rgb to ycrcb color sp ace with the formulas given below: an example of coefficients are given below: frame n frame n+1 frame n+2 frame n-1 frame n+3 frame n+4 frame buffer 0 frame buffer 1 frame buffer 3 4:2:2 image full roi isi config space codec request codec done lcd memory space y c r c b c 0 c 1 c 2 c 3 c ? 4 c ? 5 c ? 6 c ? 7 c 8 r g b y off cr off cb off + = y 0,257 r ? 0,504 g 0,098 b 16 + ? + ? + = c r 0,439 r ? 0,368 g ? ? 0,071 b 128 + ? ? = c b 0,148 r ? ? 0,291 g 0,439 b 128 + ? + ? ? = ? ? ? ? ?
766 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 41.3.5.2 memory interface dedicated fifo are used to support packed memory mapping. ycrcb pixel components are sent in a single 32-bit word in a contiguous space (packed). data is stored in the order of natural scan lines. planar mode is not supported. 41.3.5.3 dma features unlike preview datapath, codec datapath dma mode does not support linked list operation. only the codec_dma_addr register is used to configure the frame buffer base address.
767 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 41.4 image sensor interface (isi) user interface note: several parts of the isi controller use the pixel clock prov ided by the image sensor (isi_pck ). thus the user must first p rogram the image sensor to provide this clock (isi_pck) before programming the image sensor controller. table 41-9. register mapping offset register name access reset 0x00 isi control 1 register isi_cr1 read-write 0x00000002 0x04 isi control 2 register isi_cr2 read-write 0x00000000 0x08 isi status register isi_sr read 0x00000000 0x0c isi interrupt enable register isi_ier read-write 0x00000000 0x10 isi interrupt disable register isi_idr read-write 0x00000000 0x14 isi interrupt mask register isi_imr read-write 0x00000000 0x18 reserved - - - 0x1c reserved - - - 0x20 isi preview size register isi_psize read-write 0x00000000 0x24 isi preview decimation factor register isi_pdecf read-write 0x00000010 0x28 isi preview primary fbd register isi_ppfbd read-write 0x00000000 0x2c isi codec dma base address register isi_cdba read-write 0x00000000 0x30 isi csc ycrcb to rgb set 0 register isi_y2r_set0 read-write 0x6832cc95 0x34 isi csc ycrcb to rgb set 1 register isi_y2r_set1 read-write 0x00007102 0x38 isi csc rgb to ycrcb set 0 register isi_r2y_set0 read-write 0x01324145 0x3c isi csc rgb to ycrcb set 1 register isi_r2y_set1 read-write 0x01245e38 0x40 isi csc rgb to ycrcb set 2 register isi_r2y_set2 read-write 0x01384a4b 0x44-0xf8 reserved ? ? ? 0xfc reserved ? ? ?
768 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 41.4.1 isi control 1 register name: isi_cr1 address: 0xfffc0000 acess: read-write reset: 0x00000002 ? isi_rst: image sensor interface reset write-only. refer to bit softrst in section 41.4.3 ?isi status register? on page 772 for soft reset status. 0: no action 1: resets the image sensor interface. ? isi_dis: image sensor disable: 0: enable the image sensor interface. 1: finish capturing the current frame and then shut down the module. ? hsync_pol: horizontal synchronization polarity 0: hsync active high 1: hsync active low ? vsync_pol: vertical synchronization polarity 0: vsync active high 1: vsync active low ? pixclk_pol: pixel clock polarity 0: data is sampled on rising edge of pixel clock 1: data is sampled on fa lling edge of pixel clock ? emb_sync: embedded synchronization 0: synchronization by hsync, vsync 1: synchronization by embedded synchronization sequence sav/eav ? crc_sync: embedded synchronization 0: no crc correction is performed on embedded synchronization 31 30 29 28 27 26 25 24 sfd 23 22 21 20 19 18 17 16 sld 15 14 13 12 11 10 9 8 codec_on thmask full - frate 76543210 crc_sync emb_sync - pixclk_pol vsync_pol hsync_pol isi_dis isi_rst
769 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 1: crc correction is performed. if the correction is not possib le, the current frame is disc arded and the crc_err is set in the status register. ? frate: frame rate [0..7] 0: all the frames are captured, else one frame every frate+1 is captured. ? full: full mode is allowed 1: both codec and preview datapaths are working simultaneously ? thmask: threshold mask 0: 4, 8 and 16 ahb bursts are allowed 1: 8 and 16 ahb bursts are allowed 2: only 16 ahb bursts are allowed ? codec_on: enable the codec path enable bit write-only. 0: the codec path is disabled 1: the codec path is enabled and the next fr ame is captured. refer to bit cdc_pnd in ?isi status register? on page 772 . ? sld: start of line delay sld pixel clock periods to wait before the beginning of a line. ? sfd: start of frame delay sfd lines are skipped at the beginning of the frame.
770 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 41.4.2 isi control 2 register name: isi_cr2 address: 0xfffc0004 acess: read-write reset: 0x0 ? im_vsize: vertical size of the image sensor [0..2047] vertical size = im_vsize + 1 ?gs_mode 0: 2 pixels per word 1: 1 pixel per word ? rgb_mode: rgb input mode 0: rgb 8:8:8 24 bits 1: rgb 5:6:5 16 bits ? grayscale 0: grayscale mode is disabled 1: input image is assumed to be grayscale coded ?rgb_swap 0: d7 -> r7 1: d0 -> r7 the rgb_swap has no effect when the grayscale mode is enabled. ? col_space: color space for the image data 0: ycbcr 1: rgb ? im_hsize: horizontal size of the image sensor [0..2047] horizontal size = im_hsize + 1 31 30 29 28 27 26 25 24 rgb_cfg ycc_swap - im_hsize 23 22 21 20 19 18 17 16 im_hsize 15 14 13 12 11 10 9 8 col_space rgb_swap grayscale rgb_mode gs_mode im_vsize 76543210 im_vsize
771 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? ycc_swap: defines the ycc image data ? rgb_cfg: defines rgb pattern when rgb_mode is set to 1 if rgb_mode is set to rgb 8:8:8, th en rgb_cfg = 0 implies rgb color sequen ce, else it implies bgr color sequence. ycc_swap byte 0 byte 1 byte 2 byte 3 00: default cb(i) y(i) cr(i) y(i+1) 01: mode1 cr(i) y(i) cb(i) y(i+1) 10: mode2 y(i) cb(i) y(i+1) cr(i) 11: mode3 y(i) cr(i) y(i+1) cb(i) rgb_cfg byte 0 byte 1 byte 2 byte 3 00: default r/g(msb) g(lsb)/b r/g(msb) g(lsb)/b 01: mode1 b/g(msb) g(lsb)/r b/g(msb) g(lsb)/r 10: mode2 g(lsb)/r b/g (msb) g(lsb)/r b/g(msb) 11: mode3 g(lsb)/b r/g(msb) g(lsb)/b r/g(msb)
772 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 41.4.3 isi status register name: isi_sr address: 0xfffc0008 acess: read reset: 0x0 ? sof: start of frame 0: no start of frame has been detected. 1: a start of frame has been detected. ? dis: image sensor interface disable 0: the image sensor interface is enabled. 1: the image sensor in terface is disabled an d stops capturing data. the dma cont roller and the core can still read the fifos. ? softrst: software reset 0: software reset not asserted or not completed. 1: software reset has completed successfully. ? cdc_pnd: codec request pending 0: no request asserted. 1: a codec request is pending. if a codec request is asserted during a frame, the cdc_pnd bit rises until the start of a new frame. the capture is completed when the flag fo_c_emp = 1. ? crc_err: crc synchronization error 0: no crc error in the embedd ed synchronization frame (sav/eav) 1: the crc_sync is enabled in the control register and an error has been detected and not corrected. the frame is dis- carded and the isi waits for a new one. ? fo_c_ovf: fifo codec overflow 0: no overflow 1: an overrun condition has occurred in input fifo on the codec path. the overrun happens when the fifo is full and an attempt is made to write a new sample to the fifo. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????fr_ovrfo_c_emp 76543210 fo_p_emp fo_p_ovf fo_c_ovf crc_err cdc_pnd softrst dis sof
773 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? fo_p_ovf: fifo preview overflow 0: no overflow 1: an overrun condition has occurred in input fifo on the preview path. the overrun happens when the fifo is full and an attempt is made to write a new sample to the fifo. ? fo_p_emp 0:the dma has not finished transferring all the contents of the preview fifo. 1:the dma has finished transferring all the contents of the preview fifo. ?fo_c_emp 0: the dma has not finished transferring all the contents of the codec fifo. 1: the dma has finished transferring all the contents of the codec fifo. ? fr_ovr: frame rate overrun 0: no frame overrun. 1: frame overrun, the current frame is being skipped because a vsync signal has been detected while flushing fifos.
774 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 41.4.4 interrupt enable register name: isi_ier address: 0xfffc000c acess: read-write reset: 0x0 ? sof: start of frame 1: enables the start of frame interrupt. ? dis: image sensor interface disable 1: enables the dis interrupt. ? softrst: soft reset 1: enables the soft reset completion interrupt. ? crc_err: crc synchronization error 1: enables the crc_sync interrupt. ? fo_c_ovf: fifo codec overflow 1: enables the codec fifo overflow interrupt. ? fo_p_ovf: fifo preview overflow 1: enables the preview fifo overflow interrupt. ? fo_p_emp 1: enables the preview fifo empty interrupt. ?fo_c_emp 1: enables the codec fifo empty interrupt. ? fr_ovr: frame overrun 1: enables the frame overrun interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????fr_ovrfo_c_emp 76543210 fo_p_emp fo_p_ovf fo_c_o vf crc_err ? softrst dis sof
775 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 41.4.5 isi interrupt disable register name: isi_idr address: 0xfffc0010 acess: read-write reset: 0x0 ? sof: start of frame 1: disables the start of frame interrupt. ? dis: image sensor interface disable 1: disables the dis interrupt. ?softrst 1: disables the soft reset completion interrupt. ? crc_err: crc synchronization error 1: disables the crc_sync interrupt. ? fo_c_ovf: fifo codec overflow 1: disables the codec fifo overflow interrupt. ? fo_p_ovf: fifo preview overflow 1: disables the preview fifo overflow interrupt. ? fo_p_emp 1: disables the preview fifo empty interrupt. ?fo_c_emp 1: disables the codec fifo empty interrupt. ?fr_ovr 1: disables frame overrun interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????fr_ovrfo_c_emp 76543210 fo_p_emp fo_p_ovf fo_c_o vf crc_err ? softrst dis sof
776 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 41.4.6 isi interrupt mask register name: isi_imr address: 0xfffc0014 acess: read-write reset: 0x0 ? sof: start of frame 0: the start of frame interrupt is disabled. 1: the start of frame interrupt is enabled. ? dis: image sensor interface disable 0: the dis interrupt is disabled. 1: the dis interrupt is enabled. ?softrst 0: the soft reset completion interrupt is enabled. 1: the soft reset completion interrupt is disabled. ? crc_err: crc synchronization error 0: the crc_sync interrupt is disabled. 1: the crc_sync interrupt is enabled. ? fo_c_ovf: fifo codec overflow 0: the codec fifo overflow interrupt is disabled. 1: the codec fifo overflow interrupt is enabled. ? fo_p_ovf: fifo preview overflow 0: the preview fifo overflow interrupt is disabled. 1: the preview fifo overflow interrupt is enabled. ? fo_p_emp 0: the preview fifo empty interrupt is disabled. 1: the preview fifo empty interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????fr_ovrfo_c_emp 76543210 fo_p_emp fo_p_ovf fo_c_o vf crc_err ? softrst dis sof
777 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ?fo_c_emp 0: the codec fifo empty interrupt is disabled. 1: the codec fifo empty interrupt is enabled. ? fr_ovr: frame rate overrun 0: the frame overrun interrupt is disabled. 1: the frame overrun interrupt is enabled.
778 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 41.4.7 isi preview register name: isi_psize address: 0xfffc0020 acess: read-write reset: 0x0 ? prev_vsize: vertical size for the preview path vertical preview size = prev_vsize + 1 (480 max only in rgb mode). ? prev_hsize: horizontal size for the preview path horizontal preview size = prev_hsiz e + 1 (640 max only in rgb mode). 31 30 29 28 27 26 25 24 ?????? prev_hsize 23 22 21 20 19 18 17 16 prev_hsize 15 14 13 12 11 10 9 8 ?????? prev_vsize 76543210 prev_vsize
779 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 41.4.8 isi preview decimation factor register name: isi_pdecf address: 0xfffc0024 acess: read-write reset: 0x00000010 ? dec_factor: decimation factor dec_factor is 8-bit width, range is from 16 to 255. values from 0 to 16 do not perform any decimation. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 dec_factor
780 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 41.4.9 isi preview primary fbd register name: isi_ppfbd address: 0xfffc0028 acess: read-write reset: 0x0 ? prev_fbd_addr: base address for preview frame buffer descriptor written with the address of the start of the preview frame buffer queue, reads as a pointer to the current buffer being used. the frame buffer is forced to word alignment. 31 30 29 28 27 26 25 24 prev_fbd_addr 23 22 21 20 19 18 17 16 prev_fbd_addr 15 14 13 12 11 10 9 8 prev_fbd_addr 76543210 prev_fbd_addr
781 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 41.4.10 isi codec dma base address register name: isi_cdba address: 0xfffc002c acess: read-write reset: 0x0 ? codec_dma_addr: base address for codec dma this register contains codec datapath start address of buffer location. 31 30 29 28 27 26 25 24 codec_dma_addr 23 22 21 20 19 18 17 16 codec_dma_addr 15 14 13 12 11 10 9 8 codec_dma_addr 76543210 codec_dma_addr
782 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 41.4.11 isi color space conversion ycrcb to rgb set 0 register name: isi_y2r_set0 address: 0xfffc0030 acess: read-write reset: 0x6832cc95 ? c0: color space conversion matrix coefficient c0 c0 element, default step is 1/128, ranges from 0 to 1.9921875 ? c1: color space conversion matrix coefficient c1 c1 element, default step is 1/128, ranges from 0 to 1.9921875 ? c2: color space conversion matrix coefficient c2 c2 element, default step is 1/128, ranges from 0 to 1.9921875 ? c3: color space conversion matrix coefficient c3 c3 element default step is 1/128, ranges from 0 to 1.9921875 31 30 29 28 27 26 25 24 c3 23 22 21 20 19 18 17 16 c2 15 14 13 12 11 10 9 8 c1 76543210 c0
783 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 41.4.12 isi color space conversion ycrcb to rgb set 1 register name: isi_y2r_set1 address: 0xfffc0034 acess: read-write reset: 0x00007102 ? c4: color space conversion matrix coefficient c4 c4 element default step is 1/128, ranges from 0 to 3.9921875 ? yoff: color space conversion luminance default offset 0: no offset 1: offset = 128 ? croff: color space conversion red chrominance default offset 0: no offset 1: offset = 16 ? cboff: color space conversion blue chrominance default offset 0: no offset 1: offset = 16 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? cboff croff yoff ? ? ? c4 c4
784 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 41.4.13 isi color space conversion rgb to ycrcb set 0 register name: isi_r2y_set0 address: 0xfffc0038 acess: read-write reset: 0x01324145 ? c0: color space conversion matrix coefficient c0 c0 element default step is 1/256, from 0 to 0.49609375 ? c1: color space conversion matrix coefficient c1 c1 element default step is 1/128, from 0 to 0.9921875 ? c2: color space conversion matrix coefficient c2 c2 element default step is 1/512, from 0 to 0.2480468875 ? roff: color space conversion red component offset 0: no offset 1: offset = 16 31 30 29 28 27 26 25 24 ???????roff 23 22 21 20 19 18 17 16 c2 15 14 13 12 11 10 9 8 c1 76543210 c0
785 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 41.4.14 isi color space conversion rgb to ycrcb set 1 register name: isi_r2y_set1 address: 0xfffc003c acess: read-write reset: 0x01245e38 ? c3: color space conversion matrix coefficient c3 c0 element default step is 1/128, ranges from 0 to 0.9921875 ? c4: color space conversion matrix coefficient c4 c1 element default step is 1/256, ranges from 0 to 0.49609375 ? c5: color space conversion matrix coefficient c5 c1 element default step is 1/512, ranges from 0 to 0.2480468875 ? goff: color space conversion green component offset 0: no offset 1: offset = 128 31 30 29 28 27 26 25 24 ???????goff 23 22 21 20 19 18 17 16 c5 15 14 13 12 11 10 9 8 c4 76543210 c3
786 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 41.4.15 isi color space conversion rgb to ycrcb set 2 register name: isi_r2y_set2 address: 0xfffc0040 acess: read-write reset: 0x01384a4b ? c6: color space conversion matrix coefficient c6 c6 element default step is 1/512, ranges from 0 to 0.2480468875 ? c7: color space conversion matrix coefficient c7 c7 element default step is 1/256, ranges from 0 to 0.49609375 ? c8: color space conversion matrix coefficient c8 c8 element default step is 1/128, ranges from 0 to 0.9921875 ? boff: color space conversion blue component offset 0: no offset 1: offset = 128 31 30 29 28 27 26 25 24 ???????boff 23 22 21 20 19 18 17 16 c8 15 14 13 12 11 10 9 8 c7 76543210 c6
787 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 42. analog-to-digital converter (adc) 42.1 description the adc is based on a successive approximatio n register (sar) 10-bit analog-to-digital con- verter (adc). it also integrates an 4-to-1 analog multiplexer, making possible the analog-to- digital conversions of 4 analog lines. the conversions extend from 0v to advref. the adc supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a common register for all channels, as well as in a channel-dedicated register. software trigger, external trigger on rising edge of the adtrg pin or internal triggers from timer counter out- put(s) are configurable. the adc also integrates a sleep mode and a conversion sequencer and connects with a pdc channel. these features reduce both power consumption and processor intervention. finally, the user can configure adc timings, such as startup time and sample & hold time. 42.2 block diagram figure 42-1. analog-to-digital conv erter block diagram adc interrupt adtrg vddana advref gnd trigger selection control logic successive approximation register analog-to-digital converter timer counter channels user interface aic peripheral bridge apb pdc asb dedicated analog inputs analog inputs multiplexed with i/o lines ad- ad- ad- pio ad- ad- ad- adc controller pmc mck adc cell
788 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 42.3 signal description 42.4 product dependencies 42.4.1 power management the adc is automatically clocked after the first conversion in normal mode. in sleep mode, the adc clock is automatically stopped after each conversion. as the logic is small and the adc cell can be put into sleep mode, the power management controller has no effect on the adc behavior. 42.4.2 interrupt sources the adc interrupt line is connected on one of th e internal sources of the advanced interrupt controller. using the adc interrupt requires the aic to be programmed first. 42.4.3 analog inputs the analog input pins can be multiplexed with pio lines. in this case, the assignment of the adc input is automatically done as soon as the corresponding channel is enabled by writing the reg- ister adc_cher. by default, after reset, the pio line is configured as input with its pull-up enabled and the adc input is connected to the gnd. 42.4.4 i/o lines the pin adtrg may be shared with other peripheral functions through the pio controller. in this case, the pio controller should be set acco rdingly to assign the pin adtrg to the adc function. 42.4.5 timer triggers timer counters may or may not be used as hardware triggers depending on user requirements. thus, some or all of the timer counters may be non-connected. 42.4.6 conversion performances for performance and electrical characteristics of the adc, see the dc characteristics section. table 42-1. adc pin description pin name description vddana analog power supply advref reference voltage ad0 - ad 3 analog input channels adtrg external trigger
789 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 42.5 functional description 42.5.1 analog-to-digital conversion the adc uses the adc clock to perform conversi ons. converting a single analog value to a 10- bit digital data requires sample and hold clock cycles as defined in the field shtim of the ?adc mode register? on page 796 and 10 adc clock cycles. the adc clock frequency is selected in the prescal field of the mode register (adc_mr). the adc clock range is between mck/2, if presc al is 0, and mck/128, if prescal is set to 63 (0x3f). prescal must be programmed in order to provide an adc clock frequency accord- ing to the parameters given in the product definition section. 42.5.2 conversion reference the conversion is performed on a full range be tween 0v and the reference voltage pin advref. analog inputs between these voltages convert to values based on a linear conversion. 42.5.3 conversion resolution the adc supports 8-bit or 10-bit resolutions. the 8- bit selection is performed by setting the bit lowres in the adc mode register (adc_mr). by default, after a reset, the resolution is the highest and the data field in the data registers is fully used. by setting the bit lowres, the adc switches in the lowest resolution and the conversion results can be read in the eight lowest significant bits of the data registers. the two hi ghest bits of the data field in the corresponding adc_cdr register and of the ldata field in the adc_lcdr register read 0. moreover, when a pdc channel is connected to the adc, 10-bit resolution sets the transfer request sizes to 16-bit. setting the bit lowres autom atically switches to 8-bit data transfers. in this case, the destination buffers are optimized.
790 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 42.5.4 conversion results when a conversion is completed, the resulting 10-bit digital value is stored in the channel data register (adc_cdr) of the current channel and in the adc last converted data register (adc_lcdr). the channel eoc bit in the status register (adc_sr) is set and the drdy is set. in the case of a connected pdc channel, drdy rising triggers a data transfer request. in any case, either eoc and drdy can trigger an interrupt. reading one of the adc_cdr registers clears the corresponding eoc bit. reading adc_lcdr clears the drdy bit and the eoc bit corresponding to the last converted channel. figure 42-2. eocx and drdy flag behavior conversion time read the adc_cdrx eocx drdy read the adc_lcdr chx (adc_chsr) (adc_sr) (adc_sr) write the adc_cr with start = 1 conversion time write the adc_cr with start = 1
791 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary if the adc_cdr is not read befo re further incoming data is converted, the corresponding over- run error (ovre) flag is set in the status register (adc_sr). in the same way, new data converted when drdy is high sets the bit govre (general overrun error) in adc_sr. the ovre and govre flags are automatically cleared when adc_sr is read. figure 42-3. govre and ovrex flag behavior warning: if the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion, its associated data and its corresponding eoc and ovre flags in adc_sr are unpredictable. eoc0 govre ch0 (adc_chsr) (adc_sr) (adc_sr) adtrg eoc1 ch1 (adc_chsr) (adc_sr) ovre0 (adc_sr) undefined data data a data b adc_lcdr undefined data data a adc_cdr0 undefined data data b adc_cdr1 data c data c conversion conversion read adc_sr drdy (adc_sr) read adc_cdr1 read adc_cdr0 conversion
792 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 42.5.5 conversion triggers conversions of the active analog channels are started with a software or a hardware trigger. the software trigger is provided by writing the control register (adc_ cr) with the bit start at 1. the hardware trigger can be one of the tioa outputs of the timer counter channels, or the external trigger input of the adc (adtrg). the hardware trigger is selected with the field trg- sel in the mode register (adc_mr). the selected hardware trigger is enabled with the bit trgen in the mode register (adc_mr). if a hardware trigger is selected, the start of a c onversion is detected at each rising edge of the selected signal. if one of the tioa outputs is selected, the corresponding timer counter channel must be programmed in waveform mode. only one start command is necessary to initiate a conversion sequence on all the channels. the adc hardware logic automatically performs the conversions on the active channels, then waits for a new request. the channel enable (adc_cher) and channel disable (adc_chdr) reg- isters enable the analog channels to be enabled or disabled independently. if the adc is used with a pdc, only the transfe rs of converted data from enabled channels are performed and the resulting data buffers should be interpreted accordingly. warning: enabling hardware triggers does not disable the software trigger functionality. thus, if a hardware trigger is selected, the start of a conversion can be initiated either by the hardware or the software trigger. 42.5.6 sleep mode and conversion sequencer the adc sleep mode maximizes power saving by automatically deactivating the adc when it is not being used for conversions. sleep mode is se lected by setting the bit sleep in the mode register adc_mr. the sleep mode is automatically managed by a conversion sequencer, which can automati- cally process the conversions of all channels at lowest power consumption. when a start conversion request occurs, the adc is automatically activated. as the analog cell requires a start-up time, the logic waits during this time and starts the conversion on the enabled channels. when all conversions are complete, the adc is deactivated until the next trigger. trig- gers occurring during the sequence are not taken into account. the conversion sequencer allows automatic pr ocessing with minimum processor intervention and optimized power consumption. conversion sequences can be performed periodically using a timer/counter output. the periodic acquisition of several samples can be processed automat- ically without any intervention of the processor thanks to the pdc. note: the reference voltage pins always remain connected in normal mode as in sleep mode.
793 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 42.5.7 adc timings each adc has its own minimal startup time that is programmed through the field startup in the mode register adc_mr. in the same way, a minimal sample and hold time is necessary for the adc to guarantee the best converted final value between two channels selection. this time has to be programmed through the bitfield shtim in the mode register adc_mr. warning: no input buffer amplifier to isolate the source is included in the adc. this must be taken into consideration to program a precise value in the shtim field. see the section, adc characteristics in the product datasheet.
794 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 42.6 analog-to-digital conv erter (adc) user interface table 42-2. register mapping offset register name access reset 0x00 control register adc_cr write-only ? 0x04 mode register adc_mr read-write 0x00000000 0x08 reserved ? ? ? 0x0c reserved ? ? ? 0x10 channel enable register adc_cher write-only ? 0x14 channel disable register adc_chdr write-only ? 0x18 channel status register adc_chsr read-only 0x00000000 0x1c status register adc_sr read-only 0x000c0000 0x20 last converted data register adc_lcdr read-only 0x00000000 0x24 interrupt enable register adc_ier write-only ? 0x28 interrupt disable register adc_idr write-only ? 0x2c interrupt mask register adc_imr read-only 0x00000000 0x30 channel data register 0 adc_cdr0 read-only 0x00000000 0x34 channel data register 1 adc_cdr1 read-only 0x00000000 ... ... ... ... ... 0x40 channel data register 3 adc_cdr3 read-only 0x00000000 0x44 - 0xfc reserved ? ? ?
795 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 42.6.1 adc control register register name: adc_cr address: 0xfffe0000 access type: write-only ? swrst: software reset 0 = no effect. 1 = resets the adc simulating a hardware reset. ? start: start conversion 0 = no effect. 1 = begins analog-to-digital conversion. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????startswrst
796 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 42.6.2 adc mode register register name: adc_mr address: 0xfffe0004 access type: read/write ? trgen: trigger enable ? trgsel: trigger selection ? lowres: resolution ? sleep: sleep mode 31 30 29 28 27 26 25 24 ???? shtim 23 22 21 20 19 18 17 16 ?startup 15 14 13 12 11 10 9 8 prescal 76543210 ? ? sleep lowres trgsel trgen trgen selected trgen 0 hardware triggers are disabled. starting a conversion is only possible by software. 1 hardware trigger selected by trgsel field is enabled. trgsel selected trgsel 0 0 0 tio output of the timer counter channel 0 0 0 1 tio output of the timer counter channel 1 0 1 0 tio output of the timer counter channel 2 011reserved 100reserved 101reserved 1 1 0 external trigger 111reserved lowres selected resolution 0 10-bit resolution 1 8-bit resolution sleep selected mode 0 normal mode 1 sleep mode
797 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary ? prescal: prescaler rate selection adcclock = mck / ( (prescal+1) * 2 ) ? startup: start up time startup time = (startup+1) * 8 / adcclock ? shtim: sample & hold time sample & hold time = shtim/adcclock
798 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 42.6.3 adc channel enable register register name: adc_cher address: 0xfffe0010 access type: write-only ? chx: channel x enable 0 = no effect. 1 = enables the corresponding channel. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????ch3ch2ch1ch0
799 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 42.6.4 adc channel disable register register name: adc_chdr address: 0xfffe0014 access type: write-only ? chx: channel x disable 0 = no effect. 1 = disables the corresponding channel. warning: if the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conver- sion, its associated data and its corresponding eoc and ovre flags in adc_sr are unpredictable. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????ch3ch2ch1ch0
800 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 42.6.5 adc channel status register register name: adc_chsr address: 0xfffe0018 access type: read-only ? chx: channel x status 0 = corresponding c hannel is disabled. 1 = corresponding channel is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????ch3ch2ch1ch0
801 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 42.6.6 adc status register register name: adc_sr address: 0xfffe001c access type: read-only ? eocx: end of conversion x 0 = corresponding analog channel is disabl ed, or the conversion is not finished. 1 = corresponding analog channel is enabled and conversion is complete. ? ovrex: overrun error x 0 = no overrun error on the corresponding channel since the last read of adc_sr. 1 = there has been an overrun error on the corres ponding channel since the last read of adc_sr. ? drdy: data ready 0 = no data has been converted since the last read of adc_lcdr. 1 = at least one data has been conv erted and is ava ilable in adc_lcdr. ? govre: general overrun error 0 = no general overrun error occurred since the last read of adc_sr. 1 = at least one general overrun error has occurred since the last read of adc_sr. ? endrx: end of rx buffer 0 = the receive counter register has not reach ed 0 since the last write in adc_rcr or adc_rncr. 1 = the receive counter register has reached 0 since the last write in adc_rcr or adc_rncr. ? rxbuff: rx buffer full 0 = adc_rcr or adc_rncr ha ve a value other than 0. 1 = both adc_rcr and adc_rncr have a value of 0. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????rxbuffendrxgovredrdy 15 14 13 12 11 10 9 8 ????ovre3ovre2ovre1ovre0 76543210 ????eoc3eoc2eoc1eoc0
802 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 42.6.7 adc last conv erted data register register name: adc_lcdr address: 0xfffe0020 access type: read-only ? ldata: last data converted the analog-to-digital conversion data is pl aced into this register at the end of a conversion and remains until a new conver- sion is completed. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ldata 76543210 ldata
803 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 42.6.8 adc interrupt enable register register name: adc_ier address: 0xfffe0024 access type: write-only ? eocx: end of conversion interrupt enable x ? ovrex: overrun error interrupt enable x ? drdy: data ready interrupt enable ? govre: general overrun error interrupt enable ? endrx: end of receive buffer interrupt enable ? rxbuff: receive buffer full interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????rxbuffendrxgovredrdy 15 14 13 12 11 10 9 8 ????ovre3ovre2ovre1ovre0 76543210 ????eoc3eoc2eoc1eoc0
804 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 42.6.9 adc interrupt disable register register name: adc_idr address: 0xfffe0028 access type: write-only ? eocx: end of conversion interrupt disable x ? ovrex: overrun error interrupt disable x ? drdy: data ready interrupt disable ? govre: general overrun error interrupt disable ? endrx: end of receive buffer interrupt disable ? rxbuff: receive buffer full interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????rxbuffendrxgovredrdy 15 14 13 12 11 10 9 8 ????ovre3ovre2ovre1ovre0 76543210 ????eoc3eoc2eoc1eoc0
805 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 42.6.10 adc interrupt mask register register name: adc_imr address: 0xfffe002c access type: read-only ? eocx: end of conversion interrupt mask x ? ovrex: overrun erro r interrupt mask x ? drdy: data ready interrupt mask ? govre: general overrun error interrupt mask ? endrx: end of receive buffer interrupt mask ? rxbuff: receive buffer full interrupt mask 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????rxbuffendrxgovredrdy 15 14 13 12 11 10 9 8 ????ovre3ovre2ovre1ovre0 76543210 ????eoc3eoc2eoc1eoc0
806 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 42.6.11 adc channel data register register name: adc_cdrx address: 0xfffe0030 access type: read-only ? data: converted data the analog-to-digital conversion data is pl aced into this register at the end of a conversion and remains until a new conver- sion is completed. the convert data re gister (cdr) is only loaded if the corr esponding analog channel is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? data 76543210 data
807 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 43. at91sam9xe128/256/512 el ectrical characteristics 43.1 absolute maximum ratings table 43-1. absolute maximum ratings* operating temperature (industrial).......... -40 ? c to +85 ? c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational se ctions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reli- ability. storage temperature ............................... -60c to +150c voltage on input pins with respect to ground .. -0.3v to vddio+0.3v(+4v max) maximum operating voltage (vddcore, vddpll and vddbu) ........... ............ .... 2.0v maximum operating voltage (vddiom and vddiop) ............................................. 4.0v total dc output current on all i/o lines ................ 350 ma
808 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 43.2 dc characteristics the following characteristics are applicable to the operating temperature range: t a = -40c to 85c, unless otherwise specified. table 43-2. dc characteristics symbol parameter conditions min typ max units v vddcore dc supply core 1.65 1.8 1.95 v v vddbu dc supply backup 1.65 1.8 1.95 v v vddpll dc supply pll 1.65 1.8 1.95 v v vddiom dc supply memory i/os 1.65/3.0 1.8/3.3 1.95/3.6 v v vddiop0 dc supply peripheral i/os 3.0 3.3 3.6 v v vddiop1 dc supply peripheral i/os 1.65 1.8/2.5/3.3 3.6 v v vddana dc supply analog 3.0 3.3 3.6 v v il input low-level voltage v vddio from 3.0v to 3.6v -0.3 0.8 v v vddio from 1.65v to 1.95v -0.3 0.3 x v vddio v v ih input high-level voltage v vddio from 3.0v to 3.6v 2 v vddio + 0.3 v v vddio from 1.65v to 1.95v 0.7 x v vddio v vddio + 0.3 v v ol output low-level voltage i o max, v vddio from 3.0v to 3.6v 0.4 v cmos (i o <0.3 ma) v vddio from 1.65v to 1.95v 0.1 v ttl (i o max) v vddio from 1.65v to 1.95v 0.4 v v oh output high-level voltage i o max, v vddio from 3.0v to 3.6v v vddio - 0.4 v cmos (i o <0.3 ma) v vddio from 1.65v to 1.95v v vddio - 0.1 v ttl (i o max) v vddio from 1.65v to 1.95v v vddio - 0.4 r pullup pull-up resistance pa0-pa31 pb0-pb31 pc0-pc3 nrtst and nrst 67 100 180 kohm pc4 - pc31 v vddiom in 1.8v range 240 1000 kohm pc4 - pc31 v vddiom in 3.3v range 120 350 kohm i o output current pa0-pa31 pb0-pb31 pc0-pc3 16 ma pc4-pc31 in 3.3v range 2 ma pc4-pc31 in 1.8v range 4 ma
809 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary i sc static current on v vddcore = 1.8v, mck = 0 hz, excluding por t a = 25c 500 a all inputs driven tms, tdi, tck, nrst = 1 t a = 85c 5000 on v vddbu = 1.8v, logic cells consumption, excluding por t a = 25c 2 a all inputs driven wkup = 0 t a = 85c 20 table 43-2. dc characteristics (continued) table 43-3. brownout detector characteristic symbol parameter conditions min typ max units v bot- threshold level 1.52 1.55 1.58 v v hyst hysteresis v hyst = v bot+ - v bot- 50 65 mv i dd current consumption bod on (gpnvmbit[1] is set) 12 18 a bod off (gpnvmbit[1] is cleared) 1 a t start startup time 100 200 s table 43-4. dc flash characteristics symbol parameter conditions min max units t pu power-up delay 30 s i sb standby current 20 a i cc active current read at maximum frequency (tacc = 60 ns) vddcore = 1.8v 13.0 ma write vddcore = 1.8v 7.0 ma
810 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 43.3 power consumption ? typical power consumption of plls , slow clock and main oscillator. ? power consumption of power supply in four different modes: active, idle, ultra low-power and backup. ? power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock. 43.3.1 power consumption versus modes the values in table 43-5 and table 43-6 on page 811 are estimated values of the power con- sumption with operating conditions as follows: ?v ddiom = v ddiop = 3.3v ?v ddpll = 1.8v ?v ddcore = v ddbu = 1.8v ?t a = 25 c ? there is no consumption on the i/os of the device figure 43-1. measures schematics these figures represent the power consumption estimated on the power supplies. vddcore vddbu amp2 amp1 table 43-5. power consumption for different modes (1) mode conditions consumption unit active arm core clock is 180 mhz. mck is 90 mhz. all peripheral clocks activated. onto amp2 130 ma idle idle state, waiting an interrupt. all peripheral clocks de-activated. onto amp2 17 ma ultra low power arm core clock is 500 hz. all peripheral clocks de-activated. onto amp2 600 a backup device only v ddbu powered onto amp1 5 a
811 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary table 43-6. power consumption by peripheral in active mode peripheral consumption unit pio controller 10 a/mhz usart 30 uhp 14 udp 20 adc 17 twi 21 spi 10 mci 30 ssc 20 timer counter channels 6 isi 8 emac 88
812 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 43.4 clock characteristics 43.4.1 processor clock characteristics 43.4.2 master clock characteristics 43.4.3 xin clock characteristics note: 1. these characteristics apply only when the main oscillator is in bypass mode (i.e. when moscen = 0 and oscbypass = 1) in the ckgr_mor register. see ?pmc clock generator main oscillator register? in the pmc section. table 43-7. processor clock waveform parameters symbol parameter conditions min max units 1/(t cppck ) processor clock frequency vddcore = 1.65v t = 85c 160 mhz 1/(t cppck ) processor clock frequency vddcore = 1.8v t = 85c 180 mhz table 43-8. master clock waveform parameters symbol parameter conditions min max units 1/(t cpmck ) master clock frequency vddcore = 1.65v t = 85c 80 mhz 1/(t cpmck ) master clock frequency vddcore = 1.8v t = 85c 90 mhz table 43-9. xin clock electrical characteristics symbol parameter conditions min max units 1/(t cpxin ) xin clock frequency 50 mhz t cpxin xin clock period 20 ns t chxin xin clock high half-period 0.4 x t cpxin 0.6 x t cpxin ns t clxin xin clock low half-period 0.4 x t cpxin 0.6 x t cpxin ns c in xin input capacitance (1) 25 pf r in xin pulldown resistor (1) 1000 k v in vin voltage (1) 1.8 v
813 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 43.4.4 i/os criteria used to define the maximum frequency of the i/os: ? output duty cycle (40%-60%) ? minimum output swing: 100 mv to vddio - 100 mv ? addition of rising and falling time inferior to 75% of the period notes: 1. 3.3v domain: v vddiop from 3.0v to 3.6v, maximum external capacitor = 40 pf 2. 2.5v domain: v vddiop from 2.3v to 2.7v, maximum external capacitor = 30 pf 3. 1.8v domain: v vddiop from 1.65v to 1.95v, maximum external capacitor = 20 pf table 43-10. i/o characteristics symbol parameter conditions min max units freqmax vddiop0 powered pins frequency 3.3v domain (1) 83.3 mhz freqmax vddiop1 powered pins frequency 3.3v domain (1) 83.3 mhz 2.5v domain (2) 71.4 mhz 1.8v domain (3) 50 mhz
814 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 43.5 crystal oscillat or characteristics the following characteristics are applicabl e to the operating temperature range: t a = -40c to 85c and worst case of power supply, unless otherwise specified. 43.5.1 32 khz oscillator characteristics notes: 1. r s is the equivalent series resistance. 2. c lext32 is determined by taking into account inte rnal, parasitic and package load capacitance. table 43-11. 32 khz oscillator characteristics symbol parameter conditions min typ max unit 1/(t cp32khz ) crystal oscillator frequency 32 768 khz c crystal32 load capacitance crystal @ 32.768 khz 6 12.5 pf c lext32 (2) external load capacitance c crystal32 = 6 pf 4 pf c crystal32 = 12.5 pf 17 pf duty cycle 40 60 % t st startup time r s = 50 k (1) c crystal32 = 6 pf 300 ms c crystal32 = 12.5 pf 900 ms r s = 100 k (1) c crystal32 = 6 pf 600 ms c crystal32 = 12.5 pf 1200 ms xin32 xout32 gndbu c lext32 c lext32 c crystal32 at91sam9xe table 43-12. crystal characteristics symbol parameter conditions min typ max unit esr equivalent series resistor rs crystal @ 32.768 khz 50 100 k c m motional capacitance crystal @ 32.768 khz 1 3 ff c s shunt capacitance crystal @ 32.768 khz 0.8 1.7 pf
815 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 43.5.2 rc oscillator characteristics 43.5.3 slow clock selection the startup counter delay for the slow clock oscillator depends on the oscsel signal. the 32,768 hz startup delay is 1200 ms whereas it is 200 s for th e internal rc oscillator. the pin oscsel must be tied either to gndbu or vddbu for correct operation of the device. table 43-13. rc oscillator characteristics symbol parameter conditions min typ max unit 1/(t cprcz ) crystal oscillator frequency 22 42 khz duty cycle 45 55 % t st startup time 75 s table 43-14. slow clock selection oscsel slow clock startup time 0 internal rc 200 s 1 external 32768 hz 1200 ms
816 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 43.5.4 main oscillator characteristics notes: 1. c s is the shunt capacitance. 2. r s = 100 to 200 ; c s = 2.0 to 2.5 pf; c m = 2 to 1.5 ff (typ, worst case) using 1 k serial resistor on xout. 3. r s = 50 to 100 ; c s = 2.0 to 2.5 pf; c m = 4 to 3 ff (typ, worst case). 4. r s = 25 to 50 ; c s = 2.5 to 3.0 pf; c m = 7 to 5 ff (typ, worst case). 5. r s = 20 to 50 ; c s = 3.2 to 4.0 pf; c m = 10 to 8 ff (typ, worst case). 6. additional user load capacitan ce should be subtracted from c lext . 7. c lext is determined by taking into account internal, parasitic and package load capacitance. table 43-15. main oscillator characteristics symbol parameter conditions min typ max unit 1/(t cpmain ) crystal oscillator frequency 3 16 20 mhz c crystal crystal load capacitance 12.5 17.5 pf c lext (7) external load capacitance c crystal = 12.5 pf (6) 3pf c crystal = 17.5 pf (6) 13 pf duty cycle 30 50 70 % t st startup time v ddpll = 1.65v to 1.95v c s = 3 pf (1) 1/(t cpmain ) = 3 mhz c s = 7 pf (1) 1/(t cpmain ) = 8 mhz c s = 7 pf (1) 1/(t cpmain ) = 16 mhz c s = 7 pf (1) 1/(t cpmain ) = 20 mhz 14.5 4 1.4 1 ms i ddst standby current consumption standby mode 1 a p on drive level @ 3 mhz 15 w @ 8 mhz 30 @ 16 mhz 50 @ 20 mhz 50 i dd on current dissipation @ 3 mhz (2) 150 250 a @ 8 mhz (3) 150 250 @ 16 mhz (4) 300 450 @ 20 mhz (5) 400 550 1k xin xout gndpll c lext c lext c crystal at91sam9xe
817 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 43.5.5 crystal characteristics 43.5.6 pll characteristics note: 1. startup time depends on pll rc filter. a calculation tool is provided by atmel. note: 1. the embedded filter is optimized for a 2 mhz input fr equency. divb must be selected to meet this requirement. table 43-16. crystal characteristics symbol parameter conditions min typ max unit esr equivalent series resistor rs fundamental @ 3 mhz 200 fundamental @ 8 mhz 100 fundamental @ 16 mhz 80 fundamental @ 20 mhz 50 c m motional capacitance 8ff c s shunt capacitance 7pf table 43-17. plla characteristics (1) symbol parameter conditions min typ max unit f out output frequency field out of ckgr_pll is 00 80 160 mhz field out of ckgr_pll is 10, t=85c 150 220 mhz f in input frequency 1 32 mhz i pll current consumption active mode @240 mhz 3.6 4.5 ma standby mode 1 a table 43-18. pllb characteristics symbol parameter conditions min typ max unit f out output frequency field out of ckgr_pll is 01 70 130 mhz f in input frequency 1 5 (1) mhz i pll current consumption active mode @130 mhz 1.2 ma standby mode 1 a
818 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 43.6 adc note: 1. in worst case, the track-and-hold acquisition time is given by: in case of very high input impedance, this value must be res pected in order to guarantee the correct converted value. an internal input current buffer supplies the current required for the low input impedance (1 ma max) . to achieve optimal performance of the adc, the analog power supply vddana and the advref input voltage must be decoupled with a 4.7f capacitor in parallel with a 100 nf capacitor . table 43-19. channel conversion time and adc clock parameter conditions min typ max units adc clock frequency 10-bit resolution mode 5 mhz startup time return from idle mode 15 s track and hold acquisition time adc clock = 5 mhz 1.2 (1) s conversion time adc clock = 5 mhz 2 s throughput rate adc clock = 5 mhz 312 ksps table 43-20. external voltage reference input parameter conditions min typ max units advref input voltage range 2.4 vddana v advref average current 220 a current consumption on vddana 300 620 a tth (s) 1,2 0,09 z in () kohm () + = table 43-21. analog inputs parameter min typ max units input voltage range 0 advref v input leakage current 1a input capacitance 12 14 pf table 43-22. transfer characteristics parameter min typ max units resolution 10 bit integral non-linearity 2 lsb differential non-linearity -0.9 +1 lsb offset error 2 lsb gain error 2 lsb
819 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 43.7 usb transceiver characteristics 43.7.1 electrical characteristics table 43-23. electrical parameters symbol parameter conditions min typ max unit input levels v il low level 0.8 v v ih high level 2.0 v v di differential input sensitivity |(d+) - (d-)| 0.2 v v cm differential input common mode range 0.8 2.5 v c in transceiver capacitance capacitance to ground on each line 9.18 pf i hi-z state data line leakage 0v < v in < 3.3v - 10 + 10 a r ext recommended external usb series resistor in series with each usb pin with 5% 27 output levels v ol low level output measured with r l of 1.425 k tied to 3.6v 0.0 0.3 v v oh high level output measured with r l of 14.25 k tied to gnd 2.8 3.6 v v crs output signal crossover voltage measure conditions described in figure 43-1 1.3 2.0 v pull-up and pull-down resistor r pui bus pull-up resistor on upstream port (idle bus) 0.900 1.575 kohm r pua bus pull-up resistor on upstream port (upstream port receiving) 1.425 3.090 kohm r pd bus pull-down resistor 14.25 24.8 kohm i vddio current consumption transceiver enabled in input mode ddp = 1 and ddm = 0 200 a i vddcore current consumption 150 a
820 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 43.8 core power supply por characteristics the at91sam9xe board design must comply with the power-up and power-down sequence guidelines below to guarantee reliable operati on of the device. any deviation from these sequences may lead to excessive current consumption during the power-up phase which, in worse case, can result in irre versible damage to the device. 43.9 power-up sequence vddcore and vddbu are controlled by internal por (power on reset) to guarantee that these power sources reach their target values prior to the release of por. vddiom, vddiop0 and vddiop1 must not be powered until vddcore has reached a level superior to v th+ . figure 43-2. v vddcore and v vddio constraints at startup 43.10 power-down sequence switch-off the vddiom, vddiop0 and vddiop1 power supply prior to or at the same time as vddcore. no power-up or power-down restrictions apply to vddbu, vddpll and vddana. table 43-24. power-on-reset characteristics symbol parameter conditions min typ max units v th+ threshold voltage rising minimum slope of +2.0v/200ms 1.35 1.50 1.59 v v th- threshold voltage falling 1.25 1.30 1.40 v t res reset time 100 200 350 s vdd (v) core su pply por o u tp u t vddiotyp vth+ t s lck vddcore vddio vddcoretyp voh vddio > v oh t re s <- - - ->
821 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 43.11 embedded flash characteristics the maximum operating frequency is given in table 43-26 but is limited by the embedded flash access time when the pro- cessor is fetching code out of it. table 43-25 gives the device maximum operating frequency depending on the field fws of the eefc_fmr register. this field defines the number of wait states required to access the embedded flash memory. table 43-25. embedded flash wait states fws maximum mck frequency (mhz) @ 25c maximum mck frequency (mhz) @ 85c 030 18 160 35 290 56 3 66 4 85 table 43-26. ac flash characteristics parameter conditions min max units program cycle time per page including auto-erase 4 ms per page without auto-erase 2 ms full chip erase 10 ms
822 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 43.12 smc timings 43.12.1 timing conditions smc timings are given in max corner. timings are given assuming a capacitance load on data, control and address pads: in the following tables t cpmck represents the mck period. 43.12.2 read timings table 43-27. capacitance load corner supply max 3.3v 50pf 1.8v 30 pf table 43-28. smc read signals - nrd controlled (read_mode = 1) symbol parameter min max units vddiom supply 1.8v 3.3v 1.8v 3.3v no hold settings (nrd hold = 0) smc 1 data setup before nrd high 12.6 12.61 ns smc 2 data hold after nrd high -7.2 -7.2 ns hold settings (nrd hold 0) smc 3 data setup before nrd high 9 9 ns smc 4 data hold after nrd high 0 0 ns hold or no hold settings (nrd hold 0, nrd hold =0) smc 5 nbs0/a0, nbs1, nbs2/a1, nbs3, a2 - a25 valid before nrd high (nrd setup + nrd pulse)* t cpmck -3.0 (nrd setup + nrd pulse)* t cpmck -3.1 ns smc 6 ncs low before nrd high (nrd setup + nrd pulse - ncs rd setup) * t cpmck -7.1 (nrd setup + nrd pulse - ncs rd setup) * t cpmck -7.2 ns smc 7 nrd pulse width nrd pulse * t cpmck -0.3 nrd pulse * t cpmck -0.3 ns
823 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 43.12.3 write timings table 43-29. smc read signals - ncs controlled (read_mode= 0) symbol parameter min max units vddiom supply 1.8v 3.3v 1.8v 3.3v no hold settings (ncs rd hold = 0) smc 8 data setup before ncs high 8 7.8 ns smc 9 data hold after ncs high 0 0 ns hold settings (ncs rd hold 0) smc 10 data setup before ncs high 6.6 6.4 ns smc 11 data hold after ncs high 0 0 ns hold or no hold settings (ncs rd hold 0, ncs rd hold = 0) smc 12 nbs0/a0, nbs1, nbs2/a1, nbs3, a2 - a25 valid before ncs high (ncs rd setup + ncs rd pulse)* t cpmck -3.3 (ncs rd setup + ncs rd pulse)* t cpmck -3.4 ns smc 13 nrd low before ncs high (ncs rd setup + ncs rd pulse - nrd setup)* t cpmck -0.9 (ncs rd setup + ncs rd pulse - nrd setup)* t cpmck -0.9 ns smc 14 ncs pulse width ncs rd pulse length * t cpmck -7.7 ncs rd pulse length * t cpmck -7.7 ns table 43-30. smc write signals - nwe controlled (write_mode = 1) symbol parameter min max units 1.8v supply 3.3v supply 1.8v supply 3.3v supply hold or no hold settings (nwe hold 0, nwe hold = 0) smc 15 data out valid before nwe high nwe pulse * t cpmck -1 nwe pulse * t cpmck -0.99 ns smc 16 nwe pulse width nwe pulse * t cpmck -1.7 nwe pulse * t cpmck -1.7 ns smc 17 nbs0/a0 nbs1, nbs2/a1, nbs3, a2 - a25 valid before nwe low nwe setup * t cpmck -2.8 nwe setup * t cpmck -2.7 ns smc 18 ncs low before nwe high (nwe setup - ncs rd setup + nwe pulse) * t cpmck -1.2 (nwe setup - ncs rd setup + nwe pulse) * t cpmck -1.2 ns
824 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary note: 1. hold length = total cycle duration - setup duration - pulse duration. ?hold length? is for ?ncs wr hold length? or ?nwe hold length?. hold settings (nwe hold 0) smc 19 nwe high to data out, nbs0/a0 nbs1, nbs2/a1, nbs3, a2 - a25 change nwe hold * t cpmck -2.8 nwe hold * t cpmck -5.6 ns smc 20 nwe high to ncs inactive (1) (nwe hold - ncs wr hold )* t cpmck -1.4 (nwe hold - ncs wr hold )* t cpmck -1.4 ns no hold settings (nwe hold = 0) smc 21 nwe high to data out, nbs0/a0 nbs1, nbs2/a1, nbs3, a2 - a25, ncs change (1) 3.3 3.2 ns table 43-30. smc write signals - nwe controlled (write_mode = 1) (continued) symbol parameter min max units 1.8v supply 3.3v supply 1.8v supply 3.3v supply table 43-31. smc write ncs controlled (write_mode=0) symbol parameter min max units 1.8v supply 3.3v supply 1.8v supply 3.3v supply smc 22 data out valid before ncs high ncs wr pulse * t cpmck -1.2 ncs wr pulse * t cpmck -5.8 ns smc 23 ncs pulse width ncs wr pulse * t cpmck -1.13 ncs wr pulse * t cpmck -1.12 ns smc 24 nbs0/a0 nbs1, nbs2/a1, nbs3, a2 - a25 valid before ncs low ncs wr setup * t cpmck -1.7 ncs wr setup * t cpmck -3.0 ns smc 25 nwe low before ncs high (ncs wr setup - nwe setup + ncs pulse)* t cpmck -1.13 (ncs wr setup - nwe setup + ncs pulse)* t cpmck -1.12 ns smc 26 ncs high to data out, nbs0/a0, nbs1, nbs2/a1, nbs3, a2 - a25, change ncs wr hold * t cpmck -3.3 ncs wr hold * t cpmck -3.4 ns smc 27 ncs high to nwe inactive (ncs wr hold - nwe hold )* t cpmck -0.91 (ncs wr hold - nwe hold )* t cpmck -0.88 ns
825 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 43-3. smc timings - ncs controlled read and write figure 43-4. smc timings - nrd controlled r ead and nwecontrolled write nrd nc s d0 - d15 nwe nc s controlled read with no hold nc s controlled read with hold nc s controlled write s mc22 s mc26 s mc10 s mc11 s mc12 s mc9 s mc 8 s mc14 s mc14 s mc2 3 s mc27 s mc26 a0/a1/nb s [ 3 :0]/a2-a25 s mc24 s mc25 s mc12 s mc1 3 s mc1 3 nrd nc s d0 - d 3 1 nwe a0/a1/nb s [ 3 :0]/a2-a25 nrd controlled read with no hold nwe controlled write with no hold nrd controlled read with hold nwe controlled write with hold s mc1 s mc2 s mc15 s mc21 s mc 3 s mc4 s mc15 s mc19 s mc20 s mc7 s mc21 s mc16 s mc7 s mc16 s mc19 s mc21 s mc17 s mc1 8 s mc5 s mc5 s mc6 s mc6 s mc17 s mc1 8
826 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 43.13 sdramc 43.13.1 timing conditions sdramc timings are given in max corner. timings are given assuming a capacitance load on data, control and address pads: 43.13.2 timing figures table 43-32. capacitance load on data, control and address pads corner supply max 3.3v 50pf 1.8v 30 pf table 43-33. capacitance load on sdck pad corner supply max 3.3v 10pf 1.8v 10pf table 43-34. sdram pc100 characteristics parameter min max units 3.3v supply 3.3v supply sdram controller clock frequency 100 mhz control/address/data in setup (1)(2) 2ns control/address/data in hold (1)(2) 1ns data out access time after sdck rising 6 ns data out change time after sdck rising 3 ns table 43-35. sdram pc133 characteristics parameter min max units 3.3v supply 3.3v supply sdram controller clock frequency 133 mhz control/address/data in setup (1)(2) 1.5 ns control/address/data in hold (1)(2) 0.8 ns data out access time after sdck rising 5.4 ns data out change time after sdck rising 3.0 ns
827 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary notes: 1. control is the set of following signals : sdcke, sdcs, ras, cas, sda10, bax, dqmx, and sdwe 2. address is the set of a0-a9, a11-a13 3. 133mhz with cl = 3, 100 mhz with c l= 2 table 43-36. mobile characteristics parameter min max units 1.8v supply 1.8v supply sdram controller clock frequency 133/100 (3) mhz control/address/data in setup (1)(2) 1.5 ns control/address/data in hold (1)(2) 1ns data out access time after sdck rising 6/8 (3) ns data out change time after sdck rising 2.5 ns
828 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 43.14 emac timings 43.14.1 mii mode table 43-37. emac signals relative to emdc symbol parameter min (ns) max (ns) emac 1 setup for emdio from emdc rising 29.4 emac 2 hold for emdio from emdc rising 0 emac 3 emdio toggling from emdc falling 0 4.3 table 43-38. emac mii specific signals symbol parameter min (ns) max (ns) emac 4 setup for ecol from etxck rising 0 emac 5 hold for ecol from etxck rising 1.2 emac 6 setup for ecrs from etxck rising 0.9 emac 7 hold for ecrs from etxck rising 0 emac 8 etxer toggling from etxck rising 15.6 emac 9 etxen toggling from etxck rising 14.8 emac 10 etx toggling from etxck rising 15.5 emac 11 setup for erx from erxck 0 emac 12 hold for erx from erxck 4.3 emac 13 setup for erxer from erxck 0 emac 14 hold for erxer from erxck 4.1 emac 15 setup for erxdv from erxck 0 emac 16 hold for erxdv from erxck 3.7
829 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 43-5. emac mii mode emdc emdio ecol ecrs etxck etxer etxen etx[3:0] erxck erx[3:0] erxer erxdv emac 3 emac 1 emac 2 emac 4 emac 5 emac 6 emac 7 emac 8 emac 9 emac 10 emac 11 emac 12 emac 13 emac 14 emac 15 emac 16
830 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 43.14.2 rmii mode figure 43-6. emac rmii mode table 43-39. emac rmii specific signals symbol parameter min (ns) max (ns) emac 21 etxen toggling from erefck rising 13.5 16 emac 22 etx toggling from erefck rising 12.3 15.5 emac 23 setup for erx from erefck 0 emac 24 hold for erx from erefck 1.3 emac 25 setup for erxer from erefck 0 emac 26 hold for erxer from erefck 1.2 emac 27 setup for ecrsdv from erefck 0.9 emac 28 hold for ecrsdv from erefck 0 erefck etxen etx[1:0] erx[1:0] erxer ecrsdv emac 21 emac 22 emac 23 emac 24 emac 25 emac 26 emac 27 emac 28
831 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 43.15 peripheral timings 43.15.1 spi figure 43-7. spi master mode with (cpol = ncpha = 0) or (cpol= ncpha= 1) figure 43-8. spi master mode with (cpol= 0 and ncpha=1) or (cpol= 1 and ncpha = 0) figure 43-9. spi slave mode with (cpol= 0 and ncpha = 1) or (cpol = 1 and ncpha = 0) spck miso mosi spi 2 spi 0 spi 1 spck miso mosi spi 5 spi 3 spi 4 spck miso mosi spi 6 spi 7 spi 8
832 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 43-10. spi slave mode with (cpol = ncpha = 0) or (cpol= ncpha = 1) note: c load is 8 pf for miso and 6 pf for spck and mosi. spck miso mosi spi 9 spi 10 spi 11 table 43-40. spi timings symbol parameter cond min max units master mode spi clk spck frequency 47 mhz spi 0 miso setup time before spck rises 5.8 + 0.5*t cpmck 15.4 + 0.5*t cpmc ns spi 1 miso hold time after spck rises 5.14 +0.5* t cpmck 14.5 + 0.5*t cpmc ns spi 2 spck rising to mosi -0.16 0.44 ns spi 3 miso setup time before spck falls 5.72 + 0.5*t cpmck 15.7+ 0.5*t cpmck ns spi 4 miso hold time after spck falls 4.7 + 0.5* t cpmck 14.8+0.5* t cpmck ns spi 5 spck falling to mosi 0.091 0.15 ns slave mode spi 6 spck falling to miso 5.33 18.55 ns spi 7 mosi setup time befo re spck rises 1.41 ns spi 8 mosi hold time after spck rises 0 ns spi 9 spck rising to miso 5.33 14.7 ns spi 10 mosi setup time before spck falls 1.41 ns spi 11 mosi hold time after spck falls 0 ns spi 12 npcs0 setup to spck rising 0 ns spi 13 npcs0 hold after spck falling 7.02 ns spi 14 npcs0 setup to spck falling 0 ns spi 15 npcs0 hold after spck rising 4.97 ns spi 16 npcs0 falling to miso valid 14.7 ns
833 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 43.15.2 isi figure 43-11. isi timing diagram vsync hsync pixclk data[7:0] 1 2 3 4 5 6 7 valid data valid data valid data table 43-41. isi timings with peripheral supply 3.3v symbol parameter min max units isi1 vsync to hsync 1.62 ns isi2 hsync to pixclk 1.86 ns isi3 data setup time -0.9 ns isi4 data hold time 3.96 ns isi5 pixclk high time -0.14 ns isi6 pixclk low time 0.29 ns isi7 pixclk frequency 74.8 mhz table 43-42. isi timings with peripheral supply 2.5v symbol parameter min max units isi1 vsync to hsync 1.56 ns isi2 hsync to pixclk 1.95 ns isi3 data setup time -1.02 ns isi4 data hold time 4.14 ns isi5 pixclk high time -0.1 ns isi6 pixclk low time 0.25 ns isi7 pixclk frequency 69.8 mhz
834 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 43.15.3 ssc 43.15.3.1 timing conditions timings are given assuming a capacitance load on table 43-44 . 43.15.3.2 timing extraction figure 43-12. ssc transmitter, tk and tf as output table 43-43. isi timings with peripheral supply 1.8v symbol parameter min max units isi1 vsync to hsync 1.67 ns isi2 hsync to pixclk -2.26 ns isi3 data setup time -1.33 ns isi4 data hold time 4.56 ns isi5 pixclk high time -0.01 ns isi6 pixclk low time 0.15 ns isi7 pixclk frequency 64.4 mhz table 43-44. capacitance load corner supply max 3.3v 30pf 1.8v 20pf tk (cki =1) tf/td ssc 0 tk (cki =0)
835 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 43-13. ssc transmitter, tk as input and tf as output figure 43-14. ssc transmitter, tk as output and tf as input figure 43-15. ssc transmitter, tk and tf as input tk (cki =1) tf/td ssc 1 tk (cki =0) tk (cki=1) tf ssc 2 ssc 3 tk (cki=0) td ssc 4 tk (cki=0) tf ssc 5 ssc 6 tk (cki=1) td ssc 7
836 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 43-16. ssc receiver rk and rf as input figure 43-17. ssc receiver, rk as input and rf as output figure 43-18. ssc receiver, rk and rf as output rk (cki=1) rf/rd ssc 8 ssc 9 rk (cki=0) rk (cki=0) rd ssc 8 ssc 9 rk (cki=1) rf ssc 10 rk (cki=0) rd ssc 11 ssc 12 rk (cki=1) rf ssc 13
837 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 43-19. ssc receiver, rk as ouput and rf as input figure 43-20. min and max access time of output signals rk (cki=1) rf/rd ssc 11 ssc 12 rk (cki=0) table 43-45. ssc timings symbol parameter cond min max units transmitter ssc 0 tk edge to tf/td (tk outp ut, tf output) 0.17 2.66 ns ssc 1 tk edge to tf/td (tk input, tf output) 6.4 ns ssc 2 tf setup time before tk edge (tk output) 6.1 - t cpmck ns ssc 3 tf hold time after tk edge (tk output) t cpmck - 5.77 ns ssc 4 tk edge to tf/td (tk output, tf input) 0.78 (+2*t cpmck )2.8(+2*t cpmck )ns ssc 5 tf setup time before tk edge (tk input) 0 ns ssc 6 tf hold time after tk edge (tk input) t cpmck ns ssc 7 tk edge to tf/td (tk inout, tf input) 7 (+3*t cpmck ) 18 (+3*t cpmck )ns receiver ssc 8 rf/rd setup time before rk edge (rk input) 0 ns ssc 9 rf/rd hold time after rk edge (rk input) t cpmck ns ssc 10 rk edge to rf (rk input) 4.7 24.2 ns ssc 11 rf/rd setup time before rk edge (rk output) 14.7 - t cpmck ns ssc 12 rf/rd hold time after rk edge (rk output) t cpmck - 5.3 ns ssc 13 rk edge to rf (rk output) 0 0.8 ns tk (cki =0) tf/td ssc 0min tk (cki =1) ssc 0max
838 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 43.15.4 mci the pdc interface block controls all data routing between the external data bus, internal mmc/sd module data bus, and internal system fifo access through a dedicated state machine that monitors the status of fifo content (emp ty or full), fifo address, and byte/block counters for the mmc/sd module (inner system) and the application (user programming). these timings are given for a 25 pf load, corresponding to 1 mmc/sd card. figure 43-21. mci timing diagram clk cmd_dat input mci1 cmd_dat output mci2 mci3 mci4 mci5 shaded areas are not valid table 43-46. mci timings symbol parameter cload min max units mci 1 clk frequency at data transfer mode c = 25 pf 25 mhz c = 100 pf 20 mhz c = 250 pf 20 mhz clk frequency at identification mode 400 khz clk low time c = 100 pf 10 ns clk high time c = 100 pf 10 ns clk rise time c = 100 pf 10 ns clk fall time c = 100 pf 10 ns clk low time c = 250 pf 50 ns clk high time c = 250 pf 50 ns clk rise time c = 250 pf 50 ns clk fall time c = 250 pf 50 ns mci 2 input hold time 3 ns mci 3 input setup time 3 ns mci 4 output change after clk rising 5 ns mci 5 output valid before clk rising 5 ns
839 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 43.15.5 udp figure 43-22. usb data signal rise and fall times 10% 10% 90% v crs t r t f differential data lines rise time fall time fosc = 6 mhz/750 khz r ext =27 ohms c load buffer (b) (a) table 43-47. in full speed symbol parameter conditions min typ max unit t fr transition rise time c load = 50 pf 4 20 ns t fe transition fall time c load = 50 pf 4 20 ns t frfm rise/fall time matching 90 111.11 %
840 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 44. at91sam9xe128/256/512 me chanical characteristics 44.1 package drawings the at91sam9xe package drawings are shown on the pages that follow.
841 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 44-1. 217-ball lfbga package drawing table 44-1. soldering information (substrate level) ball land 0.43 mm +/- 0.05 soldering mask opening 0.30 mm +/- 0.05 table 44-2. device and 217-ball lfbg a package maximum weight 450 mg table 44-3. 217-ball lfbga package characteristics moisture sensitivity level 3 table 44-4. package reference jedec drawing reference mo-205 jesd97 classification e1
842 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary figure 44-2. 208-lead pqfp package drawing table 44-5. device and 208-lead pqfp package maximum weight 5.5 g table 44-6. 208-lead pqfp package characteristics moisture sensitivity level 3 table 44-7. package reference jedec drawing reference ms-022 jesd97 classification e3
843 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 44.2 soldering profile table 44-8 gives the recommended soldering profile from j-std-20. note: it is recommended to apply a soldering temperature higher than 250c a maximum of three reflow passes is allowed per component. table 44-8. soldering profile profile feature green package average ramp-up rate (217c to peak) 3 ? c/sec. max. preheat temperature 175c 25c 180 sec. max. temperature maintained above 217c 60 sec. to 150 sec. time within 5 ? c of actual peak temperature 20 sec. to 40 sec. peak temperature range 260 +0 ? c ramp-down rate 6 ? c/sec. max. time 25 ? c to peak temperature 8 min. max.
844 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 45. at91sam9xe128/256/512 ordering information table 45-1. at91sam9xe128/256/512 ordering information ordering code package package type temperature operating range at91sam9xe128-qu pqfp208 green industrial -40c to 85c at91sam9xe128-cu bga217 green at91sam9xe256-qu pqfp208 green industrial -40c to 85c at91sam9xe256-cu bga217 green at91sam9xe512-qu pqfp208 green industrial -40c to 85c at91sam9xe512-cu bga217 green
845 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 46. at91sam9xe128/256/512 errata 46.1 marking all devices are marked with the atmel logo and the ordering code. additional marking may be in one of the following formats: where ??yy?: manufactory year ? ?ww?: manufactory week ? ?v?: revision ? ?xxxxxxxxx?: lot number yyww v xxxxxxxxx arm
846 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 46.2 at91sam9xe128/256/512 e rrata - revision a parts refer to section 46.1 ?marking? on page 845 . 46.2.1 analog-to-digital converter (adc) 46.2.1.1 adc: sleep mode if sleep mode is activa ted while there is no activity (no co nversion is being performed), it will take effect only after a conversion occurs. problem fix/workaround to activate sleep mode as soon as possible, it is recommended to write successively, adc mode register (sleep) then adc control register (start bit field), in order to start an analog- to-digital conversion and then put adc into sleep mode at the end of this conversion. 46.2.2 multimedia card interface (mci) 46.2.2.1 mci: busy signal of r1b responses is not taken in account the busy status of the card during the response (r1b) is ignored for the commands cmd7, cmd28, cmd29, cmd38, cmd42, cmd56. additionally, for commands cmd42 and cmd56 a conflict can occur on data line0 if the mci sends data to the ca rd while the card is still busy. the behavior is correct for cmd12 command (stop_transfer). problem fix/workaround none 46.2.2.2 mci: sdio interrupt does not work with slots other than a if there is 1-bit data bus width on slots other than slot a, the sdio interrupt can not be captured. the sample is made on the wrong data line. problem fix/workaround none 46.2.2.3 mci: data timeout error flag as the data timeout error flag checking the naac timing cannot rise, the mci can be stalled wait- ing indefinitely the data start bit. problem fix/workaround a stop command must be sent with a software timeout. 46.2.2.4 mci: data write operation and number of bytes the data write operation with a number of bytes less than 12 is impossible. problem fix/workaround the pdc counters must always be equal to 12 bytes for data transfers lower than 12 bytes. the blklen or bcnt field are used to specify the real count number. 46.2.2.5 mci: flag reset is not correct in half duplex mode in half duplex mode, the reset of the fl ags endrx, rxbuff, endtx and txbufe can be incorrect. these flags are reset correctly after a pdc channel enable. problem fix/workaround enable the interrupts related to endrx, endtx, rxbuff and t xbufe only after enabling the pdc channel by writing pdc_txten or pdc_rxten.
847 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 46.2.3 reset controller (rstc) 46.2.3.1 rstc: reset type status is wrong at power-up rsttyp staus in the reset controler status register is wrong at power-up. it should be ?0? (general reset) but it is ?5? (brownout reset). the value is the same if brownout and brownout reset are enabled or not. the bodsts bit remains correct. problem fix/workaround none. 46.2.3.2 rstc: reset during sdram accesses when a user reset occurs during sdram read access, the sdram clock is turned off while data are ready to be read on the data bus. the sdram maintains the data until the clock restarts. if the user reset is programmed to assert a general reset, the data maintained by the sdram leads to a data bus conflict and adversely affects the boot memories connected on the ebi: ? nand flash boot functionality, if the system boots out of internal rom. ? nor flash boot, if the system boots on an external memory connected on the ebi cs0. problem fix/workaround 1. avoid user reset to generate a system reset. 2. trap the user reset with an interrupt. in the interrupt routine, power down sdram properly and perform peripheral and processor reset with software in assembler. example with libv3. ? the main code: //user reset interrupt setting // configure aic controller to handle ssc interrupts at91f_aic_configureit ( at91c_base_aic, // aic base address at91c_id_sys, // system peripheral id at91c_aic_prior_highest, // max priority at91c_aic_srctype_int_edge_triggered, // level sensitive sysc_handler ); // enable sysc interrupt in aic at91f_aic_enableit(at91c_base_aic, at91c_id_sys); *at91c_rstc_rmr = (0xa5<<24) | (0x4<<8) | at91c_rstc_urstien; ? the c sys handler: extern void soft_user_reset(void); void sysc_handler(void){ //check if interrupt comes from rstc if( (*at91c_rstc_rsr & at91c_rstc_ursts ) == at91c_rstc_ursts){
848 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary soft_user_reset(); //never reached while(1); } } ? the assembler routine: area test, code includeat91sam9xxx.inc exportsoft_user_reset soft_user_reset ;disable irqs mrs r0, cpsr orr r0, r0, #0x80 msr cpsr_c, r0 ;change refresh rate to block all data accesses ldr r0, =at91c_sdramc_tr ldr r1, =1 str r1, [r0] ;prepare power down command ldr r0, =at91c_sdramc_lpr ldr r1, =2 ;prepare proc_reset and periph_reset ldr r2, =at91c_rstc_rcr ldr r3, =0xa5000005 ;perform power down command str r1, [r0] ;perform proc_reset and periph_reset (in the arm pipeline) str r3, [r2] end 46.2.4 static memory controller (smc) 46.2.4.1 smc: chip select parameters modification the user must not change the configuration parameters of an smc chip select (setup, pulse, cycle, mode) if accesses are performed on this cs during the modification. for example, the modification of the chip select 0 (cs0) parameters, while fetching the code from a memory connected on this cs0, may lead to unpredictable behavior. problem fix/workaround
849 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary the code used to modify the parameters of an smc chip select can be executed from the inter- nal ram or from a memory connected to another chip select 46.2.5 serial peripheral interface (spi) 46.2.5.1 spi: baudrate set to 1 when baudrate is set to 1 (i.e. when serial cl ock frequency equals the s ystem clock frequency), and when the fields bits (number of bits to be transmitted) equals an odd value (in this case 9,11,13 or 15), an additional pulse is generated on ou tput spck. no error occurs if bits field equals 8,10,12,14 or 16 and baudrate = 1. problem fix/workaround none. 46.2.5.2 spi: bad serial clock generation on second chip_select when scbr = 1, cpol = 1 and ncpha = 0 if the spi is used in the following configuration: ? master mode ? cpol = 1 and ncpha = 0 ? multiple chip selects used with one transfer with baud rate (scbr) equal to 1 (i.e., when serial clock frequency equals the system clock frequency) and the other transfers set with scbr not equal to 1 ? transmit with the slowest chip select and then with the fastest one, then an additional pul se will be genera ted on output spck duri ng the second transfer. problem fix/workaround do not use a multiple chip select configurati on where at least one scrx register is configured with scbr = 1 and the others differ from 1 if cpha = 0 and cpol = 1. if all chip selects are configured with baudrate = 1, the issue does not appear. 46.2.5.3 spi: software reset must be written twice if a sofware reset (swrst in the spi control register) is performed, the spi may not work prop- erly (the clock is enabled before the chip select.) problem fix/workaround the spi control register field swrst (software reset) needs to be written twice to be correctly set. 46.2.6 serial synchronous controller (ssc) 46.2.6.1 ssc: clock is transmitted before the ssc is enabled ssc configuration: ? perform a sw reset ? program the receive and the transmit frame synchro ? program the transmit and the receive cock as continuous (cko = continuous receive and transmit clock) => the clock is transmitted. problem fix/workaround configure pio lines for ssc usage after ssc enabling.
850 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 46.2.6.2 ssc: transmitter limitations in slave mode if tk is programmed as output and tf is programmed as input, it is impossible to emit data when start of edge (rising or falling) of synchro with a st art delay is equal to zero. problem fix/workaround none. 46.2.6.3 ssc: periodic transmission limitations in master mode if last significant bit is sent first (msbf = 0), the first tag during the frame synchro is not sent. problem fix/workaround none. 46.2.6.4 ssc: last rk clock cycle when rk outputs a clock during data transfer when the ssc receiver is used with the following conditions: ? the internal clock divider is used (cks = 0 and div different from 0) ? rk pin set as output and provides the clock during data transfer (cko = 2) ? data sampled on rk falling edge (cki = 0) at the end of the data, the rk pin is set in high impedance which might be seen as an unex- pected clock cycle. problem fix/workaround enable the pull-up on rk pin. 46.2.6.5 ssc: first rk clock cycle when rk outputs a clock during data transfer when the ssc receiver is used with the following conditions: ? rx clock is divided clock (cks =0 and div different from 0) ? rk pin set as output and provides the clock during data transfer (cko = 2) ? data sampled on rk falling edge (cki =0) the first clock cycle time generated by the rk pin is equal to mck /(2 x (value +1)). problem fix/workaround none. 46.2.7 usb host port (uhp) 46.2.7.1 uhp: non-iso in transfers conditions: consider the following sequence: 1. the host controller issues an in token. 2. the device provides the in data in a short packet. 3. the host controller writes the received data to the system memory. 4. the host controller is now supposed to carry out two write transactions (td status write and td retirement write) to the system memory in order to complete the status update. 5. the host controller raises the request for the first write transaction. by the time the transaction is completed, a frame boundary is crossed.
851 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 6. after completing the first write transaction, the host controller skips the second write transaction. consequence: when this defect manifests itself, the host controller re-attempts the same in token. problem fix/workaround this problem can be avoided if the system guarantees that the st atus update c an be completed within the same frame. 46.2.7.2 uhp: iso out transfers conditions: consider the following sequence: 1. the host controller sends an iso out token after fetching 16 bytes of data from the system memory. 2. when the host controller is sending the iso out data, because of system latencies, remaining bytes of the packet are not available. this results in a buffer underrun condition. 3. while there is an underrun condition, if the host controller is in the process of bit-stuff- ing, it causes the host controller to hang. consequence: after the failure condition, the host controller stops sending the sof. this causes the connected device to go into suspend state. problem fix/workaround this problem can be avoided if the system can guarantee that no buffer underrun occurs during the transfer. 46.2.7.3 uhp: remote wakeup event conditions: when a remote wakeup event occurs on a downs tream port, the ohci host controller begins sending resume signaling to the device. the host controller is supposed to send this resume signaling for 20 ms. however, if the driver sets the hccontrol. hc fs into usboperational state during the resume event, then the host controller terminates sending the resume signal with an eop to the device. consequence: if the device does not recognize the resume (<20 ms) event, then the device will remain in suspend state. problem fix/workaround host stack can do a port resu me after it sets the hccontro l. hcfs to usboperational.
852 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary
853 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary revision history in the tables that follow the most recent version of the document appears first. doc. rev 6254b comments change request ref. overview: ?features? , ?ethernet mac 10/100 base-t? , 128-byte fifos (typo corrected). debug unit (dbgu), added ?mode for general purpose two-sire uart serial communication? section 10.4.9 ?ethernet 10/100 mac? , 128-byte fifos (typo corrected). section 9.13 ?chip identification? , sam9xe512 chip id is 0x329aa3a0. removed fomer section 5.2 ?power consumption?. table 3-1, ?signal description list? , comment column updated in certain instances and ?pio controller - pioa - piob - pioc? , has a foot note added to its comments column. shdwn is active low. section 6. ?i/o line considerations? , unneeded paragraphs removed. ?features? , ?additional embedded memories? fast read time: 45 ns. ?features? ?four universal synchronous/asynchrono us receiver transmitters (usart)? , added manchester encoding/decding, section 1. ?at91sam9xe128/256/512 description? , 2nd and 3rd paragraphs improved. 5800 5846 5800 rfo rfo 5930 rfo section 6.3 ?shutdown logic pins? , updated with external pull-up requirement. rfo debug and test section 12.5 ?jtag port pins? , added to debug and test. rfo boot program: section 13.4.4 ?in-applicati on programming (iap) feature? , added to datasheet. 6190 aic: section 29.6.3 ?interrupt sources? , interupt source 1, or-wiring description updated. section 29.7.5 ?protect mode? , enabling debug control protect m ode in aic_dcr register updated. qualified/internal on atp 5191 5193 dbgu: section 30.1 ?description? , added to second paragraph; ?..two-pin uart can be used as stand-alone...? 5846 ecc: section 25.4.3 ?ecc status register 1? and section 25.4.4 ?ecc status register 2? , eccerrx renamed as mulerrx on bitfields, 2, 18, 22, 26, 30. section 25.4.1 ?ecc control register? , added new bitfield: srst 5542 5543 eefc: section 20.4.2 ?eefc flash command register? , updated farg bit field description 5302 isi: section 41.4.7 ?isi preview register? , updated prev_vsize and prev_hsize with rgb only comments pmc: section 28.7 ?programming sequence? , steps 5 and 6: ?by default pres parameter is set to 0.....? 5596 rstc: section 15.3.4.5 ?software reset? perrst must be used with procrst, except for debug purposes. 5436
854 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary smc: section 23.8.5 ?coding timing parameters? , ?effective value? column under ?permitted range? updated in table 23-4 on page 211 . section 23.9.3.1 ?user procedure? , instructions regarding configuratio n parameters of smc chip select added. 5604 5621 twi: section 33.5.1 ?i/o lines? , twd and twck open drain status and condition updated. programmer interdiction added to twd and twck. section 33.10.6 ?twi status register? , gacc bit description updated. 5343 rfo 5773 usart: manchester encoding/decoding is available in this implementation of the usart (not visible in 6254a). 5930 electrical characteristics: table 43-11, ?32 khz osci llator characteristics? table 43-15, ?main oscillator characteristics? , updated typ values for c lext , updated startup time parameter, v ddpll = 1.65v to 1.95v. section 43.6 ?adc? , section added to datasheet table 43-2, ?dc characteristics? , v vddiom condition column cleared. section 43.8 ?core power supply por characteristics? , added to datasheet. table 43-25, ?embedded flash wait states? fws rows 5, 6 removed, read operations column removed, values assigned to max mck frequency columns table 43-17, ?plla characteristics(1)? fout min &m ax updated table 43-9, ?xin clock electrical characteristics? , line added for v in . section 43.4 ?clock characteristics? , section 43.12 ?smc timings? , section 43.13 ?sdramc? , section 43.14 ?emac timings? , section 43.15 ?peripheral timings? , added to datasheet. table 43-21, ?analog inputs? , adc input capacitance is 12 pf typ, 14 pf max. 5335 5345 5789 5562 5800 5298 & 5923/6189 5924 6049 6167 rfo 6242 mechanical ch aracteristics: table 44-1, ?soldering information (substrate level),? on page 841 , updated title. 5288 errata: section 46.2 ?at91sam9xe128/256/512 errata - revision a parts? former errata - revision b parts replaced and become errata - revision a parts. former errata - revision a parts removed from errata 5922 section 46.2.2.2 ?mci: sdio interrupt do es not work with slots other than a? , syntax updated. section 46.2.6.1 ?ssc: clock is transm itted before the ssc is enabled? , added to ssc errata. section 46.2.5.2 ?spi: bad serial clock generation on second chip_select when scbr = 1, cpol = 1 and ncpha = 0? , added to spi errata. section 46.2.5.3 ?spi: software reset must be written twice? , added to spi errata. section 46.2.3 ?reset controller (rstc)? , added to errata. section 46.2.3.2 ?rstc: reset during sdram accesses? , added to errata. section 46.2.4 ?static memory controller (smc)? added to errata. 6169 5439 rfo 5958 5925 6085 5642 doc. rev 6254b comments (continued) change request ref.
855 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary doc. rev 6254a comments change request ref. first issue. unqualified version on atp: 02-mar-07/qualified on 01-feb-08 product specific parts updated in this version before qualification. section 46.2 ?at91sam9xe128/256/512 errata - revision a parts? added to errata section section 46.2.6.3 ?sdramc: je dec standard compatability? , added. section 46.2.2.1 ?matrix: fixed_priority functionality? , added. section 21.5.4 ?bus matrix ma ster remap control register? , removed rcb5, rcb4, rcb3, rcb2 section 22.7.3 ?8-bit nandflash? , removed reference to nandoe and nandwe multiplexing from section 22.7.3.1 ?sof tware configuration? section 11. ?arm926ej-s processor? , removed tightly-coupled memory interface chapter. section 46.2.14.5 ?usart: txd signal is floati ng in modem and hardware handshaking modes? and section 46.2.14.6 ?usart: dcd is active high instead of low.? added to errata. section 5.1 ?power supplies? , added caution on ?con straints at startup?. section 43.2 ?dc characteristics? updated vol and voh in table 43-2 on page 808 . temperature junction info removed. prod specs 4220 4232 4283 4374 4403 4722 5293 5290 4731 section 7.2.1 ?matrix masters? , section 7.2.2 ?matrix slaves? , section 7.2.3 ?masters to slaves access? , master and slave identification lists updated. 5284 ebi, emac and peripheral timings: tbd section 6.5 ?pio controllers? , first line updated w/schmitt trigger detail. section 6.8 ?slow clock selection? table moved to electrical characteristics, table 43-14 on page 815 table 7-3, ?at91sam9xe128/256/512 masters to slaves access,? on page 20 , master/slave relations updated section 8.1.6.1 ?gpnvmbit[3] = 0, boot on embedded rom? , some lines deleted. section 8.2.4 ?error corrected code controller? replaced to correspond to actual ecc installation. figure 9-3 on page 34 , /3 divider removed. figure 12-1 ?debug and test block diagram? and figure 12-1 ?debug and test pin list? , ntrst pin added review section 2-1 ?at91sam9xe128/256/512 block diagram? , icache is 16 kbytes section 6.8 ?slow clock selection? , oscel tied to gndbu or vddbu section 8.1.6 ?boot strategies? typo on gpnvmbit[3] fixed. section 9-1 ?at91sam9xe128/256/512 system controller block diagram? , ?security bit? and ?gpnvm? signals redefined from embedded flash. table 13-3, ?large crystal table (mhz) oscsel = 1,? on page 78 , 1.367667 frequency added. section 13.3 ?device initialization? in the sub list, step c. (oscel = 1 and bypass mode ) added. section 40.5 ?typical connection? , figure and text updated to correspond to on chip conditions. section 40.2 ?block diagram? , removed warning on pull-down connection. 4265
856 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary
i 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary table of contents features ................ ................ .............. ............... .............. .............. ............ 1 1 at91sam9xe128/256/512 description ........... .............. .............. ............ 3 2 at91sam9xe128/256/512 block di agram ............ ........... ............ .......... 4 3 signal description .............. .............. ............... .............. .............. ............ 6 4 package and pinout ................. ................ ................. ................ ............. 11 4.1 208-pin pqfp package outline .........................................................................11 4.2 208-pin pqfp package pinout ..........................................................................12 4.3 217-ball lfbga package outline ......................................................................13 4.4 217-ball lfbga package pinout .......................................................................14 5 power considerations ........ .............. ............... .............. .............. .......... 15 5.1 power supplies ..................................................................................................15 6 i/o line considerations ...... .............. ............... .............. .............. .......... 16 6.1 erase pin .........................................................................................................16 6.2 i/o line drive levels ..........................................................................................16 6.3 shutdown logic pins ..........................................................................................16 7 processor and architecture .... ................ ................. ................ ............. 16 7.1 arm926ej-s processor ....................................................................................16 7.2 bus matrix ..........................................................................................................17 7.3 peripheral dma controller .................................................................................18 7.4 debug and test features ..................................................................................19 8 memories ............... .............. .............. ............... .............. .............. .......... 21 8.1 embedded memories .........................................................................................22 8.2 external memories .............................................................................................27 9 system controller ............. ................ ............... .............. .............. .......... 29 9.1 system controller block diagram ......................................................................30 9.2 reset controller .................................................................................................31 9.3 brownout detector and power-on reset ............................................................31 9.4 shutdown controller ...........................................................................................31 9.5 clock generator .................................................................................................32 9.6 power management controller ..........................................................................32 9.7 periodic interval timer .......................................................................................32
ii 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 9.8 watchdog timer .................................................................................................32 9.9 real-time timer ..................................................................................................32 9.10 general-purpose back-up registers ..................................................................33 9.11 advanced interrupt controller ............................................................................33 9.12 debug unit .........................................................................................................33 9.13 chip identification ...............................................................................................34 10 peripherals ............ .............. .............. ............... .............. .............. .......... 35 10.1 user interface .....................................................................................................35 10.2 peripheral identifier ............................................................................................35 10.3 peripheral signals multiplexing on i/o lines ......................................................36 10.4 embedded peripherals .......................................................................................40 11 arm926ej-s processor .......... ................ ................. ................ ............. 45 11.1 overview ............................................................................................................45 11.2 block diagram ....................................................................................................46 11.3 arm9ej-s processor ........................................................................................47 11.4 cp15 coprocessor .............................................................................................55 11.5 memory management unit (mmu) .....................................................................58 11.6 caches and write buffer ....................................................................................60 11.7 bus interface unit ...............................................................................................62 12 at91sam9xe debug and test .... ................ ................. .............. .......... 63 12.1 overview ............................................................................................................63 12.2 block diagram ....................................................................................................64 12.3 application examples .........................................................................................65 12.4 debug and test pin description ........................................................................66 12.5 jtag port pins ..................................................................................................67 12.6 functional description ........................................................................................67 13 at91sam9xe boot program .. ................ ................. ................ ............. 77 13.1 overview ............................................................................................................77 13.2 flow diagram .....................................................................................................77 13.3 device initialization ............................................................................................78 13.4 sam-ba boot .....................................................................................................80 13.5 hardware and software constraints ..................................................................85 14 fast flash programming inte rface (ffpi) ...... .............. .............. .......... 87 14.1 description .........................................................................................................87
iii 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 14.2 parallel fast flash programming .......................................................................87 14.3 serial fast flash programming ..........................................................................96 15 reset controller (rstc) .... ............. .............. .............. .............. ........... 103 15.1 description .......................................................................................................103 15.2 block diagram ..................................................................................................103 15.3 functional description ......................................................................................103 15.4 reset controller (rstc) user interface ..........................................................113 16 real-time timer (rtt) ....... .............. .............. .............. .............. ........... 117 16.1 description .......................................................................................................117 16.2 block diagram ..................................................................................................117 16.3 functional description ......................................................................................117 16.4 real-time timer (rtt) user interface ..............................................................119 17 periodic interval time r (pit) ............... .............. .............. ............ ........ 123 17.1 description .......................................................................................................123 17.2 block diagram ..................................................................................................123 17.3 functional description ......................................................................................124 17.4 periodic interval timer (pit) user interface .....................................................126 18 watch dog timer (wdt) ..... .............. ............... .............. .............. ........ 131 18.1 description .......................................................................................................131 18.2 block diagram ..................................................................................................131 18.3 functional description ......................................................................................132 18.4 watchdog timer (wdt) user interface ............................................................134 19 shutdown controller (shdwn ) .............. ................. ................ ........... 139 19.1 description .......................................................................................................139 19.2 block diagram ..................................................................................................139 19.3 i/o lines description ........................................................................................139 19.4 product dependencies .....................................................................................139 19.5 functional description ......................................................................................139 19.6 shutdown controller (shdwn) user interface ................................................141 20 enhanced embedded fl ash controller (eefc) ...... ................ ........... 145 20.1 description .....................................................................................................145 20.2 product dependencies .....................................................................................145 20.3 functional description ......................................................................................145 20.4 enhanced embedded flash controller (eefc) user interface ........................156
iv 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 21 at91sam9xe bus matrix ...... ................ ................. ................ ............. 161 21.1 description .......................................................................................................161 21.2 memory mapping .............................................................................................161 21.3 special bus granting techniques ....................................................................161 21.4 arbitration .........................................................................................................162 21.5 bus matrix (matrix) user interface ................................................................165 21.6 chip configuration user interface ....................................................................169 22 at91sam9xe128/256/512 exter nal bus interface ...... .............. ........ 171 22.1 description .......................................................................................................171 22.2 block diagram ..................................................................................................172 22.3 i/o lines description ........................................................................................173 22.4 application example .........................................................................................175 22.5 product dependencies .....................................................................................178 22.6 functional description ......................................................................................178 22.7 implementation examples ................................................................................187 23 static memory controller (smc) ........... ................. ................ ............. 197 23.1 description .......................................................................................................197 23.2 i/o lines description ........................................................................................197 23.3 multiplexed signals ..........................................................................................197 23.4 application example .........................................................................................198 23.5 product dependencies .....................................................................................198 23.6 external memory mapping ...............................................................................199 23.7 connection to external devices .......................................................................199 23.8 standard read and write protocols .................................................................204 23.9 automatic wait states ......................................................................................213 23.10 data float wait states .....................................................................................217 23.11 external wait ....................................................................................................222 23.12 slow clock mode .............................................................................................228 23.13 asynchronous page mode ...............................................................................231 23.14 static memory controller (smc) user interface ...............................................234 24 sdram controller (sdramc) ................ ................. ................ ........... 241 24.1 description .......................................................................................................241 24.2 i/o lines description ........................................................................................241 24.3 application example .........................................................................................242 24.4 product dependencies .....................................................................................244
v 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 24.5 functional description ......................................................................................246 24.6 sdram controller (sdramc) user interface .................................................253 25 error corrected code cont roller (ecc) ...... .............. .............. ........... 263 25.1 description .......................................................................................................263 25.2 block diagram ..................................................................................................263 25.3 functional description ......................................................................................263 25.4 error corrected code controller (ecc) user interface ....................................268 25.5 registers for 1 ecc for a page of 512/1024/2048/4096 bytes ........................279 25.6 registers for 1 ecc per 512 bytes for a page of 512/2048/4096 bytes, 8-bit word .......................................................................................................281 25.7 registers for 1 ecc per 256 bytes for a page of 512/2048/4096 bytes, 8-bit word .......................................................................................................289 26 peripheral dma controller (pdc) ................ .............. .............. ........... 305 26.1 description .......................................................................................................305 26.2 block diagram ..................................................................................................306 26.3 functional description ......................................................................................306 26.4 peripheral dma controller (pdc) user interface .............................................309 27 clock generator ................ .............. .............. .............. .............. ........... 317 27.1 description .......................................................................................................317 27.2 clock generator block diagram .......................................................................317 27.3 slow clock crystal oscillator ...........................................................................317 27.4 slow clock rc oscillator .................................................................................318 27.5 slow clock selection ........................................................................................318 27.6 main oscillator .................................................................................................318 27.7 divider and pll block ......................................................................................320 28 power management controller (pmc) .... ................. ................ ........... 322 28.1 description .......................................................................................................322 28.2 master clock controller ....................................................................................323 28.3 processor clock controller ..............................................................................323 28.4 usb clock controller .......................................................................................324 28.5 peripheral clock controller ..............................................................................324 28.6 programmable clock output controller ...........................................................324 28.7 programming sequence ..................................................................................325 28.8 clock switching details ....................................................................................330 28.9 power management controller (pmc) user interface ....................................334
vi 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 29 advanced interrupt controller (aic) ........... .............. .............. ........... 351 29.1 description .......................................................................................................351 29.2 block diagram ..................................................................................................352 29.3 application block diagram ...............................................................................352 29.4 aic detailed block diagram .............................................................................352 29.5 i/o line description ..........................................................................................353 29.6 product dependencies .....................................................................................353 29.7 functional description ......................................................................................354 29.8 advanced interrupt controller (aic) user interface .........................................364 30 debug unit (dbgu) .. ................ ................ ................. ................ ........... 375 30.1 description .......................................................................................................375 30.2 block diagram ..................................................................................................376 30.3 product dependencies .....................................................................................377 30.4 uart operations .............................................................................................377 30.5 debug unit (dbgu) user interface .................................................................384 31 parallel input/output contro ller (pio) ......... .............. .............. ........... 399 31.1 description .......................................................................................................399 31.2 block diagram ..................................................................................................400 31.3 product dependencies .....................................................................................401 31.4 functional description ......................................................................................402 31.5 i/o lines programming example .....................................................................406 31.6 parallel input/output controller (pio) user interface .......................................408 32 serial peripheral interface (spi) ................ ................ .............. ........... 425 32.1 description .......................................................................................................425 32.2 block diagram ..................................................................................................426 32.3 application block diagram ...............................................................................426 32.4 signal description ...........................................................................................427 32.5 product dependencies .....................................................................................427 32.6 functional description ......................................................................................428 32.7 serial peripheral interface (spi) user interface ...............................................438 33 two-wire interface (twi) .... .............. ............... .............. .............. ........ 451 33.1 description .......................................................................................................451 33.2 list of abbreviations .........................................................................................451 33.3 block diagram ..................................................................................................452 33.4 application block diagram ...............................................................................452
vii 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 33.5 product dependencies .....................................................................................453 33.6 functional description ......................................................................................453 33.7 master mode ....................................................................................................455 33.8 multi-master mode ...........................................................................................467 33.9 slave mode ......................................................................................................470 33.10 two-wire interface (twi) user interface ..........................................................478 34 universal synchronous asynchr onous receiver transceiver (usart) ................. ................. ................ ................. ................ ............. 493 34.1 description .......................................................................................................493 34.2 block diagram ..................................................................................................494 34.3 application block diagram ...............................................................................495 34.4 i/o lines description .......................................................................................496 34.5 product dependencies .....................................................................................497 34.6 functional description ......................................................................................498 34.7 universal synchronous asyn chronous recevier transeiver (usart) user interface ...............................................................................529 35 synchronous serial controller (ssc) .... ................. ................ ........... 551 35.1 description .......................................................................................................551 35.2 block diagram ..................................................................................................552 35.3 application block diagram ...............................................................................552 35.4 pin name list ...................................................................................................553 35.5 product dependencies .....................................................................................553 35.6 functional description ......................................................................................553 35.7 ssc application examples ..............................................................................564 35.8 synchronous serial controller (ssc) user interface .......................................567 36 timer counter (tc) ........... .............. .............. .............. .............. ........... 591 36.1 description .......................................................................................................591 36.2 block diagram ..................................................................................................592 36.3 pin name list ...................................................................................................593 36.4 product dependencies .....................................................................................593 36.5 functional description ......................................................................................594 36.6 timer counter (tc) user interface ..................................................................607 37 multimedia card interface (m ci) ........... ................. ................ ............. 625 37.1 description .......................................................................................................625 37.2 block diagram ..................................................................................................626
viii 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 37.3 application block diagram ...............................................................................627 37.4 pin name list ..................................................................................................627 37.5 product dependencies .....................................................................................627 37.6 bus topology ...................................................................................................628 37.7 multimedia card operations ............................................................................631 37.8 sd/sdio card operations ...............................................................................639 37.9 multimedia card interface (mci) user interface ..............................................640 38 ethernet mac 10/100 (emac) .. ............... ................. ................ ........... 661 38.1 description .......................................................................................................661 38.2 block diagram ..................................................................................................661 38.3 functional description ......................................................................................662 38.4 programming interface .....................................................................................674 38.5 ethernet mac 10/100 (emac) user interface .................................................677 39 usb device port (udp) ....... .............. ............... .............. .............. ........ 715 39.1 description .......................................................................................................715 39.2 block diagram ..................................................................................................716 39.3 product dependencies .....................................................................................716 39.4 typical connection ...........................................................................................718 39.5 functional description ......................................................................................719 39.6 usb device port (udp) user interface ............................................................734 40 usb host port (uhp) ........ .............. .............. .............. .............. ........... 753 40.1 description .......................................................................................................753 40.2 block diagram ..................................................................................................753 40.3 product dependencies .....................................................................................754 40.4 functional description ......................................................................................754 40.5 typical connection ...........................................................................................756 41 image sensor interface (isi) ............. ............... .............. .............. ........ 757 41.1 overview ..........................................................................................................757 41.2 block diagram ..................................................................................................758 41.3 functional description ......................................................................................758 41.4 image sensor interface (isi) user interface ....................................................767 42 analog-to-digital converte r (adc) ....... ................. ................ ............. 787 42.1 description .......................................................................................................787 42.2 block diagram ..................................................................................................787
ix 6254b?atarm?29-apr-09 at91sam9xe128/256/512 preliminary 42.3 signal description ............................................................................................788 42.4 product dependencies .....................................................................................788 42.5 functional description ......................................................................................789 42.6 analog-to-digital converter (adc) user interface ...........................................794 43 at91sam9xe128/256/512 electri cal characteristics .. ............. ........ 807 43.1 absolute maximum ratings .............................................................................807 43.2 dc characteristics ...........................................................................................808 43.3 power consumption .........................................................................................810 43.4 clock characteristics .......................................................................................812 43.5 crystal oscillator characteristics .....................................................................814 43.6 adc ..................................................................................................................818 43.7 usb transceiver characteristics .....................................................................819 43.8 core power supply por characteristics .........................................................820 43.9 power-up sequence .........................................................................................820 43.10 power-down sequence ....................................................................................820 43.11 embedded flash characteristics .....................................................................821 43.12 smc timings ....................................................................................................822 43.13 sdramc ..........................................................................................................826 43.14 emac timings .................................................................................................828 43.15 peripheral timings ...........................................................................................831 44 at91sam9xe128/256/512 mechanical char acteristics ..... ............... 840 44.1 package drawings ...........................................................................................840 44.2 soldering profile ...............................................................................................843 45 at91sam9xe128/256/512 ordering informat ion ............... ............... 844 46 at91sam9xe128/256/512 errata ............... ................ .............. ........... 845 46.1 marking ............................................................................................................845 46.2 at91sam9xe128/256/512 errata - revision a parts ......................................846 revision history.......... ................ ................. ................ .............. ........... 853 table of contents.......... ................. ................ ................. ................ ........... i
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